JPH06281957A - Active matrix liquid crystal display device - Google Patents

Abstract

PURPOSE:To provide the active matrix liquid crystal display device which can be manufactured by a small number of times of etching and can improve productivity. CONSTITUTION:Inside the same layer on an insulated substrate 36, mutually orthogonally intersecting gate line 37, signal line 38, gate electrode 39, drain electrode 40, spare capacity line, spare capacity electrode 41 and source electrode 42 are formed by etching. At the intersecting part of the gate line 37 and the signal line 38, the gate line 37 is divided so as not to be in contact with the signal line 38 and covered by a gate insulating layer 43 and afterwards, connection 52, 53 and 54 of through holes are formed at both parts corresponding to the gate electrode 39 and the source electrode 42 and a part corresponding to the divided terminal part. When forming a picture element electrode, a gap between the source electrode 42 and a picture element electrode 51, a gap between the gate are source electrodes 39 and 42 and an ormic contact layer 49 and a gap between the disconnected lines are connected through the connection parts 52, 53 and 54 by any picture element electrode material, respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device having pixel electrodes.

[0002]

2. Description of the Related Art In recent years, liquid crystal display devices are required to have a high contrast, and an active matrix type has been widely used as a drive control system for each pixel. A typical example of an active element used in such an active matrix type liquid crystal display device is a thin film transistor having a semiconductor active layer made of amorphous silicon or polycrystalline silicon.

In FIG. 18, an active element has an etching stopper layer, and an ohmic contact layer is formed by plasma CVD (Chemical Vapor Deposition).
1 shows a conventional active matrix type liquid crystal display device using an inverted staggered type silicon thin film transistor formed by a method.

In FIG. 18, the active matrix type liquid crystal display device is composed of a first substrate 12 and a second substrate 13 which are opposed to each other with a liquid crystal layer 11 interposed therebetween. Is configured as follows.

First, 15 is an insulating substrate made of glass or the like having a light-transmitting property. On the upper surface of the insulating substrate 15, a gate line (not shown) and a gate electrode 16 integral therewith, an auxiliary capacitance line parallel to the gate line, and An auxiliary capacitance electrode 17 integrated with this auxiliary capacitance line is formed. A plurality of gate lines and storage capacitance lines (not shown) corresponding to the number of pixels are formed in a direction perpendicular to the paper surface. In addition, the auxiliary capacitance electrode 17 is arranged near the gate electrode 16.

A gate insulating layer 18 is laminated on the insulating substrate 15 on which the gate line, the auxiliary capacitance line, the gate electrode 16, and the auxiliary capacitance electrode 17 are formed, and the gate insulating layer 18 is formed.
A semiconductor layer 19 is laminated and formed in a predetermined area including the gate electrode 16. In addition, an etching protection layer 20 is laminated on the semiconductor layer 19 in a range corresponding to a part of the gate electrode 16. Further, on the portion of the semiconductor layer 19 other than the etching protection layer 20, the ohmic contact layer 21 separated on the upper surface of the etching protection layer 20 as illustrated is formed.

Also, an auxiliary capacitance electrode on the gate insulating layer 18
A pixel electrode 22 is laminated and formed in a predetermined range including a portion corresponding to above 17, and a source electrode 23 is laminated and formed between the pixel electrode 22 and a right side portion of the ohmic contact layer 21. Further, on the left side portion of the ohmic contact layer 21, a drain electrode 24 integrated with a signal line (not shown) formed on the gate insulating layer 18 is laminated.
The signal lines are formed in a direction parallel to the plane of the drawing, that is, orthogonal to each other with the gate line and the gate insulating layer 18 interposed therebetween. Further, the gate electrode 16, the source electrode 23,
The thin film transistor including the drain electrode 24 is formed at each intersection of the gate line and the signal line, and charges the pixel electrode 22 by the ON operation.

Further, each part except the pixel electrode 22 is an inorganic protective layer.
The pixel electrode 22 is entirely covered with the alignment film 26. As shown in FIG. 18B, a through hole 27 is formed in the outer lead electrode portion formed on the edge portion of the insulating substrate 15 by removing the insulating film formed on the upper surface.

A second substrate 13 having a counter electrode 31 and an alignment film 32 laminated on a counter substrate 30 made of glass or the like is arranged so as to face the first substrate 12 thus formed. A liquid crystal layer 11 is injected between the second substrate 12 and the second substrate 13, and a polarizing plate 33 is provided on the outer surfaces of the first substrate 12 and the second substrate 13, respectively, to form an active matrix type liquid crystal display device. To be done.

Next, a method of manufacturing the first substrate 12 will be described. First, a metal film is formed on the insulating substrate 15 made of glass or the like by sputtering or a vacuum vapor deposition method, and then the gate line, the auxiliary capacitance line and the gate electrode are etched.
16, formed in a predetermined shape corresponding to the auxiliary capacitance electrode 17.

Next, for example, silicon nitride (SiN _x ) is used for the gate insulating layer 18 and a- is used for the semiconductor layer 19 by plasma CVD or the like.
Si and SiNx for the etching protection layer 20 are sequentially laminated. After that, SiN _x for the etching protection layer 20 located on the uppermost surface is etched to form the etching protection layer 20 on the gate electrode 16.

Next, a low resistance semiconductor layer, for example, an n-type a-Si layer is formed as a layer for the ohmic contact layer 21 by the plasma CVD method. After that, etching is performed so that the ohmic contact layer 21 and the semiconductor layer 19 are formed in a predetermined range including the upper surface of the gate electrode 16.

Further, a transparent electrode material such as ITO (Indium Tin) is formed by sputtering or vacuum deposition.
Oxide) is laminated and the ITO is further etched to form a transparent pixel electrode 22. Moreover, as shown in FIG. 18B, the insulating substrate
The film covering the extraction electrode at the edge of 15 is removed, and a through hole 27 is formed.

Next, after laminating a metal film such as aluminum by sputtering or vacuum deposition, etc., the signal line and the drain electrode 24 integral with the signal line,
The source electrode 23 connected to part of the pixel electrode 22 is formed by etching the metal film. After this,
The ohmic contact layer 21 between the source electrode 23 and the drain electrode 24 is etched and removed.

Next, a protective inorganic protective layer 25 made of, for example, SiN _x is laminated by the plasma CVD method. Then, by etching, the inorganic protective layer 25 is removed from the pixel electrodes 22 and the through holes 27 as illustrated.

In this way, the first substrate 12, which is a main part of the active matrix type liquid crystal display device using the silicon type thin film transistor, is manufactured. By the way, before each etching process described above, PEP (Photo Engraving) is performed.
There is an exposure process called Process). In this exposure step, a mask is used to form a pattern of photoresist on the substrate. In the conventional manufacturing method, seven masks are used and PEP is performed seven times.

However, the number of masks used, that is, P
When the number of EPs increases, production costs such as material costs and labor costs increase, the degree of occurrence of defects due to PEP failure or dust increases, and the yield decreases.

Therefore, it is difficult to improve the productivity by the conventional manufacturing method in which PEP is repeated seven times. However, some thin film transistors do not have the etching protection layer 20, and in this case, the number of masks used is six. Further, even if the etching protection layer 20 is provided, when the ohmic contact layer 21 is formed by the ion implantation method, the number of masks used is still six.

In any case, however, the number of times of PEP is large in the conventional manufacturing method, and how to reduce the PEP and increase the productivity is a big problem.

[0020]

As described above, in the conventional active matrix type liquid crystal display device, it is difficult to improve the productivity due to the large number of PEPs in manufacturing the first substrate which is the main part of the conventional active matrix type liquid crystal display device. There is a problem.

An object of the present invention is to provide an active matrix type liquid crystal display device in which the main part where the pixel electrode is provided can be manufactured with a smaller number of PEPs than the conventional one and the productivity can be improved. is there.

[0022]

An active matrix type liquid crystal display device of the present invention includes a first substrate having a pixel electrode, and a first substrate which is arranged with a liquid crystal layer interposed therebetween and faces the pixel electrode. A second substrate provided with an electrode is provided, wherein the first substrate is formed by etching a metal film deposited on an insulating substrate having a light-transmitting property, and intersects each other and at any one of the intersections. A gate line and a signal line that are divided so that one does not come into contact with the other, a gate electrode that is integral with the gate line and a drain electrode that is integral with the signal line, an auxiliary capacitance line parallel to the gate line, and an integral capacitance line. Of the auxiliary capacitance electrode, the source electrode located near the gate electrode, and the drain electrode and the source electrode, which are stacked on the insulating substrate on which the electrodes are formed. Part of the gate insulating layer and the end portion divided at the intersecting portion are stacked on the gate insulating layer which is removed by etching so as to be exposed, and are formed by etching so as to cover the gate electrode. A semiconductor layer, an ohmic contact layer formed on the semiconductor layer and having an opening exposing a part of an upper surface of the semiconductor layer, and an ohmic contact layer formed on the gate insulating layer including the ohmic contact layer. A pixel electrode formed by etching the formed transparent electrode material and located near the source electrode, a connection portion between the exposed portion of the pixel electrode and the source electrode and an ohmic contact layer, and an exposed portion of the drain electrode and the ohmic contact. Except for the connection portion with the contact layer, the connection portion between the exposed end portions of the intersecting portion, and the pixel electrode portion It is obtained by including an inorganic protective layer formed to cover the body.

[0023]

According to the present invention, a gate line and a signal line intersecting with each other, a gate electrode integral with the gate line and a drain electrode integral with the signal line, an auxiliary capacitance line parallel to the gate line, and an auxiliary capacitance integral with the auxiliary capacitance line. Each of the capacitor electrode and the source electrode is formed in the same layer on the insulating substrate by etching, and at the intersection of the gate line and the signal line, one of the intersecting lines is divided so as not to contact the other. And after covering the signal line with the gate insulating layer, through holes are formed in the gate insulating layer, the portion corresponding to the gate electrode and the source electrode, and the portion corresponding to the tip of the divided line. At the time of forming the pixel electrode, the source electrode and the pixel electrode, the gate electrode and the source electrode, and the ohmic contact are formed through the through hole by the pixel electrode material. Between the corresponding portions of the transfected layer, the inter-shed line, since to be connected respectively, can be reduced compared with the conventional etching times, as a result,
Productivity can be improved.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an active matrix type liquid crystal display device of the present invention will be described below with reference to the drawings. In addition,
The parts corresponding to the conventional example shown in FIG.

As shown in FIG. 1, the active matrix type liquid crystal display device comprises a first substrate 35 and a second substrate 13 which face each other with a liquid crystal layer 11 in between, and the first substrate 35.
Is configured as follows.

Reference numeral 36 is a transparent insulating substrate made of glass or the like. On the upper surface of the insulating substrate 36, a plurality of gate lines 37 and a plurality of signal lines 38 which are orthogonal to each other are provided. The gate line 37 and the signal line 38 are shown in FIG.
As shown in (c) and FIG. 2, one of the intersections, for example, the signal line 38 is divided so as not to contact the other, for example, the gate line 37 at the intersection.

Further, on the upper surface of the insulating substrate 36, a gate electrode 39 integrated with the gate line 37, a drain electrode 40 integrated with the signal line 38, an auxiliary capacitance line and an auxiliary capacitance line (not shown) parallel to the gate line 37 are provided. Integrated auxiliary capacitance electrode 41, gate electrode
Source electrodes 42 located near 39 are respectively formed.

Further, these gate electrode 39 and drain electrode
The gate electrode 39 and the drain electrode 40 are formed on the insulating substrate 36 on which the auxiliary capacitance electrode 41, the source electrode 42 and the like are formed.
A gate insulating layer 43 is laminated so as to cover 40, the auxiliary capacitance electrode 41, and the source electrode 42. This gate insulation layer 43
Of the drain electrode 40 and the source electrode 42, and a through portion for contact by etching so that a portion corresponding to the end portion of the signal line 38 divided at the intersection portion is exposed. The holes 44, 45 and 46 are formed.

Further, 47 is a semiconductor layer, and this semiconductor layer 47
Is laminated on the gate insulating layer 43 and is formed by etching in a range covering the gate electrode 39. In addition, this semiconductor layer 47
An etching protection layer 48 is provided at a position corresponding to the center of the gate electrode 39. Further, an ohmic contact layer 49 is laminated on the semiconductor layer 47 including the etching protection layer 48, and the ohmic contact layer 49 has an opening 50 for exposing a part of the upper surface of the etching protection layer 48.

Further, 51 is a pixel electrode, and this pixel electrode 51 is formed near the source electrode 42 by etching the transparent electrode material laminated on the gate insulating layer 43 including the ohmic contact layer 49. Further, at this time, the above-described etching simultaneously forms a connecting portion 52 between the ohmic contact layer 49 and a part of the source electrode 42 exposed by the pixel electrode 51 and the through hole 45. Further, a connecting portion 53 between a part of the drain electrode 40 exposed by the through hole 44 and the ohmic contact layer 49, and a connecting portion 54 between the interrupted ends exposed by the through hole 46 at the intersection are also formed.

Then, a metal layer 55 is formed on the upper surface of each of the connecting portions 52, 53, 54 except for the pixel electrode 51 portion formed of the transparent electrode material.
Are laminated, the inorganic protective layer 56 is formed so as to cover the entire portion except the pixel electrode 51 portion, and the alignment film 57 is laminated so as to cover the entire portion including the pixel electrode 51 portion.

A through hole 58 is formed in the outer lead electrode portion formed on the edge of the insulating substrate 36, from which the insulating film formed on the upper surface is removed.

The second substrate 13 in which the counter electrode 31 and the alignment film 32 are laminated and formed on the counter substrate 30 made of glass or the like is disposed so as to face the first substrate 35 thus formed. A liquid crystal layer 11 is injected between the substrate 35 and the second substrate 13, and a polarizing plate 33 is provided on the outer surfaces of the first substrate 35 and the second substrate 13, respectively, to form an active matrix type liquid crystal display device. To be done.

Next, a method of manufacturing the first substrate 35 having the above structure will be described with reference to FIGS.

First, as shown in FIG. 3, molybdenum tantalum (MoT) is sputtered on the insulating substrate 36.
a) Deposit the alloy film 61 to about 2000 angstroms.

After that, the photoresist is patterned by using a first mask (not shown), and by CF4 dry etching, as shown in FIG. 4, the gate line 37, the signal line 38, the gate electrode 39, and the drain electrode are formed. 40, auxiliary capacitance electrode
41 and the source electrode 42 are formed in the same etching process.
At the intersection of the gate line 37 and the signal line 38, as shown in FIG.
As shown in (c), one signal line 38 is divided so as not to contact the other gate line 37.

The insulating substrate 36 on which the gate line 37, the signal line 38, the gate electrode 39, the drain electrode 40, the auxiliary capacitance electrode 41, and the source electrode 42 are formed in this manner is connected to a plasma C (not shown).
After being inserted into a vacuum chamber of a VD (Chemical Vapor Deposition) apparatus and the inside of the vacuum chamber being sufficiently evacuated, the insulating substrate 36 is heated to about 350 ° C. by a heater panel (not shown). In this state, a source gas for the gate insulating layer 43 made of SiN _x is introduced from a cylinder (not shown) into the vacuum chamber of the plasma CVD apparatus. That is, as the raw material gas, silane 50 sccm, ammonia 200 sccm, nitrogen 1
000 sccm is introduced into each of the vacuum chambers. Then, the pressure inside the vacuum chamber is adjusted to 0.5 Torr, and a high-frequency oscillator (not shown) is applied to supply a power density of 0.50 W / cm ² to generate plasma, and the plasma is generated on the insulating substrate 36 as shown in FIG. About 20 gate insulating layer film 62 made of SiN _x
About 00 angstrom is laminated.

After stacking the gate insulating layer film 62, gas introduction from the cylinder is temporarily stopped, the vacuum chamber of the plasma CVD apparatus is sufficiently evacuated, and the insulating substrate 36 is heated to about 300 ° C. by the heater panel. To do. Thereafter, 200 sccm of silane and 800 sccm of hydrogen, which are the source gases of the semiconductor layer 47 made of a-Si, are introduced into the vacuum chamber of the plasma CVD apparatus from the corresponding cylinders. Then, the pressure is set to 0.
Adjusted to 5 Torr, 0.30 power density by high frequency oscillator
Insulating substrate 36 is generated by introducing W / cm ² to generate plasma.
Of the semiconductor layer film made of a-Si on the gate insulating layer film 62 of
63 is laminated to form about 500 angstroms.

After the semiconductor layer 47 made of a-Si is formed in this manner, the introduction of gas from the cylinder is temporarily stopped, the vacuum chamber of the plasma CVD apparatus is sufficiently evacuated, and insulation is performed by the heater panel. Substrate 36 is heated to about 200 ° C. After that, silane 50 sccm and ammonia 200 scc, which are the source gas of the etching protection layer 48 made of SiN _x , are used.
m and 1000 sccm of nitrogen are introduced into the vacuum chamber of the plasma CVD apparatus from the corresponding cylinders. Then, the pressure is adjusted to 0.5 Torr, a power density of 1.0 W / cm ² is applied by a high frequency oscillator to generate plasma, and the etching protection layer film 64 made of SiN _{x is formed} on the semiconductor layer 47 of the insulating substrate 36. Is laminated to form about 2000 angstroms.

After the etching protection layer 48 made of SiNx is formed in this manner, the insulating substrate 36 is taken out from the vacuum chamber of the plasma CVD apparatus, and the photoresist is patterned using the second mask. . After that, the etching protection layer film 64 is etched with an etching solution, and a part of the etching protection layer film 64 is removed as shown in FIG.
It is processed into a desired shape so as to remain as an etching protection layer 48 on 39.

Next, the insulating substrate 36 is placed in the vacuum chamber of the plasma CVD apparatus again, the inside of the vacuum chamber is sufficiently evacuated, and the insulating substrate 36 is heated to about 200 ° C. by the heater panel. Thereafter, 20 sccm of silane, 100 sccm of phosphine, and 800 sccm of hydrogen, which are source gases for the ohmic contact layer 49 made of n-type a-Si, are introduced into the vacuum chamber of the plasma CVD apparatus from the corresponding cylinders.
Then, the pressure is adjusted to 0.5 Torr, and a high frequency oscillator is used to apply a power density of 0.60 W / cm ² to generate plasma, and as shown in FIG. 7, on the etching protection layer 48 of the insulating substrate 36 and this etching. On the semiconductor layer 47 from which the protective layer 48 has been removed by etching, an ohmic contact layer film 65 for forming an ohmic contact layer 49 made of n-type a-Si is laminated in a thickness of about 500 Å.

After the ohmic contact layer film 65 made of n-type a-Si is formed in this manner, the insulating substrate is formed.
36 is taken out from the vacuum chamber of the plasma CVD apparatus,
As shown by, a molybdenum metal film 66 is formed on the surface of the ohmic contact layer film 65 by sputtering to have a thickness of about 500 Å. Then, after this, the molybdenum metal film 66 is entirely removed by etching with an etching solution. As a result, the alloy layer 67 of silicon and molybdenum remains on the surface of the ohmic contact layer 49, as shown in FIG.

The photoresist is then patterned using the third mask. After that, the ohmic contact layer film 65 and the semiconductor layer film 63 are etched with an etching solution so that the ohmic contact layer 49 and the semiconductor layer 47 remain on a predetermined range including the gate electrode 39 as shown in FIG. , Process it into the desired shape.

The photoresist is then patterned using the fourth mask. Then, as shown in FIG. 11, the gate insulating layer film 62 on the drain electrode 40 and the source electrode 42 is removed by etching with an etching solution to form through holes 44 and 45 for contacts. At the same time, as shown in FIG. 11B, a part of the gate insulating layer 43 on the external extraction electrode is removed by etching to form a through hole 58. Further, as shown in FIG. 11C, at the intersections of the gate lines 37 and the signal lines 38, the gate insulating layers corresponding to these positions are exposed so that the ends of the divided signal lines 38 are exposed. 43 is etched away to form a through hole 46 for contact.

Then, ITO (Indium) which is a material for the pixel electrode 51 which is transparent by sputtering is formed on these surfaces.
Tin Oxide) film 68, as shown in FIG.
A stack of about angstroms is formed. Thereafter, a molybdenum-tantalum-alloy film 69 is laminated on the surface of the ITO film 68 by sputtering to a thickness of about 2000 angstroms.

The photoresist is then patterned using the fifth mask. Thereafter, in the same pattern, first, the molybdenum tantalum alloy film 69 is dry-etched, and then the ITO film is etched using an etching solution.
Etch 68 respectively.

Here, the etching pattern with the same pattern is such that the metal layer 55 made of a molybdenum tantalum alloy film and the ITO film 68 remain as the shape of the pixel electrode 51 near the source electrode 42 as shown in FIG. This pixel electrode
Forming a connection portion 52 between the ohmic contact layer 49 and a part of the source electrode 42 exposed by the 51 and the through hole 45,
Furthermore, the drain electrode exposed by the through hole 44
A connection portion 53 between a part of 40 and the ohmic contact layer 49 is formed. However, at this time, the portions of the metal layer 55 and the ITO film 68 located on the gate electrode 39 are removed by etching.

As shown in FIG. 14B, the pattern is that the molybdenum tantalum alloy film 69 is formed in the through hole 58.
Also, the ITO film 68 remains, and further, as shown in FIG. 14C, the connection portion 54 between the interrupted end portions exposed by the through hole 46 is formed at the intersecting portion.
However, it is not necessary to leave the metal layer 55 and the ITO film 68 in the through hole 58 depending on the kind of metal stacked on the gate line 37 and the pixel electrode 51.

Then, by dry etching, as shown in FIG. 15, the gate electrode of the ohmic contact layer 49 is formed.
The portion above 39 is etched away to form an opening 50.

Further, the insulating substrate 36 is again subjected to plasma CVD.
It is installed in the vacuum chamber of the equipment, and after the vacuum chamber is sufficiently evacuated, the insulating substrate 36 is heated to about 200 ° C by the heater panel.
Heat to. After that, silane 50 sccm and ammonia 200 scc which are raw material gases for the inorganic protective layer 56 made of SiN _x.
m and 100 sccm of nitrogen are introduced into the vacuum chamber of the plasma CVD apparatus from the corresponding cylinders. Then, the pressure was adjusted to 0.5 Torr, and a high frequency oscillator was used to apply a power density of 1.0 W / cm ² to generate plasma.
As shown by 6, an inorganic protective layer 56 made of SiNx is laminated on the surface of the insulating substrate 36 to a thickness of about 2000 angstroms.

Next, the photoresist is patterned using the sixth mask. Then, by dry etching, the inorganic protective layer 56 on the pixel electrode 51 and the through hole 58, and the metal layer 55 remaining on the pixel electrode 51,
As shown in FIG. 17, they are removed by etching.

After this, as shown in FIG. 1, an alignment film 57 is formed on these surfaces, and the first substrate 35 is completed. However, in the present embodiment, although not shown, the intersection of the gate line 37 and the auxiliary capacitance line partially interrupts the auxiliary capacitance line, and the intersection of the signal line 38 and the auxiliary capacitance line is the auxiliary capacitance. A part of the line was interrupted, and a structure similar to the intersection of the gate line 37 and the signal line 38 was adopted.

In this way, the first substrate 35, which is the main part of the active matrix type liquid crystal display device, is manufactured. The number of masks used in the manufacturing process is 6
It is a sheet. Of course, as before, the etching protection layer
For thin film transistors without 48, only 5 masks are used. Further, even if the etching protection layer 48 is provided, when the ohmic contact layer 49 is formed by the ion implantation method, the number of masks used is still five. In any case, the number of masks used is reduced by one as compared with the conventional one. As a result, production costs such as material costs and labor costs are reduced, the degree of defects caused by PEP failure, dust, etc. is reduced, yield is improved, and productivity is increased.

Next, Table 1 shows the characteristics of the amorphous silicon thin film transistor A1 of the active matrix type liquid crystal display device manufactured as described above, that is, the field effect mobility and the threshold voltage. For comparison, the characteristics of the amorphous silicon thin film transistor A2 having the same structure and manufacturing method as the conventional one are also shown.

[0055]

[Table 1] As is clear from Table 1, the amorphous silicon thin film transistor used in the active matrix type liquid crystal display device according to the above-mentioned embodiment also shows substantially the same characteristics as the conventional one. That is, in the amorphous silicon thin film transistor used in the device of the above-mentioned embodiment, the number of masks used can be reduced by one from the conventional one, and moreover, the transistor characteristic equivalent to the conventional one can be obtained.

[0056]

According to the active matrix type liquid crystal display device of the present invention, the gate line, the signal line, the gate electrode, the drain electrode, the auxiliary capacitance line, the auxiliary capacitance electrode and the source electrode are formed in the same layer on the insulating substrate. Formed by etching, at the intersection of the gate line and the signal line,
After dividing one of the intersecting portions so that it does not contact the other and covering it with a gate insulating layer, through holes are formed in the portion corresponding to the gate electrode and the source electrode and the portion corresponding to the tip of the divided line. When the pixel electrode is formed, the source electrode and the pixel electrode, the gate electrode and the source electrode and the corresponding portion of the ohmic contact layer, and the separated lines are connected by the pixel electrode material. Therefore, the number of times of etching can be reduced, the production cost such as material cost and labor cost can be reduced, the degree of occurrence of defects can be reduced, and the yield can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of an active matrix type liquid crystal display device according to the present invention. (A) Pixel part (b) External extraction electrode part (c) Crossing part

FIG. 2 is a plan view of the intersection shown in FIG. 1 (c).

FIG. 3 is a cross-sectional view showing one manufacturing step of the main part of the active matrix liquid crystal display device of the same. (A) Pixel part (b) External extraction electrode part (c) Crossing part

FIG. 4 is a cross-sectional view showing the next manufacturing step of FIG. 3 of the main part of the active matrix liquid crystal display device of the same. (A) Pixel part (b) External extraction electrode part (c) Crossing part

FIG. 5 is a cross-sectional view showing the next manufacturing step of FIG. 4 for the main part of the active matrix liquid crystal display device of the same. (A) Pixel part (b) External extraction electrode part (c) Crossing part

FIG. 6 is a cross-sectional view showing the next manufacturing step of FIG. 5 of the main part of the active matrix liquid crystal display device of the same. (A) Pixel part (b) External extraction electrode part (c) Crossing part

FIG. 7 is a cross-sectional view showing the next manufacturing step of FIG. 6 of the main part of the active matrix liquid crystal display device of the same. (A) Pixel part (b) External extraction electrode part (c) Crossing part

FIG. 8 is a cross-sectional view showing the next manufacturing step of FIG. 7 for the main part of the active matrix liquid crystal display device of the same. (A) Pixel part (b) External extraction electrode part (c) Crossing part

9 is a cross-sectional view showing the next manufacturing step of FIG. 8 of the main part of the active matrix liquid crystal display device of the same. (A) Pixel part (b) External extraction electrode part (c) Crossing part

FIG. 10 is a cross-sectional view showing the next manufacturing step of FIG. 9 for the main part of the active matrix liquid crystal display device of the same. (A) Pixel part (b) External extraction electrode part (c) Crossing part

11 is a cross-sectional view showing the next manufacturing step of FIG. 10 of the main part of the active matrix liquid crystal display device same as above. (A) Pixel part (b) External extraction electrode part (c) Crossing part

FIG. 12 is a cross-sectional view showing the next manufacturing step of FIG. 11 of the main part of the active matrix liquid crystal display device of the same as above. (A) Pixel part (b) External extraction electrode part (c) Crossing part

FIG. 13 is a cross-sectional view showing the next manufacturing step of FIG. 12 of the main part of the active matrix liquid crystal display device of the same. (A) Pixel part (b) External extraction electrode part (c) Crossing part

14 is a cross-sectional view showing the next manufacturing step of FIG. 13 of the main part of the active matrix liquid crystal display device of the same. (A) Pixel part (b) External extraction electrode part (c) Crossing part

15 is a cross-sectional view showing the next manufacturing step of FIG. 14 of the main part of the active matrix liquid crystal display device of the same. (A) Pixel part (b) External extraction electrode part (c) Crossing part

16 is a cross-sectional view showing the next manufacturing step of FIG. 15 of the main part of the active matrix liquid crystal display device same as above. (A) Pixel part (b) External extraction electrode part (c) Crossing part

17 is a cross-sectional view showing the next manufacturing step of FIG. 16 of the main part of the active matrix liquid crystal display device same as above. (A) Pixel part (b) External extraction electrode part (c) Crossing part

FIG. 18 is a cross-sectional view showing a conventional active matrix type liquid crystal display device. (A) Pixel part (b) External extraction electrode part

[Explanation of symbols]

 11 Liquid crystal layer 13 Second substrate 31 Counter electrode 35 First substrate 36 Insulating substrate 37 Gate line 38 Signal line 39 Gate electrode 40 Drain electrode 41 Auxiliary capacitance electrode 42 Source electrode 43 Gate insulating layer 47 Semiconductor layer 49 Ohmic contact layer 50 Opening 51 Pixel electrode 52, 53, 54 Connection 56 Inorganic protection layer

Claims (1)

[Claims] 1. A first substrate having a pixel electrode, and
A second substrate is provided on the first substrate via a liquid crystal layer, and a counter electrode for the pixel electrode is provided, and the first substrate is deposited on a translucent insulating substrate. A gate line and a signal line formed by etching a metal film and intersecting each other and divided so that one of them does not come into contact with the other at the intersection, a gate electrode integrated with the gate line and a signal line integrated with the gate line. A drain electrode, an auxiliary capacitance line parallel to the gate line, an auxiliary capacitance electrode integrated with the auxiliary capacitance line, a source electrode located near the gate electrode, and laminated on an insulating substrate on which the electrodes are formed, And,
A part of the drain electrode and the source electrode and an end portion divided at the intersecting portion are removed by etching so as to be exposed, and a gate insulating layer is laminated on the gate insulating layer to form the gate electrode. A semiconductor layer formed by etching in a range to cover, an ohmic contact layer formed on the semiconductor layer and having an opening exposing a part of an upper surface of the semiconductor layer, and the ohmic contact layer including the ohmic contact layer. A pixel electrode formed by etching a transparent electrode material laminated on the gate insulating layer and located near the source electrode, a connecting portion between the exposed portion of the pixel electrode and the source electrode and an ohmic contact layer, and a drain electrode Between the exposed portion and the ohmic contact layer, between the exposed interrupted end portions of the intersecting portion And connection portion, an active matrix type liquid crystal display device being characterized in that comprising an inorganic protective layer formed to cover the whole body except the pixel electrode portion.