JPH05503812A - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing methodInfo
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- JPH05503812A JPH05503812A JP50384891A JP50384891A JPH05503812A JP H05503812 A JPH05503812 A JP H05503812A JP 50384891 A JP50384891 A JP 50384891A JP 50384891 A JP50384891 A JP 50384891A JP H05503812 A JPH05503812 A JP H05503812A
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- 239000004065 semiconductor Substances 0.000 title claims description 33
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 40
- 239000000758 substrate Substances 0.000 claims description 35
- 239000010432 diamond Substances 0.000 claims description 29
- 229910003460 diamond Inorganic materials 0.000 claims description 28
- 235000012239 silicon dioxide Nutrition 0.000 claims description 19
- 239000000377 silicon dioxide Substances 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 15
- 239000011159 matrix material Substances 0.000 claims description 8
- 229920001296 polysiloxane Polymers 0.000 claims description 4
- 239000010410 layer Substances 0.000 claims 27
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000002346 layers by function Substances 0.000 claims 1
- 230000005855 radiation Effects 0.000 description 11
- 239000000463 material Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000002285 radioactive effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 208000024891 symptom Diseases 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるため要約のデータは記録されません。 (57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 半導体装置とそれの製造方法 技術分野 本発明は、基板と前記基板上に配置されたシリコンの能動層とを含む半導体装置 であって、前記半導体装置の能動部品か前記能動層中に作製されている半導体装 置に関するものである。[Detailed description of the invention] Semiconductor device and its manufacturing method Technical field The present invention provides a semiconductor device including a substrate and a silicon active layer disposed on the substrate. an active component of the semiconductor device or a semiconductor device fabricated in the active layer; It's about location.
背景の技術 いわゆるＳＯＩ技術によって個別半導体装置や集積回路を製造することか知られ ている。この技術は、装置や回路部品を基板から、あるいは互いに絶縁された形 で作製もしくは使用する場合に大きい柔軟性を与える技術である。この技術に従 えば、電気的に絶縁性の基板上に配置された、通常はシリコンである半導体材料 の層中に回路または装置か作製される。この基板は通常は、例えばシリコンであ る半導体材料の母体の上に、通常は二酸化シリコンである電気的に絶縁性の層か 配置されたもので１ ある。基板と装置／回路との間の十分な電気的絶縁を取る ために、二酸化シリコン層は比較的厚くする必要かあり、典型的には少なくとも １μｍあるいは数μｍの厚さを有している。しかし、二酸化シリコンは熱的な特 性が劣っており、特に熱伝導率か低い。この結果、この種の装置で処理できる電 力か限られる。更に、二酸化シリコンは放射性／を離放射線に敏感である。もし 、この種の装置かそのような放射線に曝されると、酸化物中に正孔−電子対が生 成されて、正孔か酸化物中に留まることから、酸化物層の充電と共に、能動層と 酸化物層との間の接合に表面準位（ｓｕｒｆａｃｅ ５ｔａｔｅ ）か生成ｒる 。これらの現象は両方共に、前記酸化物層上に配置された前記能動層中に作製さ れた装置または回路の機能に対して良くない影響を持つ。一方、ダイヤモンドは 高い熱伝導率と高い熱容量との形で、優れた電気的絶縁能力と優れた熱的特性と を併せ持つことが知られている。従って、基板としてダイヤモンドを採用するこ と、あるいは基板とこの基板上に配置された装置または回路との間の電気的絶縁 を取るためにダイヤモンド層を使用することが提案されている。しかし、そのよ うな回路中の能動的シリコン層とダイヤモンド材料とを直接的に接合することは 、完全には制御されていない表面準位を生じ、能動層中に作製された装置や回路 の機能にとって良くない効果を持ってあろう。Background technology It is well known that individual semiconductor devices and integrated circuits are manufactured using so-called SOI technology. ing. This technology allows devices and circuit components to be isolated from the board or from each other. It is a technology that provides great flexibility when making or using materials. Following this technique For example, a semiconductor material, usually silicon, placed on an electrically insulating substrate A circuit or device is fabricated in the layers. This substrate is typically silicon, for example. an electrically insulating layer, usually silicon dioxide, on top of a matrix of semiconductor material There is one placed. Provide sufficient electrical isolation between the board and the device/circuit For this purpose, the silicon dioxide layer must be relatively thick, typically at least It has a thickness of 1 μm or several μm. However, silicon dioxide has thermal characteristics. It has poor properties, especially its thermal conductivity. As a result, the amount of electricity that can be handled by this type of equipment is Power limited. Furthermore, silicon dioxide is sensitive to radioactive/dispersing radiation. if , when this type of device is exposed to such radiation, hole-electron pairs are created in the oxide. Since the holes remain in the oxide, as the oxide layer charges, the active layer Surface states are generated at the junction between the oxide layer and the oxide layer. . Both of these phenomena occur in the active layer disposed on the oxide layer. have a negative effect on the functioning of the equipment or circuit that is used. On the other hand, diamonds Excellent electrical insulation ability and excellent thermal properties in the form of high thermal conductivity and high heat capacity. It is known to have both. Therefore, it is difficult to use diamond as a substrate. electrical isolation between the substrate and any equipment or circuitry located on it. It has been proposed to use a diamond layer to remove the But that's it Direct bonding of the active silicon layer and diamond material in such a circuit is , devices and circuits fabricated in the active layer that produce surface states that are not completely controlled. This may have a negative effect on the function of
発明の概要 本発明の目的は前節で述べたような半導体装置を得ることてあり、本発明の装置 は高い電力処理能力と優れた耐放射線性とを示し、その中では能動層と絶縁層と の間の界面における完全には制御されていない表面準位の生成という良くない効 果か回避される。Summary of the invention An object of the present invention is to obtain a semiconductor device as described in the previous section, and the device of the present invention exhibits high power handling capacity and excellent radiation resistance, in which the active layer and insulating layer The undesirable effect of not completely controlled surface state generation at the interface between The result is avoided.
更に、本発明の目的はそのような半導体装置を製造するだめの方法を得ることで ある。Furthermore, an object of the present invention is to obtain a method for manufacturing such a semiconductor device. be.
本発明に従う半導体装置と方法とを特徴づけるものは本発明の特許請求の範囲か ら明らかになろう。What characterizes the semiconductor device and method according to the present invention is the scope of the claims of the present invention. It will become clear.
図面の簡単な説明 以下に第１図と第２図とを参照しなから、本発明について詳細に説明する。第１ 図は本発明に従う半導体装置の１つの例を示す。第２図は本発明に従う方法の１ つの例を示す。Brief description of the drawing The invention will now be described in detail with reference to FIGS. 1 and 2. 1st The figure shows one example of a semiconductor device according to the invention. FIG. 2 shows one of the methods according to the invention. Here are two examples.
好適実施例の説明 第１図は本発明に従う半導体装置を示している。この装置は単結晶ノリコンウェ ハの形の基板ｌを有する。前記基板は能動的シリコン層５を支えており、その層 中にはこの装置の能動部品か本質的に既知のようにして作製される。前記能動層 は例えば、０．６μｍの厚さを有する。多分、前記基板は互いに隣合って位置す るいくつかの別々の能動層を搭載している。DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows a semiconductor device according to the invention. This device is a single-crystal Noricon wafer. It has a C-shaped substrate l. Said substrate supports an active silicon layer 5, which layer Some of the active parts of the device are manufactured in a manner known per se. the active layer has a thickness of, for example, 0.6 μm. Presumably, the substrates are located next to each other. It has several separate active layers.
基板と能動層（または複数の能動層）との間に多結晶のダイヤモンド冒３か配置 されて、それが基板と能動層との間に必要な電気的絶縁と分離とを提供する。ダ イヤモンド層３と能動層５との間に、二酸化シリコンの薄い層４か配置される。A polycrystalline diamond layer is placed between the substrate and the active layer (or active layers). , which provides the necessary electrical insulation and separation between the substrate and the active layer. da Between the diamond layer 3 and the active layer 5 a thin layer 4 of silicon dioxide is arranged.
ダイヤモンド層３と基板との間に薄い二酸化ノリコン層２か配置される。この層 は、以下に述へる製造方法において特定の目的を存するものであるか、例えばも し別の製造方法か用いられるのであれば、省略することも可能である。A thin silicon dioxide layer 2 is placed between the diamond layer 3 and the substrate. this layer Does it have a specific purpose in the manufacturing method described below? However, it can be omitted if another manufacturing method is used.
高い耐放射線性を得るために、二酸化シリコン層４はできる限り薄く作られる。In order to obtain high radiation resistance, the silicon dioxide layer 4 is made as thin as possible.
それは、放射線か照射された時に少数の電荷しか層中に生じないことを意味する 。この曹の厚さは望ましい高い耐放射線性を得るために００５μｍを越えるべき てなく、本発明の好適実施例に従えば、この層の厚さは厚くても０．０２μｍで あって、それてあれば非常に優れた耐放射線性が得られる。It means that only a small number of charges are created in the layer when it is exposed to radiation. . The thickness of this coating should exceed 0.05μm to obtain the desired high radiation resistance. According to a preferred embodiment of the invention, this layer has a thickness of at most 0.02 μm. If this is the case, very good radiation resistance can be obtained.
耐放射線性は、二酸化シリコン層を形成するための処理技術として放射線照射に よって生ずる電荷を捕獲する傾向か小さくなるような方法を採用することによっ て更に増大させることができる。そのような適した技術としては、水分を含んだ 酸素ガス中での熱酸化と、それに続く９００°Ｃ以下の温度での、不活性ガス、 例えばＮ２中での熱処理がある。多結晶ダイヤモンド層３の厚さは、望ましい熱 的インピーダンスの観点と、下層基板から能動層への影響の観点とから最適化さ れる。能動層と基板との間の、最適な電力分布を行った熱的インピーダンスを得 るために、層３の厚さは能動層の厚さよりも大きく選ばれるへきであるか、成長 時間と機械的応力とを制限するためには十分小さくなければならない。あまりに 高い電界強度のために、能動層中で降伏か発生することを防止するためには、ダ イヤモンド層の厚さは第１の最小値よりも小さくてはいけない。それは、なかで も基板と能動層との間の、意図する動作電圧に依存する。能動層中の下層の基板 からのいわゆるＭＯ３効果（電界効果）を防止するためには、ダイヤモンド層の 厚さは第２の最小値よりも小さくてはいけない。この値は、なかでも、意図する 動作電圧と、能動層中に誘起される表面電荷の最大許容値とに依存する。最後に 、ダイヤモンド層の厚さは第３の最小値よりも小さくてはいけない。この値は問 題の装置に関して許容される基板への容量結合の最大値に依存する。これら３つ の、上述の最小値のどれか最大となるかということ、すなわちダイヤモンド層の 最も小さい許容厚さを決定するものがとれになるかということは、意図する動作 電圧と、能動層中に作製される回路／装置の型とに依存することになる。能動層 中に作製された回路か低電圧動作の高速ＣＭＯＳ回路を含んでいるような本発明 の１つの応用においては、ダイヤモンド層３の厚さは約１μｍにすればよいこと が分かった。本発明の別の応用では、能動層中に作製された装置が約１Ｏ００ポ ルトの動作電圧用のスイッチングトランジスタであり、ダイヤモンド層の厚さと しては約ＩＯμｍか適当であることか分かった。最初に述べた例では、この制限 を与える値かＭＯ３効果と電気容量を回避するための最適値で決まり、また第２ の例では、この制限を与える値か能動層中ての降伏を回避する要求によって決定 される。Radiation resistance is based on radiation irradiation as a processing technique to form a silicon dioxide layer. By adopting a method that reduces the tendency to trap the resulting charge, can be further increased. Such suitable techniques include thermal oxidation in oxygen gas followed by inert gas at a temperature below 900°C; For example, there is heat treatment in N2. The thickness of the polycrystalline diamond layer 3 is determined by the desired thermal Optimized from the viewpoint of physical impedance and the influence from the lower substrate to the active layer. It will be done. Obtain thermal impedance with optimal power distribution between active layer and substrate. The thickness of layer 3 should be chosen to be larger than the active layer thickness to It must be small enough to limit time and mechanical stress. too much Due to the high field strength, to prevent breakdown from occurring in the active layer, The thickness of the diamond layer must not be less than the first minimum value. That's inside It also depends on the intended operating voltage between the substrate and the active layer. Lower substrate in active layer In order to prevent the so-called MO3 effect (electric field effect) from The thickness must not be less than the second minimum value. This value is, among other things, the intended It depends on the operating voltage and the maximum permissible amount of surface charge induced in the active layer. lastly , the thickness of the diamond layer must not be less than the third minimum value. This value is It depends on the maximum capacitive coupling to the substrate that is allowed for the device in question. these three Which of the above minimum values is the maximum, that is, the value of the diamond layer What determines the smallest allowable thickness is the intended behavior. It will depend on the voltage and the type of circuit/device fabricated in the active layer. active layer The present invention may include circuits fabricated therein or high speed CMOS circuits with low voltage operation. In one application, the thickness of the diamond layer 3 may be approximately 1 μm. I understand. In another application of the invention, the device fabricated in the active layer has approximately 1000 points. It is a switching transistor for the normal operating voltage, and the thickness of the diamond layer It was found that approximately IO μm was appropriate. In the first mentioned example, this limit The value that gives In the example, the value giving this limit is determined by the requirement to avoid breakdown in the active layer. be done.
上に述へた実施例では、基板はシリコンを含んでいる。In the embodiments described above, the substrate comprises silicon.
このことは基板か能動層と同じ熱膨張係数を持ち、そのため温度か変化した場合 に能動層にかかる機械的応力か最小化されることから望ましいことである。更に 、シリコンは優れた熱伝導率を有し、このことは能動層から熱を効率よく除去す るためには重要であり、またそれによってこの層中に作製される装置や回路に対 して大きい電力負荷か許容できることから重要である。しかしこれとは異なるも のとして、基板はその他の材料、例えはサファイヤを含むこともてきる。This means that the substrate or active layer has the same coefficient of thermal expansion, so if the temperature changes This is desirable because it minimizes the mechanical stress placed on the active layer. Furthermore , silicon has excellent thermal conductivity, which means it can efficiently remove heat from the active layer. This layer is important for the This is important because it allows large power loads to be tolerated. But this is different As such, the substrate may also include other materials, such as sapphire.
上に述へた実施例において、ダイヤモンド層は多結晶であったか、別の方法とし て単結晶であってもよい。In the examples described above, the diamond layer was polycrystalline or otherwise It may also be a single crystal.
本発明に従う半導体装置では、ダイヤモンド材料の高い熱伝導率と熱容量とのた めに、能動層中に作製された装置／回路において非常に優れた電力処理能力が得 られる。この広いダイナミックレンジに亘る電力処理能力は、従来技術の典型的 な回路の２倍から数倍も大きいものである。更に、放射線が照射された時に生ず る電荷を捕獲する傾向がダイヤモンドは小さいためと、二酸化シリコン層の厚さ か薄いためとによって非常に優れた耐放射線性か得られる。更に、ダイヤモンド 層と能動層との間に配置された薄い二酸化シリコン層のために、基板に面する能 動層の界面の制御されない表面準位が能動層に及ぼす影響と、能動層と基板との 間に配置された絶縁層中の電荷効果が能動層に及ぼす影響とか低減する。In the semiconductor device according to the present invention, due to the high thermal conductivity and heat capacity of diamond material, Therefore, very good power handling capability can be obtained in devices/circuits fabricated in the active layer. It will be done. This power handling capability over a wide dynamic range is typical of conventional technology. It is twice to several times larger than a conventional circuit. Furthermore, the symptoms that occur when radiation is applied Diamond tends to trap charge due to its small size and the thickness of the silicon dioxide layer. Due to its thinness, very good radiation resistance can be obtained. Furthermore, diamond Due to the thin silicon dioxide layer placed between the active layer and the active layer, the active layer faces the substrate. The influence of uncontrolled surface states at the interface of the active layer on the active layer and the relationship between the active layer and the substrate The influence of charge effects in the intervening insulating layer on the active layer is reduced.
第２ａ図から第２ｆ図は、本発明に従う半導体装置の生産のための好適な方法に おける複数の引き続く工程を示している。生産の出発点は第２ａ図に示された単 結晶シリコンの母体Ａである。完成した装置における基板に面する側の母体への 表面に、第２ｂ図に示されたように、例えば酸素の存在下での熱処理によって二 酸化シリコン層４か取り付けられる。第２Ｃ図はどのようにして二酸化シリコン 層４の上に多結晶ダイヤモンド層３か取り付けられるかを示しており、それは例 えばＣＶＤ （化学蒸着法）や、゛プラズマジェット法の助けによって行われる 。Figures 2a to 2f illustrate a preferred method for producing a semiconductor device according to the present invention. 1 shows several successive steps in the process. The starting point for production is the unit shown in Figure 2a. This is a matrix A of crystalline silicon. To the mother body on the side facing the board in the completed device 2b, for example by heat treatment in the presence of oxygen. A silicon oxide layer 4 is applied. Figure 2C shows how silicon dioxide It shows whether a polycrystalline diamond layer 3 is installed on top of layer 4, which is shown in the example For example, it is carried out with the help of CVD (chemical vapor deposition) or plasma jet method. .
第２ｄ図は層３の上にどのようにしてシリコンの薄い層２を取り付けるかを示し ており、それは例えばＣＶＤ法の助けによって行われる。後に続くホンディング において良い結果を得るように、層２の表面は研磨および／または研削され、表 面に優れた平坦性と平滑性とが持たせられる。第２ｅ図は母体Ａかとのようにし て層２を基板１の表面に対して結合されるかを示している。後の熱処理によって 、層２は、例えば熱ボンディングによって基板へ接着される。その後、第２ｆ図 に示されたように、第２ｆ図の母体への上側のかなりの部分か、例えばエツチン グによって除去され、能動装置や回路をその中に作製するために適した厚さを持 つ能動層５か残される。最後に、層５中に望みの能動装置または回路が本質的に 既知のようにして作製され、その後必要な接続要素か形成され、そして装置のカ プセル封止か行われる。Figure 2d shows how to apply a thin layer of silicone 2 on top of layer 3. This is done, for example, with the aid of CVD methods. Honding that follows The surface of layer 2 is polished and/or ground to obtain good results in The surface has excellent flatness and smoothness. Figure 2e is as if it were parent body A. 2 shows how layer 2 is bonded to the surface of substrate 1. by subsequent heat treatment , layer 2 is adhered to the substrate, for example by thermal bonding. Then, Fig. 2f As shown in FIG. removed by molding and has a thickness suitable for fabricating active devices and circuits therein. One active layer 5 is left. Finally, in layer 5 the desired active device or circuitry is essentially fabricated in a known manner, after which the necessary connecting elements are formed and the device cover is Psel sealing is performed.
Ｆｉｇ、２８ 〜．２ｂ Ｆｉｇ、 ２ｃ Ｆｉｇ、 ２６ Ｆｉｇ、 ２ｅ 〜、２ｆ 要約書 半導体装置は、基板と、前記基板上に配置されたシリコンの能動層（５）とを含 み、前記能動層中に前記装置の能動部品か作製される。基板（１）と能動層（５ ）との間にダイヤモンド層（３）か配置され、前記ダイヤモンド層と前記能動層 との間に二酸化シリコンの層（４）か配置される。Fig, 28 ~． 2b Fig, 2c Fig, 26 Fig, 2e ~, 2f abstract The semiconductor device includes a substrate and a silicon active layer (5) disposed on the substrate. Then, active parts of the device are fabricated in the active layer. Substrate (1) and active layer (5 ), a diamond layer (3) is disposed between the diamond layer and the active layer. A layer of silicon dioxide (4) is placed between the two.
国際調査報告 ＋−ｗｎｍ−＋ｂ−１．＋−ｉｉ Ｌ ＰＣＴ／ＳＥ ９１１０（１０２９国際 調査報告 ＰＣＴ／ＳＥ ９１１０００２９international search report +-wnm-+b-1. +-ii L PCT/SE 9110 (1029 International Investigation report PCT/SE 91100029
Claims (1)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SE9000245-2 | 1990-01-24 | ||
| SE9000245A SE465492B (en) | 1990-01-24 | 1990-01-24 | Semiconductor component containing a diamond layer arranged between a substrate and an active layer and process prior to its preparation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05503812A true JPH05503812A (en) | 1993-06-17 |
Family
ID=20378335
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50384891A Pending JPH05503812A (en) | 1990-01-24 | 1991-01-17 | Semiconductor device and its manufacturing method |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP0513100A1 (en) |
| JP (1) | JPH05503812A (en) |
| SE (1) | SE465492B (en) |
| WO (1) | WO1991011822A1 (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1993001617A1 (en) * | 1991-07-08 | 1993-01-21 | Asea Brown Boveri Ab | Method for the manufacture of a semiconductor component |
| US5561303A (en) * | 1991-11-07 | 1996-10-01 | Harris Corporation | Silicon on diamond circuit structure |
| US5276338A (en) * | 1992-05-15 | 1994-01-04 | International Business Machines Corporation | Bonded wafer structure having a buried insulation layer |
| DE69225911T2 (en) * | 1992-12-18 | 1999-02-11 | Harris Corp | SILICON ON DIAMOND CIRCUIT STRUCTURE AND PRODUCTION METHOD THEREFOR |
| US5272104A (en) * | 1993-03-11 | 1993-12-21 | Harris Corporation | Bonded wafer process incorporating diamond insulator |
| US5376579A (en) * | 1993-07-02 | 1994-12-27 | The United States Of America As Represented By The Secretary Of The Air Force | Schemes to form silicon-on-diamond structure |
| IT1268123B1 (en) * | 1994-10-13 | 1997-02-20 | Sgs Thomson Microelectronics | SLICE OF SEMICONDUCTOR MATERIAL FOR THE MANUFACTURE OF INTEGRATED DEVICES AND PROCEDURE FOR ITS MANUFACTURING. |
| US6171931B1 (en) | 1994-12-15 | 2001-01-09 | Sgs-Thomson Microelectronics S.R.L. | Wafer of semiconductor material for fabricating integrated devices, and process for its fabrication |
| EP0720223B1 (en) * | 1994-12-30 | 2003-03-26 | STMicroelectronics S.r.l. | Process for the production of a semiconductor device having better interface adhesion between dielectric layers |
| FR2767605B1 (en) * | 1997-08-25 | 2001-05-11 | Gec Alsthom Transport Sa | INTEGRATED POWER CIRCUIT, METHOD FOR MANUFACTURING SUCH A CIRCUIT, AND CONVERTER INCLUDING SUCH A CIRCUIT |
| FR2781082B1 (en) * | 1998-07-10 | 2002-09-20 | Commissariat Energie Atomique | SEMICONDUCTOR THIN-LAYER STRUCTURE HAVING A HEAT-DISTRIBUTING LAYER |
| US20020089016A1 (en) | 1998-07-10 | 2002-07-11 | Jean-Pierre Joly | Thin layer semi-conductor structure comprising a heat distribution layer |
| US6552395B1 (en) * | 2000-01-03 | 2003-04-22 | Advanced Micro Devices, Inc. | Higher thermal conductivity glass for SOI heat removal |
| FR3079662B1 (en) * | 2018-03-30 | 2020-02-28 | Soitec | SUBSTRATE FOR RADIO FREQUENCY APPLICATIONS AND MANUFACTURING METHOD THEREOF |
-
1990
- 1990-01-24 SE SE9000245A patent/SE465492B/en not_active IP Right Cessation
-
1991
- 1991-01-17 WO PCT/SE1991/000029 patent/WO1991011822A1/en not_active Application Discontinuation
- 1991-01-17 JP JP50384891A patent/JPH05503812A/en active Pending
- 1991-01-17 EP EP19910903273 patent/EP0513100A1/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| SE9000245L (en) | 1991-07-25 |
| SE465492B (en) | 1991-09-16 |
| WO1991011822A1 (en) | 1991-08-08 |
| EP0513100A1 (en) | 1992-11-19 |
| SE9000245D0 (en) | 1990-01-24 |
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