WO1993001617A1 - Method for the manufacture of a semiconductor component - Google Patents

Method for the manufacture of a semiconductor component Download PDF

Info

Publication number
WO1993001617A1
WO1993001617A1 PCT/SE1992/000390 SE9200390W WO9301617A1 WO 1993001617 A1 WO1993001617 A1 WO 1993001617A1 SE 9200390 W SE9200390 W SE 9200390W WO 9301617 A1 WO9301617 A1 WO 9301617A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
substrate
diamond layer
silicon
diamond
Prior art date
Application number
PCT/SE1992/000390
Other languages
French (fr)
Inventor
Per Svedberg
Original Assignee
Asea Brown Boveri Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asea Brown Boveri Ab filed Critical Asea Brown Boveri Ab
Publication of WO1993001617A1 publication Critical patent/WO1993001617A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3732—Diamonds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a method for the manufac ⁇ ture of a semiconductor component, said component having a substrate, a diamond layer on said substrate, and at least one active silicon layer on said diamond layer, at least one semiconductor circuit component being formed in said active silicon layer.
  • the component or circuit is formed in a layer of semiconducting material, usually silicon, which layer is arranged on an electrically insulating substrate.
  • This substrate usually is a body of semiconductor material, for instance silicon, having an electrically insulating layer, such as silicon dioxide, upon which the active silicon layer is arranged.
  • the silicon dioxide layer has to be relatively thick, typically at least one or a few ⁇ m. Silicon dioxide does, however, have poor thermal properties, especially a low thermal conductivity.
  • diamond is a material combining good electrical insulation with a high thermal conductivity and a high thermal capacity. It has therefore been proposed to use diamond as a substrate, or to use a diamond layer as electrical insulation between a substrate and active semi ⁇ conductor layers.
  • the direct junction beween the diamond material and the active silicon layer has, however, proved to cause insufficiently controlled surface states, which will influence in a negative manner the function of the components or circuits formed in the active layer.
  • the present invention has as an object to obtain a simple and advantageous method for manufacturing semiconductor components of the kind initially referred to.
  • a further object is to obtain a manufacturing method, by the use of which a closely controlled thickness of the active layer or layers may be achieved in a simple manner, and which method makes it possible to manufacture very thin active layers.
  • Another object is to obtain a manufacturing method which results in a component, in which the so-called corner effects are avoided at the edges of the active layers.
  • a further object of the invention is to obtain a manufacturing method which gives a component with a high resistance against radiation effects (good radiation hardness) .
  • Figure 1 shows the silicon body, which is to form the active layers, after the generation of a diamond layer and a polycrystal- line silicon layer.
  • Figure 2 shows the assembly generated by bonding the silicon body to the substrate.
  • Figure 3 shows the final assembly before separation into individual components .
  • the manufacture is started with a body 1 of monocrystalline silicon, which has a plane surface (the upper surface in figure 1) .
  • Recesses la, lb etc are formed in a surface of the body.
  • the recesses form a square lattice.
  • the silicon remaining between the recesses forms square mesas 10a, 10b, 10c etc.
  • Each mesa will eventually form an active silicon layer.
  • the lateral dimensions of the mesas are adapted to the component, the components, or to the integrated circuit to be formed in the mesa. The same applies to the height of the mesas, which is equal to the depth of the recesses la, lb etc.
  • a typical mesa may have the form of a square with the length of its sides being betweenlO ⁇ m and 1 mm.
  • the depth of the recesses that is, the height of the mesas eventually to be formed, may typically be 0.5 ⁇ m.
  • the width of the recesses may be 2 - 10 ⁇ m.
  • the recesses are formed by etching, using, for instance, conventional photolitographic technology to define the parts to be etched and masking those parts of the surface not to be etched .
  • a thin layer 2 of silicon dioxide is formed on the surface of the silicon body. This layer prevents direct contact between the active silicon layer and the diamond layer in the finished component, thereby preventing or reducing undesirable surface states.
  • the oxide layer 2 is preferably thin in order to reduce the formation of charge carriers in the layer if the component is subjected to radiation.
  • the thickness of the layer is preferably not greater than 0.02 ⁇ m, and 1 it should not exceed 0.05 ⁇ m.
  • the oxide layer 2 may be generated by thermal oxidation of the silicon in a moist oxygen atmosphere, followed by a heat treatment in an inert atmosphere. This method has proved to result in a low tendency of formation or capture of charge carriers in the oxide layer when the component is subjected to radiation.
  • a polycrystalline diamond layer 3 is formed on the oxide layer 2.
  • the diamond layer may advantageously be formed by a so-called hot wire CVD technique. Alterna ⁇ tively a so-called plasma jet technique may be used for the formation of the diamond layer.
  • the thickness of the diamond layer should exceed the depth of the recesses la, lb etc. A typical thickness could be between 1.0 ⁇ m and 20 ⁇ m.
  • a layer 4 of polycrystalline silicon is grown on the surface of the diamond layer 3 by means of any of several well-known methods .
  • the thickness of the polycrystalline silicon layer” 4 is preferably kept as low as possible.
  • the primary function of this layer is to accommodate unavoidable surface unevenness of the diamond layer, and to make it possible to obtain the very plane and smooth surface neccessary for the subsequent bonding to the substrate.
  • the thickness of the polysilicon layer 4 should not be greater than -necessary to achieve this object. A typical thickness could be 6 ⁇ m.
  • the required thickness of layer 4 may be reduced by grinding and/or polishing the surface of the diamond layer 3 to a high degree of planeness and evenness before application of the polysilicon layer .
  • the surface of the polysilicon layer 4 is ground and/or polished in order to give the surface the high degree of planeness and surface finish necessary for the subsequent bonding to the substrate. After this operation the surface will be the one shown by the dashed line A-A in figure 1.
  • Figure 2 shows the silicon body 1 with the finished surface A-A.
  • a substrate in the form of a silicon body 5 is applied to the body 1 or, rather, to the surface of the layer 4 applied to that body. That surface of the substrate 5 which faces layer 4 is, just as the surface of layer 4, brought to a high degree of planeness and surface smoothness by means of grinding and/or polishing. After applying said surfaces against each other the assembly is subjected to a heat treatment in a known manner, causing so-called thermal bonding between the surfaces.
  • the body 1 is removed, by grinding and/or polishing or other suitable method, to a depth determined by the plane C-C defined by the surfaces of those parts of the diamond layer 3, which are situated in the recesses la, lb etc.
  • These parts of the diamond layer will, due to the great hardness of the diamond material, function as an automatic stop for the grinding/polishing procedure.
  • the material removal will automatically stop when the above-mentioned parts of the diamond layer are reached.
  • the thickness of the active 'layers is automatically controlled to a high accuracy, and this desired thickness will be accurately obtained by means of a simple grinding/polishing operation.
  • the material removal may be made in such a manner as to introduce only minimum defects in the remaining active silicon layers
  • Figure 3 shows the assembly after the removal of the body 1 down to the plane C-C (this figure shows the assembly turned upside down in relation to its position in figures 1 and 2) .
  • the active layers 12a, 12b have the form of squares, separated by a continuous lattice of diamond ridges . As each active layer is laterally completely surrounded by the diamond material, the above-mentioned corner effects are completely eliminated.
  • Each active layer may comprise anything from one single component, such as a single transistor, up to one or more complicated integrated circuits.
  • the assembly shown in figure 3 is divided into separate components, typically with one active layer per component.
  • Division lines Bl-Bl and B2-B2 are shown in figure 3.
  • the division is preferably done in a conventional manner by scribing the component surface and breaking it along the scribed lines . It may be advantageous to remove those parts of the diamond ridges, which are situated along the intended scribing lines, before the scribing and breaking operation.
  • a component according to the invention may comprise additio ⁇ nal layers than those shown in the figures.
  • a thin layer of a suitable material may be applied to the diamond layer 3 before application of the polysilicon layer 4 in order to improve the adhesion between these layers.
  • the polycrystalline silicon layer 4 may alternatively be a layer of amorphous silicon.
  • the etched grooves la, lb etc (figure 1) form a continuous square lattice, and the active layers of the final product will therefore have the form of squares.
  • the active layers may be geiven rectangular form
  • a layer of a suitable glass with a low melting point may replace the polysilicon layer 4.
  • a suitable glass may be a phosphorus- silicon oxide glass with 4% phosphorus having a softening point at approximately 1050 degrees centigrade.
  • the phospho ⁇ rus glass layer is planarized by heating the body 1 to the softening point of the glass. Thereafter the substrate 5 can be bonded to the body 1. The bond is further strengthened by another heat treatment close to the softening point.
  • the thermal conductivity of glass is lower than that of silicon, the glass layer should be as thin as possible in order not to impede the heat transfer from the active layers to the substrate.
  • the etched grooves la, lb etc form a continuous square lattice
  • the final product as shown in figure 3 has a plurality of separate active layers 11a, lib, lie etc separated by the diamond ridges 12a, 12b etc, which form a continuous lattice.
  • the recesses etched in the surface of the silicon body 1 may be separate from each other, for instance constitute a plurality of square recesses .
  • the active silicon layer will then be a continuous layer with a plurality of separate diamond mesas reaching the surface.

Abstract

A semiconductor component may be manufactured by forming in a surface of a silicon body (1) a number of recessed surface portions having essentially plane bottom surfaces and a predetermined depth, deposing on said surface, including said recesses, a diamond layer (3) having a thickness exceeding the depth of said recessed surface portions, said diamond layer having first surface parts (12a, 12b) adjoining the bottoms of said recesses, bonding said silicon body to said substrate with said diamond layer facing the substrate, removing parts of said silicon body distant from said substrate down to a plane (C-C) determined by the surfaces of said first parts (12a, 12b) of said diamond layer.

Description

Me hod for the Manufacture of a Semiconductor Component
Technical Field
The present invention relates to a method for the manufac¬ ture of a semiconductor component, said component having a substrate, a diamond layer on said substrate, and at least one active silicon layer on said diamond layer, at least one semiconductor circuit component being formed in said active silicon layer.
Background Art
It is known to manufacture single semiconductor components and integrated circuits in the so-called SOI technology, which results in a great flexibility in the design and use of the components or circuits by their being electrically insulated from the substrate and from each other. In said technology the component or circuit is formed in a layer of semiconducting material, usually silicon, which layer is arranged on an electrically insulating substrate. This substrate usually is a body of semiconductor material, for instance silicon, having an electrically insulating layer, such as silicon dioxide, upon which the active silicon layer is arranged. In order to obtain a sufficient electrical insulation between the substrate and the component or circuit, the silicon dioxide layer has to be relatively thick, typically at least one or a few μm. Silicon dioxide does, however, have poor thermal properties, especially a low thermal conductivity. This fact results in components of this kind having a limited power handling capacity. Further, such components are sensitive to radioactive (ionizing) radiation. Such radiation results in the formation of electron-hole pairs in the oxide layer, the holes remaining in the oxide and causing a charging-up of the oxide layer, and also resulting in surface states at the junction between the active silicon layer and the oxide layer. Both these phenomena influence in a negative manner the function of the component or circuit formed in the active silicon layer.
It is also known that diamond is a material combining good electrical insulation with a high thermal conductivity and a high thermal capacity. It has therefore been proposed to use diamond as a substrate, or to use a diamond layer as electrical insulation between a substrate and active semi¬ conductor layers. The direct junction beween the diamond material and the active silicon layer has, however, proved to cause insufficiently controlled surface states, which will influence in a negative manner the function of the components or circuits formed in the active layer.
Prior art components of this kind have required complicated manufacturing processes. It has been difficult to achieve a closely controlled thickness of the active silicon layer, and therefore it has been difficult or impossible to manu¬ facture components with thin active layers. Some of the processes used have also tended to generate defects in the active layer. In those cases where the active layer (or several separate active layers) has or have been deposited on the diamond layer various so-called corner effects (such as increased electrical fields or crystal defects) have been hard to avoid at the edges of the layer or layers .
Disclosure of the Invention
The present invention has as an object to obtain a simple and advantageous method for manufacturing semiconductor components of the kind initially referred to.
A further object is to obtain a manufacturing method, by the use of which a closely controlled thickness of the active layer or layers may be achieved in a simple manner, and which method makes it possible to manufacture very thin active layers.
Another object is to obtain a manufacturing method which results in a component, in which the so-called corner effects are avoided at the edges of the active layers. A further object of the invention is to obtain a manufacturing method which gives a component with a high resistance against radiation effects (good radiation hardness) .
Brief Description of the Drawings
A preferred embodiment of the invention will be described below referring to the enclosed drawings 1-3, which illus¬ trate various stages of the manufacturing process . Figure 1 shows the silicon body, which is to form the active layers, after the generation of a diamond layer and a polycrystal- line silicon layer. Figure 2 shows the assembly generated by bonding the silicon body to the substrate. Figure 3 shows the final assembly before separation into individual components .
Description of the Preferred Embodiments
According to a preferred embodiment of the invention the manufacture is started with a body 1 of monocrystalline silicon, which has a plane surface (the upper surface in figure 1) . Recesses la, lb etc are formed in a surface of the body. The recesses form a square lattice. The silicon remaining between the recesses forms square mesas 10a, 10b, 10c etc. Each mesa will eventually form an active silicon layer. The lateral dimensions of the mesas are adapted to the component, the components, or to the integrated circuit to be formed in the mesa. The same applies to the height of the mesas, which is equal to the depth of the recesses la, lb etc. A typical mesa may have the form of a square with the length of its sides being betweenlO μm and 1 mm. The depth of the recesses, that is, the height of the mesas eventually to be formed, may typically be 0.5 μm. The width of the recesses may be 2 - 10 μm.
The recesses are formed by etching, using, for instance, conventional photolitographic technology to define the parts to be etched and masking those parts of the surface not to be etched .
After the etching procedure a thin layer 2 of silicon dioxide is formed on the surface of the silicon body. This layer prevents direct contact between the active silicon layer and the diamond layer in the finished component, thereby preventing or reducing undesirable surface states. The oxide layer 2 is preferably thin in order to reduce the formation of charge carriers in the layer if the component is subjected to radiation. The thickness of the layer is preferably not greater than 0.02 μm, and1 it should not exceed 0.05 μm.
The oxide layer 2 may be generated by thermal oxidation of the silicon in a moist oxygen atmosphere, followed by a heat treatment in an inert atmosphere. This method has proved to result in a low tendency of formation or capture of charge carriers in the oxide layer when the component is subjected to radiation.
As the next step a polycrystalline diamond layer 3 is formed on the oxide layer 2. The diamond layer may advantageously be formed by a so-called hot wire CVD technique. Alterna¬ tively a so-called plasma jet technique may be used for the formation of the diamond layer. The thickness of the diamond layer should exceed the depth of the recesses la, lb etc. A typical thickness could be between 1.0 μm and 20 μm.
Thereafter a layer 4 of polycrystalline silicon is grown on the surface of the diamond layer 3 by means of any of several well-known methods . As the formation of such a layer is typically a slow and therefore expensive process, the thickness of the polycrystalline silicon layer" 4 is preferably kept as low as possible. The primary function of this layer is to accommodate unavoidable surface unevenness of the diamond layer, and to make it possible to obtain the very plane and smooth surface neccessary for the subsequent bonding to the substrate. The thickness of the polysilicon layer 4 should not be greater than -necessary to achieve this object. A typical thickness could be 6μm. The required thickness of layer 4 may be reduced by grinding and/or polishing the surface of the diamond layer 3 to a high degree of planeness and evenness before application of the polysilicon layer .
After these process stages the state of the silicon body 1 with the layers applied thereon is the one shown in figure 1.
As the next step the surface of the polysilicon layer 4 is ground and/or polished in order to give the surface the high degree of planeness and surface finish necessary for the subsequent bonding to the substrate. After this operation the surface will be the one shown by the dashed line A-A in figure 1.
Figure 2 shows the silicon body 1 with the finished surface A-A. A substrate in the form of a silicon body 5 is applied to the body 1 or, rather, to the surface of the layer 4 applied to that body. That surface of the substrate 5 which faces layer 4 is, just as the surface of layer 4, brought to a high degree of planeness and surface smoothness by means of grinding and/or polishing. After applying said surfaces against each other the assembly is subjected to a heat treatment in a known manner, causing so-called thermal bonding between the surfaces.
As the next step the body 1 is removed, by grinding and/or polishing or other suitable method, to a depth determined by the plane C-C defined by the surfaces of those parts of the diamond layer 3, which are situated in the recesses la, lb etc. These parts of the diamond layer will, due to the great hardness of the diamond material, function as an automatic stop for the grinding/polishing procedure. The material removal will automatically stop when the above-mentioned parts of the diamond layer are reached. In this manner the thickness of the active 'layers is automatically controlled to a high accuracy, and this desired thickness will be accurately obtained by means of a simple grinding/polishing operation. Also, the material removal may be made in such a manner as to introduce only minimum defects in the remaining active silicon layers
Figure 3 shows the assembly after the removal of the body 1 down to the plane C-C (this figure shows the assembly turned upside down in relation to its position in figures 1 and 2) . The active layers 12a, 12b have the form of squares, separated by a continuous lattice of diamond ridges . As each active layer is laterally completely surrounded by the diamond material, the above-mentioned corner effects are completely eliminated.
After this, the desired semiconductor circuits and/or components are formed in the active layers by conventional steps. Each active layer may comprise anything from one single component, such as a single transistor, up to one or more complicated integrated circuits.
As a final step the assembly shown in figure 3 is divided into separate components, typically with one active layer per component. Division lines Bl-Bl and B2-B2 are shown in figure 3. The division is preferably done in a conventional manner by scribing the component surface and breaking it along the scribed lines . It may be advantageous to remove those parts of the diamond ridges, which are situated along the intended scribing lines, before the scribing and breaking operation.
It should be pointed out that the figures are intended to illustrate the principle of the invention, and the dimensions etc shown in the figures are not necessarily
< shown to scale.
A component according to the invention may comprise additio¬ nal layers than those shown in the figures. For instance, a thin layer of a suitable material may be applied to the diamond layer 3 before application of the polysilicon layer 4 in order to improve the adhesion between these layers.
The polycrystalline silicon layer 4 may alternatively be a layer of amorphous silicon.
In the preferred embodiment described above the etched grooves la, lb etc (figure 1) form a continuous square lattice, and the active layers of the final product will therefore have the form of squares. Alternatively, by selecting another shape of the lattice formed by the grooves, the active layers may be geiven rectangular form
In an alternative method according to the invention a layer of a suitable glass with a low melting point may replace the polysilicon layer 4. Such a glass may be a phosphorus- silicon oxide glass with 4% phosphorus having a softening point at approximately 1050 degrees centigrade.The phospho¬ rus glass layer is planarized by heating the body 1 to the softening point of the glass. Thereafter the substrate 5 can be bonded to the body 1. The bond is further strengthened by another heat treatment close to the softening point. As the thermal conductivity of glass is lower than that of silicon, the glass layer should be as thin as possible in order not to impede the heat transfer from the active layers to the substrate.
In the preferred embodiment described above the etched grooves la, lb etc (figure 1) form a continuous square lattice, and the final product as shown in figure 3 has a plurality of separate active layers 11a, lib, lie etc separated by the diamond ridges 12a, 12b etc, which form a continuous lattice. Alternatively the recesses etched in the surface of the silicon body 1 may be separate from each other, for instance constitute a plurality of square recesses . In the final product as shown in figure 3 the active silicon layer will then be a continuous layer with a plurality of separate diamond mesas reaching the surface.

Claims

Claims
1. A method for the manufacture of a semiconductor component, said component having a substrate (5) , a diamond layer (3) on said substrate, and at least one active silicon layer (11a, lib) on said diamond layer, at least one semi¬ conductor circuit component being formed in said active silicon layer, said method comprising the steps of
forming in a surface of a silicon body (1) a number of recessed surface portions (la, lb) having essentially plane bottom surfaces and a predetermined depth,
depositing on said surface, including said recesses, a diamond layer (3) having a thickness exceeding the depth of said recessed surface portions, said diamond layer having first surface parts (12a, 12b) adjoining the bottoms of said recesses,
bonding said silicon body to said substrate with said diamond layer facing the substrate,
removing parts of said silicon body distant from said substrate down to a plane (C-C) determined by the surfaces of said first parts (12a, 12b) of said diamond layer.
2. A method according to claim 1, which includes the step of forming a layer of silicon dioxide (2) on said surface of said silicon body (1) after forming said recesses and before depositing said diamond layer.
3. A method according to claim 2, said silicon dioxide layer (2) having a thickness not exceeding 0.05 μm.
4. A method according to claim 1, including the step of depositing a layer (4) of polycrystalline silicon on the surface af said diamond layer (3) before the bonding of said silicon body (1) to said substrate (5) .
5. A method according to claim 4, including the step of forming a plane surface (A-A) with a high surface finish on said polycrystalline silicon layer (4) .
6. A method according to claim 5, including the step of polishing the surface of said polycrystalline silicon layer
(4) .
7. A method according to claim 4, said polycrystalline silicon layer (4) having a thickness not exceeding 10 μm.
8 A method according to claim 1, including the steps of
forming on the surface of said diamond layer (3) a layer of glass,
planarizing said glass layer by heating to the softening point of the glass, and thereafter
bonding said body to said substrate.
9. A method according to claim 1, said diamond layer (3) having a thickness of at least 1 μm.
10. A semiconductor component having a substrate (5), a diamond layer (3) bonded to said substrate, and an active silicon layer (lib) adjacent to a surface (C-C) opposed to said substrate and separated from the substrate by the diamond layer, wherein parts (12a, 12b) of said diamond layer (3) extend to said surface.
11. A semiconductor component according to claim 10, in which said active layer (lib) is completely surrounded by parts (12a, 12b) of said diamond layer (3) extending to said surface (C-C) .
12. A semiconductor component according to claim 10, comprising a layer of silicon dioxide (2) between said diamond layer (3) and said active layer (lib) .
13. A semiconductor component according to claim 12, said silicon dioxide layer (2) having a thickness not exceeding 0.05 μm.
14. A semiconductor component according to claim 10, said diamond layer (3) having a thickness of at least 1 μm.
PCT/SE1992/000390 1991-07-08 1992-06-09 Method for the manufacture of a semiconductor component WO1993001617A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US72581491A 1991-07-08 1991-07-08
US725,814 1991-07-08

Publications (1)

Publication Number Publication Date
WO1993001617A1 true WO1993001617A1 (en) 1993-01-21

Family

ID=24916071

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/SE1992/000390 WO1993001617A1 (en) 1991-07-08 1992-06-09 Method for the manufacture of a semiconductor component

Country Status (1)

Country Link
WO (1) WO1993001617A1 (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994020985A1 (en) * 1993-03-11 1994-09-15 Harris Corporation Bonded wafer process incorporating diamond insulator
DE4426420C1 (en) * 1994-07-26 1996-02-01 Daimler Benz Ag Semiconductor substrate with buried dielectric diamond layer
EP0707338A2 (en) * 1994-10-13 1996-04-17 STMicroelectronics S.r.l. Wafer of semiconductor material for fabricating integrated semiconductor devices, and process for its fabrication
EP0814509A2 (en) * 1993-07-29 1997-12-29 Motorola, Inc. Method for making a substrate structure with improved heat dissipation
KR20000025029A (en) * 1998-10-07 2000-05-06 박한오 Expansion method of arrayed amplification of restriction enzyme fragments
US6171931B1 (en) 1994-12-15 2001-01-09 Sgs-Thomson Microelectronics S.R.L. Wafer of semiconductor material for fabricating integrated devices, and process for its fabrication
DE19542943C2 (en) * 1995-11-17 2001-03-08 Daimler Chrysler Ag Method for producing a microelectronic component with a multilayer composite structure
US6982210B2 (en) 2003-07-10 2006-01-03 S.O.I.Tec Silicon On Insulator Technologies S.A. Method for manufacturing a multilayer semiconductor structure that includes an irregular layer
US7011134B2 (en) 2000-10-13 2006-03-14 Chien-Min Sung Casting method for producing surface acoustic wave devices
US7095157B2 (en) 2000-10-13 2006-08-22 Chien-Min Sung Cast diamond tools and formation thereof by chemical vapor deposition
US7132309B2 (en) 2003-04-22 2006-11-07 Chien-Min Sung Semiconductor-on-diamond devices and methods of forming
US7846767B1 (en) 2007-09-06 2010-12-07 Chien-Min Sung Semiconductor-on-diamond devices and associated methods

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0317124A2 (en) * 1987-11-16 1989-05-24 Crystallume Silicon on insulator semiconductor components containing thin synthetic diamond films
WO1991011822A1 (en) * 1990-01-24 1991-08-08 Asea Brown Boveri Ab Semiconductor device and method for its manufacture

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0317124A2 (en) * 1987-11-16 1989-05-24 Crystallume Silicon on insulator semiconductor components containing thin synthetic diamond films
WO1991011822A1 (en) * 1990-01-24 1991-08-08 Asea Brown Boveri Ab Semiconductor device and method for its manufacture

Non-Patent Citations (7)

* Cited by examiner, † Cited by third party
Title
APPL. PHYS. LETT., 56, No. 23, June 1990, M.I. LANDSTRASS et al.: "Total Dose Radiation Hardness of Diamond-Based Silicon-on-Insulator Structures", see page 2316 - page 2318. *
APPL. PHYS. LETT., Vol. 55, No. 10, September 1989, M.I. LANDSTRASS et al.: "Resistivity of Chemical Vapor Deposited Diamond Films", see page 975 - page 977. *
APPL. PHYS. LETT., Vol. 55, No. 14, October 1989, M.I. LANDSTRASS et al.: "Hydrogen Passivation of Electrically Active Defects in Diamond", see page 1391 - page 1393. *
JAPANESE JOURNAL OF APPLIED PHYSICS, Vol. 21, No. 4, April 1982, SEIICHIRO MATSUMOTO et al.: "Vapor Deposition of Diamond Particles from Methane", see page L183 - page L185. *
JAPANESE JOURNAL OF APPLIED PHYSICS, Vol. 25, No. 10, October 1986, AKIRA ONO et al.: "Thermal Conductivity of Diamond Films Synthesized by Microwave Plasma CVD", see page L808 - L810. *
PATENT ABSTRACTS OF JAPAN, Vol. 10, No. 340, E455; & JP,A,61 144 036, 01-07-1986, NEC CORP. *
PATENT ABSTRACTS OF JAPAN, Vol. 13, No. 171, C588; & JP,A,64 003 097, 06-01-1989, MATSUSHITA ELECTRIC WORKS LTD. *

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994020985A1 (en) * 1993-03-11 1994-09-15 Harris Corporation Bonded wafer process incorporating diamond insulator
EP0814509A2 (en) * 1993-07-29 1997-12-29 Motorola, Inc. Method for making a substrate structure with improved heat dissipation
EP0814509A3 (en) * 1993-07-29 1998-02-04 Motorola, Inc. Method for making a substrate structure with improved heat dissipation
DE4426420C1 (en) * 1994-07-26 1996-02-01 Daimler Benz Ag Semiconductor substrate with buried dielectric diamond layer
EP0707338A2 (en) * 1994-10-13 1996-04-17 STMicroelectronics S.r.l. Wafer of semiconductor material for fabricating integrated semiconductor devices, and process for its fabrication
EP0707338A3 (en) * 1994-10-13 1996-05-15 Sgs Thomson Microelectronics
US5855693A (en) * 1994-10-13 1999-01-05 Sgs-Thomson Microelectronics S.R.L. Wafer of semiconductor material for fabricating integrated devices, and process for its fabrication
US6171931B1 (en) 1994-12-15 2001-01-09 Sgs-Thomson Microelectronics S.R.L. Wafer of semiconductor material for fabricating integrated devices, and process for its fabrication
DE19542943C2 (en) * 1995-11-17 2001-03-08 Daimler Chrysler Ag Method for producing a microelectronic component with a multilayer composite structure
KR20000025029A (en) * 1998-10-07 2000-05-06 박한오 Expansion method of arrayed amplification of restriction enzyme fragments
US7011134B2 (en) 2000-10-13 2006-03-14 Chien-Min Sung Casting method for producing surface acoustic wave devices
US7095157B2 (en) 2000-10-13 2006-08-22 Chien-Min Sung Cast diamond tools and formation thereof by chemical vapor deposition
US7132309B2 (en) 2003-04-22 2006-11-07 Chien-Min Sung Semiconductor-on-diamond devices and methods of forming
US7812395B2 (en) 2003-04-22 2010-10-12 Chien-Min Sung Semiconductor-on-diamond devices and methods of forming
US6982210B2 (en) 2003-07-10 2006-01-03 S.O.I.Tec Silicon On Insulator Technologies S.A. Method for manufacturing a multilayer semiconductor structure that includes an irregular layer
US7846767B1 (en) 2007-09-06 2010-12-07 Chien-Min Sung Semiconductor-on-diamond devices and associated methods

Similar Documents

Publication Publication Date Title
KR100268121B1 (en) Structure of semiconductor substrate and manufacture of the same
US6563172B2 (en) Semiconductor substrate processing method
US5086011A (en) Process for producing thin single crystal silicon islands on insulator
JPS61296709A (en) Manufacture of semiconductor
JPS6113642A (en) Method of forming separate region of semiconductor substrate
WO1993001617A1 (en) Method for the manufacture of a semiconductor component
JPH07263541A (en) Dielectric separation substrate and manufacture thereof
GB2206445A (en) Method of manufacturing dielectrically isolated integrated circuits and circuit elements
US6194253B1 (en) Method for fabrication of silicon on insulator substrates
USH1137H (en) Wafer bonding technique for dielectric isolation processing
JP4465760B2 (en) Method for manufacturing vertical semiconductor device
JPH0437020A (en) Preparation of thermocompression bonding wafer
JPH04181719A (en) Forming method for crystalline article
JPH0658934B2 (en) Method for manufacturing semiconductor device
JPH08236615A (en) Dielectrically isolated substrate and fabrication thereof
JPH02205339A (en) Manufacture of semiconductor device
JP2002057309A (en) Method of forming soi substrate
JPH0370155A (en) Manufacture of dielectric separating type semiconductor device
KR102533585B1 (en) Producing method of silicon on insulator substrate
KR102546554B1 (en) Producing method of multi silicon on insulator substrate and multi silicon on insulator substrate
JP3614927B2 (en) Method for manufacturing bonded semiconductor substrate
JPS6249643A (en) Semiconductor device and its manufacture
JPS6252923A (en) Method for insulating isolation of semiconductor layer by dielectric
JPS6362252A (en) Manufacture of dielectric isolation substrate
JPH0212854A (en) Manufacture of dielectric isolated semiconductor integrated circuit substrate

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB GR IT LU MC NL SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
122 Ep: pct application non-entry in european phase