JP2904095B2 - Method of manufacturing single electronic device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a single electronic device, and more particularly, to a method of manufacturing a single electronic device that operates by moving one electron.

[0002]

2. Description of the Related Art Conventionally, a single electronic device capable of operating at a high temperature and having a controlled microstructure is known (Y. Takahash
IE et al., IEDM Technical Digest, p.938, 1994). FIG.
5 shows a configuration diagram of an example of a conventional single electronic device described in this document, FIG. 5A is a top view, and FIG.
FIG. 3A is a sectional view taken along line AA ′ of FIG.

In order to manufacture a conventional single electronic device having this structure, first, an insulating film 304 is formed on a semiconductor substrate 305, and a single-crystal silicon film is further formed thereon. Source 301 using the SOI substrate of
After forming the source and drain 303 by a known method, thermal oxidation is performed after processing the source 301 and the drain 303 and a thin line between the source 301 and the drain 303 with a length of 50 nm and a width of 30 nm using plasma etching. This thermal oxidation is to narrow the width of the fine line end with respect to the center of the fine line,
This is performed in order to prevent a short circuit between a gate 302 to be formed later and the fine wire.

Due to this thermal oxidation, the central portion of the thin line between the source 301 and the drain 303 becomes 306 in FIGS. 5A and 5B.
As shown by, due to the stress accompanying volume expansion during thermal oxidation, the oxidation rate is low, and the thin line has a shape in which the center expands in the width direction and the thickness direction, respectively. Thereafter, the gate 302 is formed via the insulating film 304 by a known method.

In this structure, when a voltage is applied to the gate electrode 302 to induce an inversion layer in the thin wire, the threshold voltage becomes large because the thin film has a thicker oxide film than the central portion of the thin wire. Further, the thin line end is thinner at the thin line end than the central portion of the thin line, and pinch-off is easy to occur. For this reason, the end of the thin line functions as a potential barrier, and a quantum dot is formed at the center of the thin line. The size of this quantum dot is several tens of nm.
Since the energy is small, the electrostatic energy is relatively large, and Coulomb oscillation is observed even at room temperature.

[0006]

However, in the above-described conventional method for manufacturing a single-electron device, the source 301 and the drain 302 have large regions and have parasitic resistance and capacitance, so that high-speed operation of the device is restricted. Therefore, there is also a problem in high integration of devices. Further, in the case of configuring a circuit using a single electronic element, a clear connection method of a plurality of single electronic elements has not been shown conventionally.

[0007] The present invention has been made in view of the above points,
It is an object of the present invention to provide a method for manufacturing a single electronic device capable of operating at a high temperature and miniaturizing.

Another object of the present invention is to provide a method of manufacturing a single electronic device which can be applied to a high-speed and high-performance circuit.

[0009]

In order to achieve the above object, the present invention provides a method for forming a semiconductor layer on an insulating substrate by using a source and a gate.
Process to form a rain, and sauce and dough
The shape between the rains is a half connected in series by multiple thin wires.
The conductor layer is processed and thin wires that are adjacent to each other
A first step of forming the elements so that they are connected to each other at a predetermined angle ; and thinning the thin wires by thermal oxidation of the element that has undergone the first step. A second step of making the thickness smaller than a width and a thickness of each connecting portion of the plurality of fine wires; and a third step of forming a gate on an oxide film of the element after the second step. Features.

Here, in the third step of the present invention, it is desirable to form a part of each of the source and the drain and the whole of the plurality of fine wires so as to overlap each other. In the first step, a plurality of fine lines are each connected to an adjacent fine line by 90%.
It is desirable to connect at an angle of degrees.

In the present invention, the width and thickness of each non-connection portion of the plurality of thin wires are made larger than the width and thickness of each connection portion of the plurality of thin wires by utilizing the stress at the time of thermal oxidation in the second step. When a voltage is applied to the gate to induce an inversion layer in the fine wire, the thin wire connection and the source region and the thin wire connection and the drain region can be easily pinched off. Since the thickness of the insulator formed by thermal oxidation is larger than that of the portion and the threshold voltage is high, a quantum dot structure in which the thin wire connection portion is sandwiched between two potential barrier regions can be obtained.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIGS. 1A and 1B are configuration diagrams of a single electronic device manufactured by a first embodiment of the manufacturing method of the present invention. FIG. 1A is a top view, and FIG. AA ′ in FIG.
FIG. In the single electronic device manufactured in this embodiment, as shown in FIG. 1B, an insulating film 102 is formed on a semiconductor substrate 101, and a silicon layer on the insulating film 102 is further processed. A source 103 and a drain 104 are formed as shown in FIGS.

Further, between the source 103 and the drain 104, two thin wires 106 made of the same silicon layer are used as shown in FIG.
The connection is made as shown in FIG. These two fine wires 10
6 are connected at an angle of 90 degrees, and the thin line width and thickness of the thin line connecting portion 107 are larger than the thin line width and thickness of the non-connecting portion.

Source 103, drain 104 and fine wire 1
Reference numeral 06 is covered with an insulating film 102 as shown in FIG. 1B, and a gate 105 exists on the insulating film 102.
The gate 105 is provided so as to overlap a part of the source 103 and the drain 104 and the entire thin line 106 as shown in FIG. In addition, in the insulating film 102 on the thin wire 106, the thickness of the non-connection portion is larger than the thickness of the thin wire connection portion 107.

Next, a method of manufacturing the single electronic device will be described with reference to FIG. First, the substrate 1 shown in FIG.
First, an SOI substrate in which an insulating film 102 is formed on the substrate 01 and a silicon layer on the insulating film 102 is formed is prepared. After doping the silicon layer with impurities of a predetermined conductivity type, a resist is applied to the SOI substrate, the silicon layer on the insulating film 102 is processed by electron beam lithography and reactive ion etching (RIE), and a source 103 and a drain are formed. 104 and the source 103 and the drain 1
Two thin lines 106 between the lines 04 are formed. As shown in FIG. 2A, these two fine wires 106 are connected at a length L at an angle of 90 degrees, and their width W and thickness are uniform.

Next, as shown in FIG. 2B, the thin wire 106 is thinned by performing thermal oxidation. That is, since the thin wire connecting portion 107 has a large stress at the time of oxidation, the oxidation speed is lower than that of the thin wire non-connecting portion, and the consumption of silicon due to oxidation is small. Therefore, the width and thickness of the thin wire non-connection portion after oxidation are smaller than those of the thin wire connection portion 107. In addition, due to the thermal oxidation at this time, an oxide film is formed on the source 103, the drain 104, and the thin wire 106, and the oxide film thickness on the thin wire non-connection portion is larger than the oxide film thickness on the thin wire connection portion 107.

Next, the resist is patterned by using an electron beam lithography technique, and the source 103 and the drain 104 are formed by coating the resist on the fine wires 106 and then implanting impurities. Thereafter, annealing is performed to activate the implanted impurities. Finally, aluminum sputtering, electron beam lithography and patterning by RIE are performed to form a gate 105 on an oxide film (the insulating film 1 in FIG. 1).
02) formed on top.

According to the single electron device of this embodiment manufactured as described above, when a voltage is applied to the gate 105 and an inversion layer is induced on the surface of the thin wire 106, the thin wire connecting portion 107 and the source 103 Inter-region and fine wire connecting portion 107
The region between the drains 104 is smaller in width and thickness than the thin wire connection portion 107, and easily pinches off. In these regions, the thickness of the insulating film 102 is larger than that of the thin wire connection portion 107 and the threshold voltage is higher. For this reason, the thin wire connecting portion 107 has a quantum dot structure sandwiched between two potential barrier regions. If the potential barrier region is sufficiently short, carriers can tunnel through the potential barrier region, and a single-electron transistor structure is formed.

(Second Embodiment) FIG. 3 is a top view of a single electronic device manufactured according to a second embodiment of the method for manufacturing a single electronic device of the present invention. The silicon layer on the insulating film is processed to form the source 203 and the drain 204. Further, between the source 203 and the drain 204, four thin wires 206a, 206b,
It is connected via 06c and 206d. Each of these thin lines 206a to 206d is 9
They are connected at an angle of 0 degrees, and the thin line width and thickness of the thin line connecting portion 207 are larger than the thin line width and thickness of the non-connecting portion.

Source 203, drain 204 and fine wire 2
06a to 206d are covered with an insulating film, and a gate 205 exists on the insulating film. This gate 205 is shown in FIG.
As shown in FIG. 2, the source 203 and a part of the drain 204 are formed so as to overlap with the thin lines 206a to 206d.

Next, the manufacturing method of this embodiment will be described with reference to FIG. In FIG. 4A, a silicon layer on an insulating film is processed by electron beam lithography and RIE, and a source 203, a drain 204, and a source 203 are formed.
Four thin wires 206a-20 connected between the drains 204 at 90 degrees to adjacent thin wires as shown
6d is formed. The width and thickness of each of the thin lines 206a to 206d are the same.

Next, the element shown in FIG. 4A is subjected to thermal oxidation, so that the thin wire 2 is formed as shown in FIG.
06a to 206d are thinned. Since the thin wire connection portion 207 has a large stress at the time of oxidation, the oxidation speed is lower than that of the thin wire non-connection portion, and the consumption of silicon due to oxidation is small. For this reason, the width and thickness of the thin wire non-connection portion after oxidation are
It is smaller than the thin wire connection portion 207. In addition, during the thermal oxidation, the source 203, the drain 204 and the thin wire 206 are formed.
An oxide film is formed so as to cover a to 206d. The thickness of the oxide film on the thin wire connection portion is larger than the thickness of the oxide film on the thin wire connection portion 207.

After that, aluminum is deposited and patterned by electron beam lithography and RIE to form a gate 205 on the oxide film.

In the device according to the second embodiment manufactured by the above manufacturing method, when a voltage is applied to the gate 205 to induce an inversion layer on the surfaces of the thin wires 206a to 206d, the thin wire connecting portion 207 and the source 203 The inter-region and the region between the thin wire connection portion 207 and the drain 204 have a smaller width and thickness than the thin wire connection portion 207, and are liable to pinch off. Large, high threshold voltage, etc.
The thin wire connection portion 207 has a quantum dot structure sandwiched between two potential barrier regions. If the potential barrier region is sufficiently short, carriers can tunnel through the potential barrier region, and a single-electron transistor structure is formed. In this case, since a plurality of quantum dots are connected in series, co-tunneling (Co-Tunnelin) is performed.
g) is less likely to occur, and a clearer Coulomb blockade phenomenon can be observed than in the first embodiment.

[0025]

Next, an example of the first embodiment shown in FIG. 1 will be described. First, the upper silicon layer
An SOI substrate of about several tens nm is prepared. Here, a commercially available film having a thickness of about 50 nm is used.
The upper silicon layer is doped with boron, which is a p-type impurity, by about 10 ¹⁵ cm ⁻³ . A negative resist is applied to the SOI substrate, exposed by an electron beam lithography apparatus, and then the silicon layer is processed by RIE. Fine line 106 between source 103 and drain 104
Both the length L and the width W can be reduced to about 20 nm.

Next, thermal oxidation is performed in an O ₂ atmosphere to grow an oxide film to a thickness of about 20 nm. As a result, oxide films are grown on the upper and lower surfaces of the silicon layer. Here, if the thermal oxidation temperature is too high, the viscosity of the oxide film becomes small, and the stress applied to the thin wire connecting portion 107 becomes small. Therefore, the thermal oxidation is performed at a temperature of about 800 ° C. here. In the thin wire connecting portion 107, the oxidation rate is low due to the stress due to thermal oxidation, whereas in the thin wire non-connecting portion, the stress is small and the oxidation reaction sufficiently proceeds, and silicon in the fine wire is consumed. And the thickness is reduced. At the same time, the oxide film thickness of the non-connection portion of the thin wire is larger than that of the thin wire connection portion 107.

Next, the resist is patterned by using an electron beam lithography technique, and after covering the fine wire 106 with the resist, the n-type impurity arsenic (As ⁺ ) is applied under the conditions of an energy of 50 keV and a dose of 1E16 / cm ² . To form a source 103 and a drain 104. Thereafter, in a nitrogen (N ₂ ) atmosphere at 900 ° C.
The implanted As is activated by annealing for about 30 minutes. Finally, aluminum is sputtered and patterned to form a gate 105 on the oxide film.

Next, an example of the second embodiment shown in FIG. 3 will be described. First, the upper silicon layer is a few nm
An SOI substrate having a thickness of about several tens nm is prepared. Here, a commercially available film having a thickness of about 50 nm is used. The upper silicon layer is doped with boron, which is a p-type impurity, by about 10 ¹⁵ cm ⁻³ .
A negative resist is applied to the SOI substrate, exposed by an electron beam lithography apparatus, and then the silicon layer is processed by RIE. Fine wire 2 between source 203 and drain 204
The length L and width W of 06 can both be reduced to about 20 nm.

Next, thermal oxidation is performed in an O ₂ atmosphere to grow an oxide film to a thickness of about 20 nm. As a result, oxide films are grown on the upper and lower surfaces of the silicon layer. Here, if the thermal oxidation temperature is too high, the viscosity of the oxide film becomes small, and the stress applied to the thin wire connection portion 207 becomes small. Therefore, the thermal oxidation is performed at a temperature of about 800 ° C. here. In the thin wire connection portion 207, the oxidation rate is low due to the stress due to thermal oxidation, whereas in the thin wire non-connection portion, the stress is small and the oxidation reaction proceeds sufficiently, and silicon in the fine wire is consumed. And the thickness is reduced. At the same time, the oxide film thickness of the non-connection portion of the thin wire is larger than that of the thin wire connection portion 207.

Next, the resist is patterned by using the electron beam lithography technique, and all the thin lines 206a are formed.
After covering the top surface with a resist, arsenic (As ⁺ ) as an n-type impurity is applied with an energy of 50 keV and a dose of 1E1.
It was implanted into the silicon layer with a 6 / cm ² conditions, source 203
And a drain 204 are formed. Thereafter, the implanted As is activated by annealing at 900 ° C. for about 30 minutes in an N ₂ atmosphere. Finally, aluminum is sputtered and patterned to form a gate 205 on the oxide film.

Although the two embodiments and examples using the method for manufacturing a single electronic device of the present invention have been described above, instead of a silicon layer doped with boron as an upper silicon layer of an SOI substrate, phosphorus is used. Alternatively, a silicon layer doped with an n-type impurity such as arsenic or antimony may be used. In this case, the source and drain regions need to be doped with a p-type impurity such as boron. Further, the impurity concentration in the upper silicon layer can be selected in a range of about 10 ¹⁴ cm ⁻³ to 10 ¹⁹ cm ⁻³ regardless of the impurity type.

It is sufficient that a sufficient stress is applied to the thin wire connection portion during oxidation, and the connection angle does not need to be 90 degrees. The oxide film thickness of the silicon layer can be selected from several nm to such an extent that the fine line is not cut. However, since the impurity concentration and the oxide film thickness in the upper silicon layer affect the voltage applied to the gate to induce carriers into fine lines,
It is necessary to set appropriate conditions.

The oxidation temperature of the upper silicon layer is not required to be 800 ° C., as long as the oxidation of the thin wire connection portion is sufficiently suppressed. When the oxidation amount is large and the width or thickness of the fine wire after oxidation is small, it is not necessary to extremely suppress oxidation of the fine wire connection part,
Even when the oxidation is performed at 800 ° C. or more, the formation of the dot structure can be performed. Also, as ion implantation species for source and drain,
In addition to As ⁺ , P ⁺ , Sb ^{+ and the} like are also possible. Further, the source and the drain can be formed by other methods such as solid-phase diffusion and plasma doping other than the ion implantation. Instead of aluminum, the gate may be substituted with another metal such as tungsten or polysilicon doped with impurities.

As is apparent from the two embodiments, parallel connection of the quantity dot structure or mixed connection of series and parallel is easy.

[0035]

As described above, according to the present invention,
Since the quantum dot structure is formed by utilizing the stress at the time of thermal oxidation, a quantum dot structure below the lithography limit can be formed, and a single electronic device capable of high-temperature operation and integration can be manufactured. Further, according to the present invention, a single-electron element having a large degree of freedom in connection between quantum dots and a small parasitic resistance and a small parasitic capacitance can be manufactured. The device can be manufactured.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a single electronic device manufactured by a first embodiment of the method of the present invention, (a) is a top view, and (b) is a cross-sectional structure diagram along AA ′ line. .

FIG. 2 is an explanatory diagram of a first embodiment of the method of the present invention.

FIG. 3 is a top view of a single electronic device manufactured according to a second embodiment of the method of the present invention.

FIG. 4 is an explanatory diagram of a second embodiment of the method of the present invention.

5A and 5B are configuration diagrams of an example of a single electronic device manufactured by a conventional method, in which FIG. 5A is a top view and FIG. 5B is a cross-sectional structure diagram along line AA ′.

[Explanation of symbols]

 Reference Signs List 101 semiconductor substrate 102 insulating film 103, 203 source 104, 204 drain 105, 205 gate 106, 206a to 206d fine wire 107, 207 fine wire connection portion

Claims (3)

(57) [Claims] 1. A source及Bido a semiconductor layer on an insulating substrate
Processed to form rain, the sauce and
Drains are connected in series by multiple thin wires
The semiconductor layer is processed, and the plurality of fine wires are adjacent to each other.
A first step of forming the thin wires to be connected at a predetermined angle to each other, and thinning the thin wires by thermal oxidation of the element that has undergone the first step, so that the thin wires are not stressed by the stress during the thermal oxidation. A second step of making the width and thickness of the connection part smaller than the width and thickness of each connection part of the plurality of fine wires; and a third step of forming a gate on the oxide film of the element having undergone the second step A method for manufacturing a single electronic device, comprising the steps of: 2. The manufacturing of a single electronic device according to claim 1, wherein the third step is to form a part of each of the source and the drain and the whole of the plurality of thin wires so as to overlap each other. Method. 3. The method according to claim 1, wherein the first step is connected in series.
3. The method according to claim 1, wherein adjacent ones of the plurality of thin wires are connected at an angle of 90 degrees.