JPH1012895A - Monolithic electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a monolithic device which operates at a high temperature. SOLUTION: A semiconductor layer 107 having a thickness of several Åto several hundreds of Å, within an SOI substrate including about 10<18> -10<20> cm<-3> impurities, is patterned so as to form a source electrode 101 and a drain electrode 103 by plasma etching or the like. Further, a thin line 104, having a width of several Å to several hundreds of Å and a length of Åto several hundreds of Å, is formed between the source electrode 101 and the drain electrode 103. The thin line 104 has a narrow regions having a width of several Å to several hundreds of Å at positions 104a and 104b in its central portion, and has a region between these two regions, as an island 109. A gate electrode 102 is provided, via an insulating film 108, on the island 109. The island 109 between two narrow potential barriers is formed by applying a voltage to the gate electrode 102.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a single electronic device, and more particularly, to a single electronic device that operates by transferring single electrons.

[0002]

2. Description of the Related Art Conventionally, a single electronic device capable of operating at a high temperature and having a controlled microstructure is known (Y. Takahash
IE et al., IEDM Technical Digest, p.938, 1994). FIG.
5 shows a configuration diagram of an example of a conventional single electronic device described in this document, FIG. 5A is a top view, and FIG.
FIG. 3A is a sectional view taken along line AA ′ of FIG.

In order to manufacture a conventional single electronic device having this structure, first, a buried insulating film 5 is formed on a semiconductor substrate 505.
06, and a 50 nm thick SOI (Silicon On Insulat
or) A source 501 and a drain 503 are formed by a known method using a substrate, and then the source 501 and the drain 5 are formed.
03 and the length 50n between the source 501 and the drain 503
Thermal oxidation is performed after processing the thin wire 504 having a width of 50 nm and a width of 50 nm using plasma etching. This thermal oxidation is source 5
In order to reduce the width of the fine line end with respect to the central portion of the fine line between
This is performed in order to prevent a short circuit with the C.04.

As shown in FIGS. 5A and 5B, due to this thermal oxidation, the central portion of the thin line between the source 501 and the drain 503 has a low oxidation rate due to stress accompanying volume expansion during thermal oxidation. Is an island 509 whose center swells in the width direction and the thickness direction, respectively. After that, the gate 502 is formed via the insulating film 508 by a known method.

In this structure, when a voltage is applied to the gate 502 to induce an inversion layer in the thin wire, the threshold voltage becomes large because the insulating film is thicker at the end of the thin wire than at the center of the thin wire. Further, the thin line end is thinner at the thin line end than the central portion of the thin line, and pinch-off is easy to occur. For this reason, the end of the thin line functions as a potential barrier, and a quantum dot is formed at the center of the thin line. Since the size of this quantum dot is as small as about several tens of nm, the electrostatic energy is relatively large, and Coulomb blockade oscillation is observed even at room temperature.

[0006]

However, the structure of the above-mentioned conventional single-electron element uses a potential barrier formed at the end of the fine wire as a tunnel barrier. However, the impurity concentration in the fine wire is low, and carriers are generated at a low temperature. Because it freezes out, it becomes a wide barrier. In order to improve the operating temperature, a barrier with a small width and a high barrier is required.However, if the barrier height is increased by a method such as increasing the impurity concentration in the fine wire, the barrier width increases at the same time. Is too large, and there is a problem that the high-temperature operation is limited.

[0007] The present invention has been made in view of the above points,
It is an object of the present invention to provide a single electronic device capable of operating at a high temperature.

Another object of the present invention is to provide a single electronic device which can be easily manufactured.

[0009]

In order to achieve the above object, the present invention has a structure in which a buried insulating film and a semiconductor layer are laminated on a substrate, and the semiconductor layer comprises a drain and a source and a fine wire between them. In a single electronic device, an impurity is introduced so as to electrically degenerate the fine wire, and formed so that at least one island sandwiched by a plurality of electric barrier regions exists, and the electric barrier region is formed. The thin line is characterized in that it is depleted based on a voltage applied to an electrically insulated gate.

In the present invention, when a voltage of a certain value or more is applied to the gate, only the electrical barrier region of the thin line is completely depleted. Even if the barrier height is increased by increasing the gate voltage, the impurity concentration of the fine wire is large enough to be electrically degenerated, and the increase in the barrier width in the length direction (longitudinal direction) of the fine wire can be reduced.

Here, the above-mentioned electric barrier region is a region where the width of the thin line is smaller than the width of the other region of the thin line, or the thickness of the thin line is smaller than the thickness of the other region of the thin line. It is a featured area.

Further, in the present invention, the gate is formed near the island by the semiconductor layer, or is formed on the insulating film covering the semiconductor layer and near the island.

Further, the present invention is characterized in that a plurality of islands are formed and connected to each other in series or in parallel.

[0014]

Next, embodiments of the present invention will be described with reference to the drawings.

(First Embodiment) FIGS. 1A and 1B show the configuration of a single electronic device according to a first embodiment of the present invention. FIG. 1A is a top view, and FIG. FIG. 2 is a cross-sectional view taken along line AA ′ of FIG.

In the single electronic device of this embodiment, a buried insulating film 106 is formed on a semiconductor substrate 105,
Further, a semiconductor layer 107 having a thickness of several to several hundreds of millimeters in an SOI substrate having a single crystal silicon film formed thereon and containing impurities of about 10 ¹⁸ to 10 ²⁰ cm ⁻³ is patterned, and is subjected to plasma etching or the like. Is used to form a source 101 and a drain 103, and between the source 101 and the drain 103, a width of {Å to several hundreds} and a length of {Å to several hundreds}.
A thin line 104 of a degree is formed.

In the center of the thin line, two narrow areas 104a and 104b are formed, each having a narrow width of several to several hundreds of squares.
And The gate 102 is provided over the island 109 with an insulating film 108 interposed therebetween.

Next, the operation of this embodiment will be described. Since the impurity is introduced into the semiconductor layer 107 at about 10 ¹⁹ cm ^{−3, the} semiconductor layer 107 is electrically degenerated and exhibits metallic conduction even at a low temperature. However, when a voltage is applied to the gate 102, the surface of the thin wire 104 can be depleted by several nm. For this reason, when a voltage of a certain value or more is applied to the gate 102, the above-described 2 having a narrow thin line width
Only the regions 104a and 104b are completely depleted, and a potential barrier is formed in these regions.

As the voltage applied to the gate 102 is further increased, the potential barrier height is increased. However, since the impurity concentration in the fine wire 104 is high, the height of the fine wire 104 in the length direction (longitudinal direction) is increased. The increase in barrier width is small. As described above, in the first embodiment, by applying a voltage to the gate 102, the island 109 sandwiched between two narrow potential barriers can be formed, and a single electronic element structure can be realized. .

(Second Embodiment) Next, a second embodiment of the present invention will be described.
An embodiment will be described. 2A and 2B show the configuration of a second embodiment of a single electronic device according to the present invention, wherein FIG. 2A is a top view, and FIG. 2B is a line AA ′ in FIG. It is sectional drawing.

In the single electronic device of this embodiment, a buried insulating film 206 is formed on a semiconductor substrate 205,
Further, a semiconductor layer 207 having a thickness of several to several hundreds of millimeters in an SOI substrate on which a single crystal silicon film is formed and containing impurities of about 10 ¹⁸ to 10 ²⁰ cm ⁻³ is patterned, and plasma etching is performed. Is used to form a source 201 and a drain 203, and a width {Å to several hundreds} and a length {Å to several hundreds} between the source 201 and the drain 203.
A thin line 204 of a degree is formed.

At the center of the thin line, two small areas 204a and 204b are formed, each having a small thickness of several tens to several hundreds of millimeters.
9 is assumed. The gate 202 is provided over the island 209 via the insulating film 208.

Next, the operation of this embodiment will be described. Since the impurity is introduced into the semiconductor layer 207 at about 10 ¹⁹ cm ^{−3, the} semiconductor layer 207 is electrically degenerated and shows metallic conduction even at a low temperature. However, when a voltage is applied to the gate 202, the surface of the thin wire 204 can be depleted by about several nm. For this reason, when a voltage of a certain value or more is applied to the gate 202, only the regions 204a and 204b having a small thin line thickness are completely depleted, and a potential barrier is formed in these regions.

As the voltage applied to the gate 202 is further increased, the potential barrier height is increased. However, since the impurity concentration in the thin wire 204 is high, the height of the thin wire 204 in the longitudinal direction (longitudinal direction) is increased. The increase in barrier width is small. As described above, in the second embodiment, by applying a voltage to the gate 202, the island 209 sandwiched between the two narrow potential barriers can be formed, and a single electronic element structure can be realized. .

(Third Embodiment) Next, a third embodiment of the present invention will be described.
An embodiment will be described. 3A and 3B show a configuration of a third embodiment of a single electronic device according to the present invention. FIG. 3A is a top view, and FIG. 3B is an AA ′ line of FIG. 3A. It is sectional drawing.

In the single electronic device of this embodiment, a buried insulating film 306 is formed on a semiconductor substrate 305,
Further, a semiconductor layer 307 having a thickness of several to several hundreds of millimeters in an SOI substrate having a single crystal silicon film formed thereon and containing impurities of about 10 ¹⁸ to 10 ²⁰ cm ⁻³ is patterned, and plasma etching is performed. Is used to form a source 301 and a drain 303, and between the source 301 and the drain 303, the width is several hundreds of mm and the length is several hundreds of mm.
A thin line 304 of a degree is formed.

At the center of the thin line, there are provided two narrow areas 304a and 304b each having a narrow width of about several to several hundreds of millimeters.
9 is assumed. The semiconductor layer 3 is formed at the same time as the formation of the thin wire 304.
By patterning 07, as shown in FIG. 3A, a gate 302 is formed at a distance of 100 nm from the island 309. The island 309 is covered with an insulating film 308 for passivation.

Next, the operation of this embodiment will be described. Since the impurity is introduced into the semiconductor layer 307 at about 10 ¹⁹ cm ^{−3, the} semiconductor layer 307 is electrically degenerated and shows metallic conduction even at a low temperature. However, when a voltage is applied to the gate 302, the surface of the thin wire 304 can be depleted by several nm. For this reason, when a voltage of a certain value or more is applied to the gate 302, only the regions 304a and 304b having a small thin line width are completely depleted, and a potential barrier is formed in these regions.

As the voltage applied to the gate 302 is further increased, the potential barrier height is increased. However, since the impurity concentration in the thin wire 304 is high, the height of the thin wire 304 in the longitudinal direction (longitudinal direction) is increased. The increase in barrier width is small. As described above, in the third embodiment, by applying a voltage to the gate 302, an island 309 sandwiched between two narrow potential barriers can be formed, and a single electronic element structure can be realized. .

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described.
An embodiment will be described. 4A and 4B show a configuration of a fourth embodiment of a single electronic device according to the present invention. FIG. 4A is a top view, and FIG. 4B is a line AA ′ in FIG. It is sectional drawing.

In the single electronic device of this embodiment, a buried insulating film 406 is formed on a semiconductor substrate 405,
Further, a semiconductor layer 307 having a thickness of several to several hundreds of millimeters in an SOI substrate having a single crystal silicon film formed thereon and containing impurities of about 10 ¹⁸ to 10 ²⁰ cm ⁻³ is patterned, and plasma etching is performed. Is used to form a source 401 and a drain 403, and between the source 401 and the drain 403, a width {Å to several hundreds} and a length {Å to several hundreds}.
A thin line 404 of the order is formed.

At the center of the thin line, 404a, 404b,
At three places indicated by reference numeral 404c, narrow areas of about several to several hundreds of squares are provided, and two areas sandwiched between these three areas are islands 409. A gate 402 is formed over the island 409 with an insulating film 408 therebetween.

Next, the operation of this embodiment will be described. Since the impurity is introduced into the semiconductor layer 407 at about 10 ¹⁹ cm ^{−3, the} semiconductor layer 407 is electrically degenerated and shows metallic conduction even at a low temperature. However, when a voltage is applied to the gate 402, the surface of the thin wire 404 can be depleted by about several nm. For this reason, when a voltage of a certain value or more is applied to the gate 402, only the regions 404a, 404b, and 404c having a small thin line width are completely depleted, and a potential barrier is formed in these regions.

When the voltage applied to the gate 402 is further increased, the above-mentioned potential barrier height is increased. However, since the impurity concentration in the thin wire 404 is high, the height of the thin wire 404 in the longitudinal direction (longitudinal direction) is increased. The increase in barrier width is small.

As described above, in the fourth embodiment, by applying a voltage to the gate 402, two islands 409 sandwiched between narrow potential barriers can be formed, and the islands 409 are connected in series. A single electronic device structure can be realized. In this embodiment, since two islands 409 are connected in series, co-tunneling hardly occurs and clear Coulomb blockade oscillation can be observed.

[0036]

Next, examples of the above embodiments will be described. An example of the embodiment of FIG. 1 will be described. As a method for producing a single electronic device of the structure of FIG. 1, first, a silicon substrate containing about 5 × 10 ¹⁹ cm ^-3 phosphorus, oxygen is implanted high concentration ions to the silicon substrate, a silicon substrate SIMOX forming oxide film inside
(Separation by Implanted Oxygen) method to form an SOI substrate. The thickness of the buried insulating film 106 is 300 n
m, the thickness of the semiconductor layer 107 is about 50 nm. Further, by performing thermal oxidation, the thickness of the semiconductor layer 107 is reduced, and finally a film thickness of about 10 nm can be realized.

Subsequently, after removing the silicon oxide film on the surface with HF, electron beam exposure and reactive ion etching (RI
E) The semiconductor layer 107 is processed by the technique to
1 and the drain 403 are formed, and a space between them is processed into a thin line having a width of 10 nm and a length of 100 nm. Narrow areas are provided at two places 104a and 104b adjacent to the center of the thin line, and the area sandwiched between these areas is referred to as an island 10.
9 is assumed. The narrow region of the fine line width can be formed by providing a narrow region in the fine line 104 at the time of electron beam exposure. A narrow region having a width of about 5 nm and a length of about 10 nm can be realized. The length of the island 109 is about 10 nm.

Next, chemical vapor deposition (CV) is performed on the device.
A silicon oxide film having a thickness of about 100 nm is grown by the method D), and an insulating film 108 is formed. Subsequently, the source 10 is formed by photolithography and RIE etching.
A contact hole is opened in the insulating film 108 on each region of the first and drain 103, and then aluminum
about m. The aluminum is processed by the optical lithography technology and the RIE etching technology.
1. The formation of an electrode on the drain 103 and the formation of the gate 102 are simultaneously performed on the insulating film 108.

In the single electron device formed as described above, when a negative voltage of −3 V or more was applied to the gate 102, clear Coulomb blockade oscillation was observed at a temperature of 4K. This vibration was also observed at 77K, confirming that high-temperature operation was possible.

Next, an example of the second embodiment shown in FIG. 2 will be described. As a method of manufacturing a single electronic device having the structure shown in FIG. 2, first, an SOI substrate is formed by a SIMOX method using a silicon substrate containing about 5 × 10 ¹⁹ cm ^{−3 of} phosphorus. The thickness of the buried insulating film 206 is 300 n
m, the thickness of the semiconductor layer 207 is about 50 nm. Further, by performing thermal oxidation, the thickness of the semiconductor layer 207 is reduced, and finally a film thickness of about 10 nm can be realized.

Subsequently, after removing the silicon oxide film on the surface with HF, the film is subjected to electron beam exposure and RIE etching technology.
The semiconductor layer 207 is processed to form the source 201 and the drain 2
No. 03 is formed and a space between them is processed into a thin line having a width of 10 nm and a length of 100 nm. A region having a small thickness is provided at two places 204a and 204b adjacent to the center of the thin line,
The region sandwiched between these regions is referred to as an island 209. The length of the region where the thickness of the thin wire is small is 20 nm, and the thickness is 5 nm.
Some degree is feasible. Island 209
Is about 20 nm in length.

Next, 100 Å is formed on the device by the CVD method.
A silicon oxide film having a thickness of about nm is grown, and an insulating film 20 is formed.
8 is formed. Subsequently, the source 201 and the drain 20 are formed by photolithography and RIE etching.
A contact hole is opened in the insulating film 208 on each of the regions 3 and aluminum is then evaporated to a thickness of about 300 nm. Aluminum is processed by a photolithography technique and an RIE etching technique, and an electrode is formed on the source 201 and the drain 203 and a gate 202 is formed on the insulating film 208 at the same time.

In the single electron device formed as described above, when a negative voltage of -2.5 V or more was applied to the gate 202, clear Coulomb blockade oscillation was observed at a temperature of 4K. This vibration was also observed at 50 K, and it was confirmed that high-temperature operation was possible.

Next, an example of the third embodiment shown in FIG. 3 will be described. As a method of manufacturing a single electronic device having the structure shown in FIG. 3, first, an SOI substrate is formed by a SIMOX method using a silicon substrate containing about 5 × 10 ¹⁹ cm ^{−3 of} phosphorus. The thickness of the buried insulating film 306 is 300 n.
m, the thickness of the semiconductor layer 307 is about 50 nm. Further, by performing thermal oxidation, the thickness of the semiconductor layer 307 is reduced, and finally a film thickness of about 10 nm can be realized.

Subsequently, after removing the silicon oxide film on the surface with HF, by electron beam exposure and RIE etching technology,
The semiconductor layer 307 is processed to form the source 301 and the drain 3
No. 03 is formed and a space between them is processed into a thin line having a width of 10 nm and a length of 100 nm. A narrow line width area is provided at two places 304a and 304b adjacent to the center of the thin line, and an area sandwiched between these areas is referred to as an island 309. A pattern is formed in an area having a small fine line width at the time of electron beam exposure. The width of the narrow region is 5 nm and the length is 1
A thickness of about 0 nm can be realized. The length of the region of the island 309 is about 20 nm.

The gate 302 is formed by processing the semiconductor layer 307 simultaneously with the formation of the thin wire 304. Next, a silicon oxide film having a thickness of about 100 nm is grown on the device by a CVD method, and an insulating film 308 is formed. Subsequently, a contact hole is opened in the insulating film 308 on each of the source 301, the drain 303, and the gate 302 by the photolithography technique and the RIE etching technique, and then aluminum is deposited to a thickness of about 300 nm. Aluminum is processed by optical lithography technology and RIE etching technology, and source 301 and drain 3
03 and the gate 302 are simultaneously formed on the insulating film 308.

In the single electron device formed as described above, when a negative voltage of -1.1 V or more was applied to the gate 302, clear Coulomb blockade oscillation was observed at a temperature of 4K. This vibration was also observed at 77K, confirming that high-temperature operation was possible.

Next, an example of the fourth embodiment shown in FIG. 4 will be described. As a method of manufacturing a single electronic device having the structure of FIG. 4, first, an SOI substrate is formed by a SIMOX method using a silicon substrate containing about 5 × 10 ¹⁹ cm ^{−3 of} phosphorus. The thickness of the buried insulating film 406 is 300 n.
m, the thickness of the semiconductor layer 407 is about 50 nm. Further, by performing thermal oxidation, the thickness of the semiconductor layer 407 is reduced, and finally a film thickness of about 10 nm can be realized.

Subsequently, after removing the silicon oxide film on the surface with HF, by electron beam exposure and RIE etching technology,
The semiconductor layer 407 is processed to form the source 401 and the drain 4
No. 03 is formed and a space between them is processed into a thin line having a width of 10 nm and a length of 100 nm. In the center of the thin line, three narrow regions are provided at three places 404a, 404b, and 404c adjacent to each other. Two regions sandwiched between these regions are referred to as islands 409. The area where the fine line width is narrow is
Perform pattern formation. The width of this narrow region is 5n.
m and a length of about 10 nm can be realized. The length of the region of the island 409 is about 10 nm.

Next, 100 Å is formed on the device by the CVD method.
A silicon oxide film having a thickness of about nm is grown, and an insulating film 40 is formed.
8 is formed. Subsequently, the source 401 and the drain 40 are formed by photolithography and RIE etching.
A contact hole is opened in the insulating film 408 on each of the regions 3, and thereafter, aluminum is deposited by about 300 nm. Aluminum is processed by a photolithography technique and an RIE etching technique, and an electrode is formed on the source 401 and the drain 403 and a gate 402 is formed on the insulating film 408 at the same time.

In the single electron device formed as described above, when a negative voltage of −3 V or more was applied to the gate 402, clear Coulomb blockade oscillation was observed at a temperature of 4K. This vibration was also observed at 77K, confirming that high-temperature operation was possible.

Although the embodiments of the four embodiments have been described above, the present invention is not limited to these embodiments.
The following modifications are conceivable. That is, SO
An SOS (Silicon On Sapphire) substrate may be used instead of the I substrate. Also, by annealing the polysilicon on the oxide film or the polysilicon, the single crystallized semiconductor is converted into the semiconductor layers 107, 207, 307, and 40.
7 may be used.

In the embodiment, the dopant in the semiconductor layer is n-type impurity phosphorus, but may be a p-type impurity such as boron. However, in this case, the conductivity type of the source and the drain is p-type. Further, the insulating films 108, 208,
As 308 and 408, a silicon nitride film or a SiON film may be used other than the silicon oxide film. In the third embodiment, the structure of the thin line 304 having a narrow region is described. However, as in the second embodiment, a thin line having a thin region is also formed with a gate in a semiconductor layer. It is easily possible to form

In the fourth embodiment, two islands 409 have been described. However, a structure in which three or more islands are connected in series can be easily realized. Further, a structure in which two or more islands are connected in parallel (for example, a plurality of fine wires 404 are formed in parallel between the source 401 and the drain 403) can be similarly realized.

[0055]

As described above, according to the present invention,
Even if the barrier height is increased, the impurity concentration of the fine wire is large enough to degenerate electrically, and the increase in the barrier width in the length direction (longitudinal direction) of the fine wire can be reduced. Since the device can be electrically confined, the device can operate at a high temperature of several tens of K or more.

Further, according to the present invention, since the gate is formed in the vicinity of the island by the semiconductor layer, the gate can be formed in the same process as the thin wire, and the device manufacturing process can be simplified.

Further, according to the present invention, a plurality of islands are formed and connected in series with each other, so that the influence of co-tunneling can be reduced and clear Coulomb blockade oscillation can be observed. Further, by connecting them in parallel with each other, it is possible to reduce variation in characteristics.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a third embodiment of the present invention.

FIG. 4 is a configuration diagram of a fourth embodiment of the present invention.

FIG. 5 is a configuration diagram of a conventional example.

[Explanation of symbols]

 101, 201, 301, 401 Source 102, 202, 302, 402 Gate 103, 203, 303, 403 Drain 104, 204, 304, 404 Fine wire 105, 205, 305, 405 Substrate 106, 206, 306, 406 Buried insulating film 107, 207, 307, 407 Semiconductor layer 108, 208, 308, 408 Insulating film 109, 209, 309, 409 Island

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 49/00 H01L 29/78 301J

Claims (6)

[Claims] 1. A single electronic device in which a buried insulating film and a semiconductor layer are laminated on a substrate, and wherein the semiconductor layer has a structure including a drain, a source, and a fine wire between the drain and the source, wherein the fine wire is electrically degenerated. Doping, and formed so that at least one island sandwiched between a plurality of electrical barrier regions is present, and the electrical barrier region is formed into a gate that is electrically insulated from the fine wire. A single electronic device characterized by being depleted based on an applied voltage. 2. The single electronic device according to claim 1, wherein the electric barrier region is a region in which the width of the fine line is smaller than the width of another region of the fine line. 3. The single electronic device according to claim 1, wherein the electric barrier region is a region in which the thickness of the fine wire is smaller than the thickness of another region of the fine wire. 4. The single electronic device according to claim 1, wherein the gate is formed near the island by the semiconductor layer. 5. The single gate according to claim 1, wherein the gate is formed on an insulating film covering the semiconductor layer and near the island. One electronic element. 6. The single electronic device according to claim 1, wherein a plurality of said islands are formed and connected in series or in parallel with each other.