JPH0775237B2 - Method for manufacturing field effect transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate field effect transistor (hereinafter abbreviated as MIS-FET), and in particular, an MIS-FET having an SOI structure having a small leakage current between a source and a drain in an off state. The present invention relates to a manufacturing method of.

[0002]

2. Description of the Related Art As a semiconductor element, a field effect transistor of a type in which a carrier moving in a semiconductor is controlled by an electric field created by an electrode called a gate has been widely used. In particular, the MIS-FET in which the gate electrode is provided on the gate region (channel) provided between the source and drain regions via the insulating film such as SiO ₂ has an extremely high input impedance and consumes less power. Moreover, it is a stable semiconductor element and is widely used as an element such as an IC or an LSI.

As an example of this MIS-FET, a conventional S
A typical MIS-FET having an OI (abbreviation of Silicon on Insulator) structure will be described with reference to FIGS.

First, low pressure CVD is performed on an insulating substrate 10 such as quartz.
Then, about 5000 Å of polycrystalline silicon is deposited, a thermal oxide film 13 serving as an insulating film of 1000 to 1500 Å is formed on the surface of this polycrystalline silicon, and then B ⁺ is implanted.

Next, the gate electrode 14 is formed by using a metal such as Mo.
After forming P, P ⁺ or As ⁺ is implanted and annealed in an inert gas at 700 ° C. to form a channel, a p-type region 11 and an n ⁺ -type source and drain region 1 are formed.
2 is formed. Finally, an oxide film is etched for electrode connection to form openings 17 and 18, and wirings 15 and 16 for connecting source / drain electrodes are formed using a metal such as aluminum to complete the MIS-FET.

In this case, the gate electrode 14 may be made of polycrystalline silicon doped with phosphorus. FIG. 4B is a plan view of this FET, and the sectional view shown in FIG.

[0007]

However, in such a conventional FET, since the As in the n ⁺ region diffuses along the grain boundaries of the polycrystalline silicon during the heat treatment, the leakage current in the off state is increased. There was a drawback that it increased.

The present invention eliminates such drawbacks, and provides a method for manufacturing an FET with extremely small leakage current in the off state.

In the conventional FET, the present inventors are directly affected by the diffusion of impurities because the source and drain regions and the gate region are directly joined as described above.
Further, it was thought that the problem of leakage current would occur due to insufficient electrical connectivity of these, and as a result of earnest research from this viewpoint, the present invention was reached.

[0010]

The present invention has been made to solve the above-mentioned conventional drawbacks, and in a method of manufacturing a field effect transistor, a silicon film is deposited on an insulating substrate and a silicon region is formed by etching. And a step of forming an oxide film on the surface of the silicon region,
A step of depositing an ion-implanted film on the oxide film and patterning so as to form a gear cup 1 in the central portion; a step of forming a channel region from above the pattern and implanting ions for controlling a threshold value; The step of removing the ion-implanted film and forming a pattern serving as a gate electrode so that the pattern width L thereof is larger than the gear cup l, and implanting n ⁺ or p ⁺ -type semiconductor region forming ions from above the gate electrode And a step of heat-treating the substrate in an inert gas atmosphere, and a step of forming an opening for source / drain electrode connection in the oxide film to form a source / drain electrode. .

[0011]

According to the method of manufacturing a field effect transistor as described above, a semiconductor region of opposite conductivity type is interposed between two n or p type semiconductor regions for setting source and drain regions, with an intrinsic semiconductor layer interposed therebetween. Since it is possible to provide a field-effect transistor that is bonded to a p-n junction of a source / drain region and a gate region,
It is possible to have an in structure and improve the junction characteristics, and at the same time, allow a margin for the p-type to n-type transition regions to reduce the influence of the diffusion of arsenic, phosphorus, etc. along the grain boundaries.
Thereby, the leakage current in the off state can be reduced.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view of essential parts showing one embodiment of the MIS-FET manufactured by the manufacturing method of the present invention.

MIS manufactured by the manufacturing method of the present invention
-FET is two polycrystalline silicon (n ⁺ type) that sets the source and drain regions formed on the insulating substrate 20.
Reverse conductivity type polycrystalline silicon (p-type) 21 for setting a channel region is interposed between 22 and these polycrystalline silicon (n ⁺ -type) and (p-type) are polycrystalline silicon (p-type), respectively. It is joined through an intrinsic semiconductor layer made of (undoped) 29.

A gate electrode 24 is formed on the channel region via a thermal oxide film 23 which is an insulating film, and openings 27 and 28 are formed in the source and drain regions.
The source / drain electrode connecting wirings 25 and 26 are joined together through.

The thickness of the polycrystalline silicon (undoped) 29 in the bonding direction is set to about several thousand Å.

Setting the source and drain regions 2
As one n or p type semiconductor region, a high concentration of group V or I
A so-called n ⁺ or p ⁺ type semiconductor containing a group II element is preferable, and n ⁺ or p ⁺ type silicon or germanium is usually used.

As a semiconductor region for setting the gate region, silicon of a conductivity type opposite to that of the source and drain regions (that is, p type when the source / drain is n type, n type when the source / drain is p type) is used. Alternatively, germanium or the like is used.

As the intrinsic semiconductor layer, an undoped semiconductor is used as it is. Specifically, silicon, germanium, or the like is used.

The optimum thickness in the joining direction is n or p.
Although it may vary depending on the thickness of the type semiconductor region or the reverse type semiconductor region, the thickness of the insulating film (these are sufficient as applied to the conventional FET), etc., it is usually about 100 to 1000.
0Å is preferred. If it is less than 100 Å, the effect of interposing the intrinsic semiconductor layer is insufficient, and if it exceeds 10,000 Å, the electric resistance in the intrinsic region becomes excessively large, and the current is limited, which is not preferable.

Each of these semiconductor regions and layers may be composed of any one of single crystal, polycrystal and amorphous semiconductors. In particular, low pressure CVD or plasma CV is performed on an insulating substrate.
A polycrystalline or amorphous silicon film formed by D, or a polycrystalline or single crystal silicon film deposited by low pressure CVD or plasma CVD and further formed by an annealing method using a laser beam, an electron beam, a lamp, etc. It is preferably applied.

Here, a specific manufacturing process of the MIS-FET will be described with reference to FIG.

First, a depressurized CV is applied on an insulating substrate 20 such as quartz.
Approximately 5000 liters of polycrystalline silicon was deposited at D and etched by a mixed gas plasma of CF ₄ and O ₂ , as shown in FIG.
As shown in (a), a polycrystalline silicon island 21 'is formed.

Next, as shown in FIG. 2B, a thermal oxide film 23 of about 1500 Å is formed on the surface of the polycrystalline silicon island, and then, for example, a Mo film is formed as an ion implantation mask to form 2
3'is patterned, a gear cup 1 is provided above the central portion of the polycrystalline silicon island 21 'of the pattern, and B ⁺ ions are implanted as channel region forming ions.

Further, after the Mo film is removed by etching, as shown in FIG. 2C, for example, Ti, Ta, M
A pattern to be the gate electrode 24 is formed by using a metal such as o or Al. At this time, the pattern width L is made larger than the gear cup 1 by about 3 μm.

The gate electrode 24 may be made of polycrystalline silicon.

Then, as shown in FIG. 2D, As ⁺ ions are implanted as n ⁺ type semiconductor region forming ions, and 70
Heat treatment is performed in an inert gas atmosphere at a temperature of 0 ° C.

Finally, as shown in FIG. 2E, openings 27, 2 for connecting the source / drain electrodes are formed in the thermal oxide film 23.
8 is formed, Al is deposited, and etching is performed to complete the FET having the structure shown in FIG.

However, when the gate pattern 24 is Al, the lift-off method is used instead of etching.

FIG. 1 obtained by the above manufacturing method.
FIG. 3 shows the results of evaluation of the characteristics of the FET and the conventional FET shown in FIG. 4 in which the intrinsic semiconductor layer is not interposed.
From the figure, it can be seen that the subthreshold current of the FET obtained by the present invention is greatly reduced and the switching characteristics are remarkably improved.

The semiconductor in the above-mentioned embodiments is not limited to the above-mentioned silicon material, and germanium and other electrode materials can be appropriately used in the same manner as these.

Further, the same effect is exhibited even in the structure in which the n-type region and the p-type region are replaced with each other in the above embodiment.

[0033]

According to the method of manufacturing a field effect transistor of the present invention, a semiconductor of a reverse conductivity type is interposed between two n or p type semiconductor regions for setting source and drain regions, with an intrinsic semiconductor layer interposed therebetween. Since it is possible to provide a field effect transistor that is joined to a region, p-n junctions of the source / drain regions and the gate region are respectively formed.
It is possible to have a -i-n structure and to improve the bonding characteristics.

It is possible to reduce the influence of the diffusion of arsenic, phosphorus, etc. by providing a margin for the p-type to n-type transition region, thereby reducing the leakage current in the off state.

Therefore, according to the manufacturing method of the present invention, an FET having an extremely high on / off current ratio can be obtained. Therefore, an FET which is extremely useful as an address element of various semiconductor devices, particularly an active matrix type liquid crystal display device. Can be provided.

[Brief description of drawings]

FIG. 1 is a MIS-FE produced by the production method of the present invention.
It is an important section sectional view showing one example of T.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of the MIS-FET shown in FIG.

FIG. 3 is a MIS-FE obtained by the manufacturing method of the present invention.
5 is a graph showing the Id and Vgs characteristics of T together with a comparative example.

4A is a sectional view illustrating a conventional MIS-FET, and FIG. 4B is a plan view thereof.

[Explanation of symbols]

10, 20 Insulating substrate 11, 21 Polycrystalline silicon (p type) 12, 22 Polycrystalline silicon (n ⁺ type) 13, 23 Thermal oxide film 14, 24 Gate electrode 15, 16, 25, 26 For connecting source / drain electrodes Wiring 17, 18, 27, 28 Source / drain connection opening 29 Polycrystalline silicon (undoped)

Claims (1)

[Claims] 1. A step of depositing a silicon film on an insulating substrate and forming a silicon region by etching, a step of forming an oxide film on the surface of the silicon region, and an ion implantation mask being formed on the oxide film to form a central region. Patterning so as to form a gear 1 in the portion, a step of implanting ions of a conductivity type opposite to that of the source / drain for forming a channel region from above the pattern, the ion implantation mask is removed, and the gate is removed. The pattern width L of the metal or polycrystalline silicon thin film pattern to be the electrode
Is formed to be larger than the gap l, a step of implanting n- or p-type semiconductor region forming ions from above the gate electrode, a step of heat-treating the substrate in an inert gas atmosphere, the oxide film And a step of forming a source / drain electrode connection opening to form a source / drain electrode, the method comprising: