JPH0225037A - Silicon thin film transistor and its manufacture - Google Patents

Abstract

PURPOSE:To prevent a gate electrode and an impurity Si layer from continuing and to obtain good transistor characteristics by a method wherein the film thickness of a second Si layer is made thick and the second Si layer and the n-type Si layer are formed continuously. CONSTITUTION:An Si nitride gate insulating layer 3, an amorphous Si first Si layer 4 and an Si nitride protective insulating layer 5 are formed on an insulative Si substrate 1 with a gate electrode 2 formed thereon, part of the layer 5 is removed to expose the layer 4 and a pair of contact parts 6 are formed. Then, a second Si layer (a film thickness of 100nm) 7 consisting of amorphous Si and an n-type Si layer (a film thickness of 30nm) 8 consisting of P-doped amorphous Si are formed in order. It is desirable that the layers 7 and 8 are formed continuously as they are in a vacuum state. Then, part of each layer 7 and 8 is removed and the layers 7 and 8 are respectively formed into the configurations of source and drain electrodes, each comprising either of a pair of the contact parts 6. Thereby, a thin film transistor is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a silicon thin film transistor used in active matrix liquid crystal displays and the like, and a method for manufacturing the same.

[Prior Art] FIG. 2 is a process cross-sectional view showing a conventional method for manufacturing a silicon thin film transistor.

The manufacturing method will be explained below using FIGS.

(a) On the insulating substrate 1 on which the gate electrode 2 is formed, a gate insulating layer 3 using silicon nitride, a silicon layer 4a using amorphous silicon, and a protective insulating layer 5 using silicon nitride are sequentially formed. Then, a portion of the protective insulating layer 5 is etched to expose the silicon layer 4a, and a pair of contact portions 6 overlapping with the ends of the gate electrode 2 are formed.

(b) An impurity silicon layer 8 containing an appropriate amount of, for example, phosphorus as an impurity is formed.

(C) Part of the impurity silicon layer 8 is etched, and this impurity silicon layer 8 is attached to the pair of contact portions 6.
The source and drain electrodes are formed in the shape of the source and drain electrodes.

By the above manufacturing method, a silicon thin film transistor as shown in FIG. 2(c) was formed.

[Issue to be solved ml] In the silicon thin film transistor manufactured as described above, stress is concentrated on the gate insulating layer 3 or the silicon layer 4a formed near the end of the gate electrode 2, and cracks are likely to occur in this portion. When this crack reaches the gate electrode 2, when forming the impurity silicon layer 8 in the step shown in FIG. A problem arises in that the impurity silicon layer 8 serving as the source and drain electrodes becomes conductive. Even if the crack does not reach the gate electrode 2, the gate insulating layer 3 and the protective insulating layer 5 are usually formed of the same kind of material, so the protective insulating layer is removed in the process shown in FIG. When etching the layer 5, the gate insulating layer 3 is simultaneously etched through the cracks in the silicon layer 4a, and the holes reach the gate electrode 2 in the same way as above, and the gate electrode 2 and the impurity silicon layer 6 are also electrically connected. A problem arises.

The present invention has been made to solve the above-mentioned conventional problems,
It is an object of the present invention to provide a silicon thin film transistor in which conduction between a gate electrode and an impurity silicon layer is not established, and a method for manufacturing the same.

[Means for Solving the Problems] The present invention provides a gate electrode formed on an insulating substrate, a gate insulating layer formed on the insulating substrate on which this gate electrode is formed, and this gate insulating layer. A protective insulation layer formed on the first silicon layer except for a first silicon layer formed on the first silicon layer and a pair of contact portions overlapping the ends of the gate electrode on the first silicon layer. a pair of second silicon layers having the shapes of source and drain electrodes and in contact with the first silicon layer on the pair of contact portions; and a pair of second silicon layers formed on the pair of second silicon layers. The above object is achieved by a thin film transistor characterized by having a pair of impurity silicon layers.

Further, in the silicon thin film transistor, a gate insulating layer, a first silicon layer, and a protective insulating layer are sequentially formed on an insulating substrate on which a gate electrode is formed, and a part of the protective insulating layer is removed to form the first silicon thin film transistor. a step of exposing the silicon layer and forming a pair of contact portions overlapping the end portions of the gate electrode; a step of sequentially forming a second silicon layer and an impurity silicon layer; and a step of sequentially forming a second silicon layer and an impurity silicon layer. Preferably, the manufacturing method includes a step of removing a portion of the silicon layer and forming the second silicon layer and the impurity silicon layer in the shape of the source and drain electrodes including the pair of contact portions.

Further, in the above manufacturing method, it is preferable that the second silicon layer and the impurity silicon layer are formed continuously in a vacuum state.

[Example] An example of the present invention will be described below based on the drawings.

In FIG. 1, 1 is an insulating substrate, 2 is a gate electrode, and 3 is an insulating substrate.
is a gate insulating layer made of silicon nitride, 4 is a first silicon layer made of amorphous silicon, 5 is a protective insulating layer made of silicon nitride, 6 is a contact portion, and 7 is made of amorphous silicon. The second silicon layer 8 is an n-type silicon layer made of amorphous silicon doped with phosphorus.

The manufacturing process will be explained below using FIGS.

(a) On an insulating substrate 1 on which a gate electrode 2 is formed, a gate insulating layer 3 made of silicon nitride, a first silicon layer (thickness 30 nm) 4 made of amorphous silicon, and a layer made of silicon nitride are formed. A protective insulating layer 5 is formed, and the protective insulating layer 5 is
A portion of the first silicon layer 4 is removed to expose the first silicon layer 4 and form a pair of contact portions 6.

(b) A second silicon layer (thickness 100100 nm) using amorphous silicon and an n-type silicon layer (thickness 30 nm) 8 made of amorphous silicon doped with phosphorus are formed in sequence. It is preferable that the silicon layer 7 and the n-type 2932 layer 8 are formed continuously in a vacuum state so as not to cause deterioration of the interface characteristics between the two.

(C) Second silicon layer 7 and n-type 2932 layer 8
The second silicon layer 7 and the n-type 2932 layer 8 are formed in the shape of source and drain electrodes including the pair of contacts 6. The contact portion refers to a connection point between the second silicon layer 7 formed in the shape of the source and drain electrodes and the first silicon layer 4.

By the above manufacturing method, a silicon thin film transistor as shown in FIG. 3(c) can be obtained.

Note that the first silicon layer 4, the second silicon layer 7,
The formation temperature and film thickness of the n-type 2932 layer 8 are preferably set as follows.

First silicon layer 20-30 nm, 350-600"C Second silicon layer 50 nm or more 250-3006C N-type silicon layer 20-50 nm, 200-300°C In the silicon thin film transistor described above, the gate electrode 2 Even if there are holes that reach the contact part 6 from
Since the n-type 2932 layer 8 is formed via the second silicon layer 7, the gate electrode 2 and the n-type 2932 layer 8 are not electrically connected as in the conventional case. Moreover, it is also possible to fill the holes when forming the second silicon layer 7.

Furthermore, if the thickness of the second silicon layer 7 is increased, the n-type 293 forming the gate electrode 2 and the source and drain electrodes can be formed.
The dielectric strength with respect to the second layer 8 can be increased.

Further, when the second silicon layer 7 and the n-type 2932 layer 8 are formed continuously in a vacuum state, the interface characteristics between them do not deteriorate, so that good transistor characteristics can be obtained.

Note that the first silicon layer 4, the second silicon layer 7, and the n-type 2932 layer 8 are not limited to amorphous silicon, and polysilicon or the like may be used.

[Effects of the Invention] According to the present invention, even if a hole is generated that reaches the contact portion from the gate electrode, the gate electrode and the n-type silicon layer will not be electrically connected to each other, and the second silicon layer may eliminate the hole. This makes it possible to fill in the gaps, significantly improving yield.

Further, by increasing the thickness of the second silicon layer, it is possible to improve the dielectric strength between the gate electrode and the source and drain electrodes.

Furthermore, good transistor characteristics can be obtained by continuously forming the second silicon layer and the n-type silicon layer in a vacuum state.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the manufacturing process of an embodiment of a silicon thin film transistor according to the present invention, and FIG. 2 is a sectional view showing the manufacturing process of a conventional silicon thin film transistor. 1... Insulating substrate 2... Gate electrode 3... Gate insulating layer 4... First silicon layer 5... Protective insulating layer 6... Contact portion 7... Second silicon Layer 8...n-type silicon layer

Claims (3)

[Claims] (1) A gate electrode formed on an insulating substrate, a gate insulating layer formed on the insulating substrate on which this gate electrode was formed, and a first silicon layer formed on this gate insulating layer. and, except for a pair of contact portions overlapping the ends of the gate electrode on the first silicon layer,
a protective insulating layer formed on the silicon layer; a pair of second silicon layers having the shape of source and drain electrodes and in contact with the first silicon layer on the pair of contact portions; A thin film transistor comprising a pair of impurity silicon layers formed on a second silicon layer. (2) A gate insulating layer, a first silicon layer, and a protective insulating layer are sequentially formed on the insulating substrate on which the gate electrode is formed, and a part of the protective insulating layer is removed to form the first silicon layer. forming a pair of contact portions overlapping with the end portions of the gate electrode; sequentially forming a second silicon layer and an impurity silicon layer; and forming the second silicon layer and the impurity silicon layer. 2. The step of forming the second silicon layer and the impurity silicon layer in the shape of source and drain electrodes including the pair of contact portions by removing a portion of the silicon layer. Method for manufacturing silicon thin film transistors. (3) The method of manufacturing a silicon thin film transistor according to claim 2, wherein the second silicon layer and the impurity silicon layer are formed continuously in a vacuum state.