JP3530749B2 - Active matrix device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention refers to an insulating substrate (in this specification, refers to the entire object having an insulating surface, and unless otherwise specified, not only on an insulating material such as glass but also on a material such as a semiconductor or a metal. (Also referred to as an insulating layer formed on the substrate), and an active matrix circuit formed using a thin film insulating gate type semiconductor device (also referred to as a thin film transistor or a TFT) formed thereon. In particular, the present invention relates to a monolithic active matrix circuit having peripheral circuits for driving the active matrix circuit on the same substrate. The monolithic active matrix circuit according to the present invention is used for a matrix type display (display device) such as a liquid crystal display or a plasma display.

[0002]

2. Description of the Related Art As shown in FIG. 5, a monolithic active matrix circuit is divided into an active matrix circuit area, a source driver and a gate driver, which are formed by substantially the same process. In the active matrix circuit, TFTs are used as switching elements of liquid crystal cells. In order to supplement the capacitance of the liquid crystal cell, an auxiliary capacitance is usually provided in parallel with the liquid crystal cell. Peripheral circuits such as a source driver and a gate driver are composed of a shift register and a switch element, which are required to operate at high speed. Therefore, the monolithic active matrix circuit is configured using a crystalline semiconductor (for example, polycrystalline silicon). In addition, the peripheral circuit is a complementary circuit (CM
OS). For these technologies,
For example, it is described in JP-A 1-289917. Among them, for example, a T forming a switching TFT of an active matrix circuit and a shift register of a peripheral circuit.
It is shown that the FT has substantially the same cross-sectional structure.

[0003]

However, a TFT as a switching element of an active matrix circuit is provided.
TFTs in CMOS circuits, such as shift registers
And the behavior is not the same. For example, in a TFT of a switching element, a large reverse bias voltage (negative in the case of N-channel type) is applied to a gate electrode, but in a TFT in a CMOS logic circuit, a reverse bias voltage is basically applied. It is not applied. Also, the former operation speed is 1 of the speed required for the latter.
/ 100 or less is sufficient. As described above, it is not preferable to use the TFTs having the same structure, which are different in use conditions and required characteristics.

[0004]

According to the present invention, the structure of a TFT as a switching element used in an active matrix circuit and a TFT used in a CMOS logic circuit represented by a shift register of a peripheral circuit are changed. By doing so, the circuit is optimized. That is, the source / drain of the TFT of the active matrix circuit is substantially N-type or P-type.
Only one of the impurities of the type is doped, and the source / drain of the TFT of the peripheral circuit of the same conductivity type as the TFT of the active matrix circuit is doped with both the N type and the P type impurities.

For example, the TF of an active matrix circuit
If T is a P-channel type, the impurities doped into the source / drain are P-type impurities. on the other hand,
The impurities doped into the source / drain of the P-channel TFT of the peripheral circuit are both P-type impurities and N-type impurities. Of course, in general, the concentration of P-type impurities is N
It goes without saying that the concentration is higher than the concentration of the type impurities. In particular, in the present invention, a sidewall is formed on the side surface of the gate electrode / wiring, and by using this, a TFT having an optimum structure is obtained. The formation of the sidewall in the present invention is performed by depositing an insulating film covering the gate electrode / wiring and anisotropically etching this. In this way, the low-concentration drain (LD) is used by using the substantially triangular insulator (sidewall) formed on the side surface of the gate electrode / wiring as a mask at the time of doping.
D) Structure, offset gate structure, etc. are formed.

A process for obtaining an LDD by forming such a side wall will be described with reference to FIG. First, an island-shaped crystalline semiconductor region 1 is formed on a substrate 101.
Form 03. The base insulating film 102 may be formed over the substrate. Then, after depositing the gate insulating film 104, the gate electrode 105 and the gate wiring 106 are formed of an appropriate material. As a material for the gate electrode / wiring, a material capable of anodizing, for example, aluminum is preferably used. (Fig. 1 (A))

After that, ions of a doping impurity are accelerated and irradiated to expose the gate electrode 1 to the semiconductor region.
The impurity region 109 is formed using 05 as a mask. If phosphorus is used as the doping impurity, the impurity region becomes N-type, and if boron is used, it becomes P-type. By adjusting the concentration and mixing ratio of these impurities, the degree of conductivity type of the impurities can be controlled. In order to obtain the LDD structure, it is necessary to reduce the doping amount (dose amount).
An offset gate structure can be obtained without doping, and a normal source / drain can be obtained by doping with high concentration. (Fig. 1 (B))

The gate electrode / wiring may be anodized to form the anodic oxide coating 108 before the doping step. This anodic oxide film serves as an etching stopper in the subsequent anisotropic etching step and protects the gate electrode. Also, the same effect is
It can also be obtained by forming a film such as a silicon nitride film on the gate electrode. After that, an insulator film 110 is formed so as to cover the gate electrode / wiring (and the anodic oxide film around it).
Coverability is important in forming this coating, and a thickness of 1/3 to 2 times the height of the gate electrode / wiring is suitable. For this purpose, plasma CVD method or low pressure CVD method,
A chemical vapor deposition (CVD) method such as atmospheric pressure CVD method is preferable. As a result, the thickness of the silicon oxide film on the side surface of the gate electrode / wiring is increased by the amount shown by the dotted line in FIG. (Fig. 1 (C))

The insulator thus formed is preferentially etched in a direction substantially perpendicular to the substrate by anisotropic etching. This needs to be performed at least to the extent that the insulating film 110 in the flat portion is etched, and the etching may be advanced to such an extent that the gate insulating film thereunder is etched. As a result, the side surfaces of the gate electrodes and wiring, since originally thicker insulating material film, a substantially triangular-shaped insulator (sidewall) 111 and 112 left behind. (Fig. 1 (D))

After that, high-concentration impurity doping is performed using the sidewalls 111 and 112 as a doping mask to form the source / drain 114. Also,
In the region below the sidewall, LDD region 113 is formed because no doping is performed. (Fig. 1
(E) After that, the doped impurities are activated by means such as thermal annealing, irradiation of laser light or intense light equivalent thereto (optical annealing). Further, the interlayer insulator 115
After the formation of the wiring, a contact hole is formed in one or both of the source / drain of the TFT, and the wiring 1
16 and 117 are formed. (Fig. 1 (F))

A TFT having an LDD structure can be obtained through the above steps. Although this is not limited to the LDD structure, as shown in FIG.
In the structure having the sidewall 112 on the side surface of 06,
The step of the second-layer wiring 117 over the gate wiring 106 is gentle due to the presence of the sidewalls 112, so that it is effective in preventing disconnection.

In this way, an LDD structure, an offset gate structure, etc. can be obtained. In the present invention, the N-channel type TFT which needs the hot carrier countermeasure has the LDD structure, and the P-channel type TFT which does not need it has the normal or offset gate structure. In the present invention, the TFT used for the active matrix circuit may be an N-channel type or a P-channel type, but the P-channel type is preferable from the viewpoint of less deterioration of characteristics. Hereinafter, the present invention will be described in more detail with reference to examples.

[0013]

EXAMPLES Example 1 FIG. 2 shows the present example. First, as a base oxide film 202 on a substrate (Corning 7059) 201, a thickness of 1000 to 5000Å, for example, 20
A 00Å silicon oxide film was formed. As a method for forming this oxide film, a sputtering method in an oxygen atmosphere was used. However, in order to further improve mass productivity, TEOS is used as plasma C
It may be formed by decomposing / depositing by the VD method. Further, the silicon oxide film thus formed may be annealed at 400 to 650 ° C.

After that, an amorphous silicon film of 300 to 500 is formed by plasma CVD method or LPCVD method.
0Å, preferably 400 to 1000Å, for example 500
Å Deposit and place this in a reducing atmosphere at 550 to 600 ° C for 8
Allow to crystallize by standing for ~ 24 hours. In that case, a small amount of a metal element such as nickel that promotes crystallization may be added to promote crystallization. Further, this step may be performed by laser irradiation. Then, the silicon film crystallized in this way was etched to form island regions 203, 204 and 205. In FIG.
The island-shaped regions 203 and 204 are TFTs of the peripheral circuit,
The island region 205 means a region for forming a TFT of an active matrix circuit. Further, a silicon oxide film 206 having a thickness of 700 to 1500 Å, for example, 1200 Å, was formed on this by a plasma CVD method.

Thereafter, the thickness is 1000Å to 3 μm, for example, 5000Å of aluminum (0.1 to 0.5 wt%).
Film (including Sc (scandium)) is formed by a sputtering method and is etched to form a gate electrode 207,
208 and 209 were formed. Although not apparent in the figure, all the gate electrodes 207 to 209 are connected. (Fig. 2
(A))

Then, an electric current is applied to the gate electrodes 207 to 209 in an electrolytic solution to carry out anodization to obtain a thickness of 500 to 2500.
Å, for example, 2000 Å anodic oxide coating was formed on the top and side surfaces of the gate electrode. The electrolytic solution used was L-
Although tartaric acid was diluted with ethylene glycol at a concentration of 5% and the pH was adjusted to 7.0 ± 0.2 with ammonia, other suitable solutions may be used. The substrate 201 is dipped in an electrolytic solution, the + side of the constant current source is connected to the gate wiring on the substrate, and the platinum electrode is connected to the-side of the substrate 2
A voltage was applied in a constant current state of 0 mA, and oxidation was continued until it reached 150V. Furthermore, the oxidation was continued at a constant voltage of 150 V until the current became 0.1 mA or less. As a result, an aluminum oxide film having a thickness of 2000Å was obtained. After the anodic oxidation process was completed, the gate electrode / wiring was divided, and the necessary portions were electrically separated. This dividing step may be performed in a later step.

After that, the photoresist mask 210 is used to form regions 203 and 2 for forming P-channel TFTs.
05, and by ion doping, phosphorus is self-alignedly implanted into the island-shaped silicon film 204 using the gate electrode portion (that is, the gate electrode and the anodic oxide film around it) as a mask to form an N-type low-concentration impurity region. (LDD) 211 was formed. Dose amount is 1 × 10 ¹³ to 1 × 10 ¹⁴ atoms / cm
² , the acceleration voltage was 10 to 90 kV, for example, the dose amount was 2 × 10 ¹³ atoms / cm ² , and the acceleration voltage was 80 kV.
(Fig. 2 (B))

Then, as in the step of FIG. 1C, a silicon oxide film was deposited by the plasma CVD method. Here, TEOS and oxygen or monosilane and nitrous oxide were used as the source gas. The thickness of the silicon oxide film is
The optimum value depends on the height of the wiring. For example, when the height of the gate electrode / wiring is about 6000 Å including the anodic oxide film as in this embodiment, it is preferably ⅓ to 1.2 μm, which is ⅓ to Ⅻ of the height.
It was 0Å. In this film forming process, it is required that the film thickness be uniform in the flat portion and that the step coverage be good.

Next, similar to the step of FIG. 1D, the above-mentioned silicon oxide film was etched by performing anisotropic dry etching by the known RIE method.
In this etching process, the gate insulating film 206 was also etched. Through the above steps, a substantially triangular insulator (sidewall) 21 is formed on the side surface of the gate electrode / wiring.
2, 213 and 214 remained. Also, the gate insulating films 215, 216, and 2 are formed under the sidewalls and the gate electrode portion.
17 remained. (FIG. 2C) After that, phosphorus was again introduced by the ion doping method. At this time, only the active matrix circuit portion was covered with a photoresist mask 218. As can be seen from FIG. 5, the peripheral circuit and the active matrix circuit are apart from each other to some extent, so that this patterning was relatively easy.

In this case, the dose amount is set to be one to three orders of magnitude larger than the dose amount in the step of FIG. Moreover, since the gate insulating film is etched, the acceleration voltage is 10 to 30 k.
V was suitable. In the present embodiment, the dose is 1 × 10 ¹⁵ atoms / cm ^{2 which} is 50 times the dose of the first phosphorus doping. The acceleration voltage was 10 kV. As a result, regions (source / drain) 219 and 220 in which a high concentration of phosphorus is introduced.
Was formed. On the other hand, a low-concentration N-type region was left below the sidewall 213, adjacent to the high-concentration N-type region 220. (Fig. 2 (D))

Subsequently, by the ion doping method,
Boron was introduced. At this time, the region 204 for forming the N-channel type TFT was covered with a photoresist mask 221. The dose amount in this case was set larger than the dose amount of phosphorus in the step of FIG. 2D because the N-type region 219 was inverted to P-type. In this embodiment, the dose is 3 × 10 ¹⁵ atoms / cm ^{2 which} is three times the dose of phosphorus doping shown in FIG. The acceleration voltage was 10 kV. As a result, the N-type region 219
Became a P-type region and became a P-type region 222. In addition, the island-shaped region 205 was also doped with boron to form a P-type region (source / drain) 223. (Fig. 2 (E))

Further, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated to activate the doped impurities. (Laser annealing process) Energy density of laser is 200-4
00 mJ / cm ² , preferably 250 to 300 mJ / c
m ² was suitable. This step may be performed by thermal annealing instead of laser irradiation. Also, thermal annealing may be performed after laser irradiation.

Next, C as an interlayer insulator 224 is formed on the entire surface.
A silicon oxide film having a thickness of 5000 Å was formed by the VD method.
Then, contact holes were formed in the source / drain of the TFT. At this time, the contact hole 225 was also formed in the impurity region on the pixel electrode side of the TFT of the active matrix circuit. Then, the second-layer aluminum wiring / electrodes 226 to 229 were formed. The thickness of aluminum wiring is almost the same as that of the gate electrode / wiring, 4000-600
It was 0Å. No metal wiring was formed in the contact hole 225. Here, paying attention to the active matrix circuit, the metal wiring 229 is a signal line. The gate electrode 209 is connected to the gate line. (Fig. 2
(F))

Finally, a passivation film 230 of a silicon nitride film was formed by the plasma CVD method. And
A contact hole was formed again in the portion where the contact hole 225 was formed to expose the impurity region. An indium tin oxide (ITO) film, which is a transparent conductive material, was deposited by a sputtering method, and this was etched to form a pixel electrode 231.

In this way, the P- channel type thin film transistor 232 of the peripheral driving circuit, the N- channel type thin film transistor 233 of the same, and the P-channel type thin film transistor 234 of the active matrix circuit were obtained. As is clear from the above steps, the transistors 232 and 234 are
Both are P-channel type having an offset gate structure, but the source / drain is doped with impurities, the former being both phosphorus and boron, whereas the latter is only boron. In particular, the latter structure is advantageous when a large reverse bias voltage is applied like a switching element of an active matrix circuit.

[Embodiment 2] This embodiment relates to a monolithic active matrix circuit, and its outline is shown in FIG.
Shown in (A), (B), and (C). The method of manufacturing the element of this example is basically the same as that of Example 1 (see FIG. 2).
This embodiment is a further development of the monolithic active matrix circuit shown in FIG. The transistors 401 and 402 are an N-channel type and a P-channel type, respectively, and each represents a transistor used for a peripheral driver circuit. Further, in the peripheral drive circuit, a contact 403 between the gate wiring and the second layer wiring 404 is provided. At this time, contact holes are formed in both the interlayer insulator and the anodic oxide.
(Fig. 4 (A))

A circuit diagram of a unit pixel of the active matrix circuit is shown in FIG. In this embodiment, a double gate circuit in which two transistors 405 and 406 are connected in series is used as a switching element. Further, on the island regions which connect the pixel electrode 408 to form a wiring 407 of the same layer as the gate electrode, and an auxiliary capacitor 40 9 a gate insulating film as a dielectric. Wiring 407 as a capacitor line, kept at a constant voltage, so that the MOS capacitor is formed between the island region. (Figure 4 (B), (C))

[Embodiment 3] FIG. 3 shows the present embodiment. The crystalline island-shaped silicon region 3 is formed on the substrate 301 on which a 2000 Å-thick silicon oxide film is formed as the base oxide film 302.
03, 304 and 305 were formed. Further, a silicon oxide film 3 having a thickness of 1200 Å is formed on this by a plasma CVD method.
06 was formed. In FIG. 3, island regions 303, 3
Reference numeral 04 denotes a peripheral circuit TFT, and island-shaped region 305 denotes a region for forming an active matrix circuit TFT. Further, a 5000 Å-thick aluminum gate electrode 30 whose side and top surfaces are anodized is used.
7, 308 and 309 were formed. (Fig. 3 (A))

Then, regions 303 and 3 for forming P-channel TFTs are formed by a photoresist mask 310.
05, and phosphorus was implanted into the island-shaped silicon film 304 by ion doping in a self-aligned manner using the gate electrode portion as a mask to form a low concentration N-type region 311. The doping conditions were a dose of 2 × 10 ¹³ atoms / cm ² and an accelerating voltage of 80 kV. (Fig. 3 (B))

Next, the region 304 for forming the N-channel TFT and the active matrix region 305 are covered with a photoresist mask 312, and self-aligned with the gate electrode portion on the island-shaped silicon film 303 by an ion doping method. Boron was then implanted to form a high concentration P-type region 313. The doping conditions were a dose of 3 × 10 ¹⁵ atoms / cm ² and an accelerating voltage of 60 kV. (FIG. 3 (C)) And by the process shown in FIG.
Sidewalls 31 are formed on the sides of the gate electrodes 307 to 309.
4, 315, 316 were formed. In addition, the gate insulating films 317 and 318 are formed under the sidewalls and the gate electrode portion.
319 remained. (Fig. 3 (D))

Then, again by the ion doping method.
Then, phosphorus was introduced. In this case, active matrix times
Cover only the path with a photoresist mask 320
It was The dose amount in this case is the dose of the process of FIG.
It was 1-3 digits more than the quantity. Also, the gate insulating film is etched
Is appropriate, the accelerating voltage should be 10 to 30 kV.
Met. In this example, the first phosphorus doping dose is
50 times the amount of 1 x 10 ¹⁵Atom / cm²And Accelerating power
The pressure was 10 kV. As a result, a high concentration of phosphorus was introduced.
An N-type region (source / drain) 321 is formed.
However, in the region 313 where boron was introduced previously,
The boron dose is greater than the phosphorus dose
Therefore, it remained P-type. In addition, the area 313
The region under the id wall 314 is completely phosphorus-doped.
Was not done. Furthermore, at the bottom of the sidewall 315
Is adjacent to the high-concentration N-type region 321, and is a low-concentration N-type region.
Was left. (Fig. 3 (E))

Next, the photoresist mask 320 was removed, and a low concentration of boron was introduced by an ion doping method. In this case, the dose amount is preferably one to three orders of magnitude lower than the previous dose amount of boron. In this embodiment, 3 × 10 ^{13 which is} 1/100 of the dose of boron in FIG.
Atom / cm ² . The acceleration voltage was 10 kV. As a result, a low concentration P-type region 322 was formed in the island-shaped region 305 forming the TFT of the active matrix circuit. (Fig. 3 (F))

Further, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated to activate the doped impurities. (Laser annealing process) The energy density of the laser is 200 to 400 mJ / cm.
² , preferably 250-300 mJ / cm ² . This step may be performed by thermal annealing instead of laser irradiation. Also, thermal annealing may be performed after laser irradiation.

Finally, as in the first embodiment, the interlayer insulator 32
3, metal wirings 324 to 327, passivation film 32
8. An ITO pixel electrode 329 was formed. (Fig. 3
(G)) In this way, the N-channel thin film transistor of the peripheral drive circuit, the same P-channel thin film transistor, and the P-channel thin film transistor 234 of the active matrix circuit could be obtained. As is apparent from the above steps, in this embodiment, the N-channel TFT of the peripheral circuit has the LDD structure. The P-channel type TFT has a normal structure in the peripheral driving circuit, but has the offset gate type in the active matrix circuit. Moreover, the source / drain of the TFT of the active matrix circuit is only lightly doped.

Such a structure is ideal for use as a switching element of an active matrix circuit. That is, the offset gate type is a leakage current (OF) when a reverse bias voltage is applied to the gate electrode.
(Also referred to as F current) is small, and the outflow of charges held in the pixel cell is suppressed. Further, when the source / drain impurity concentration is low, it is possible to prevent characteristic deterioration caused by application of a reverse bias voltage. On the other hand, since high speed operation is desired in the peripheral circuit, it is preferable to use a TFT having a normal structure as shown in the figure.

[Embodiment 4] This embodiment relates to a monolithic active matrix circuit, and its outline is shown in FIG.
Shown in (D), (E), and (F). The method of manufacturing the element of this example is basically the same as that of Example 3 (see FIG. 3).
This embodiment is a further development of the monolithic active matrix circuit shown in FIG. The transistors 411 and 412 are an N-channel type and a P-channel type, respectively, and each represents a transistor used in a peripheral driver circuit. Further, in the peripheral driving circuit, a contact 413 between the gate wiring and the second layer wiring 414 is provided. At this time, contact holes are formed in both the interlayer insulator and the anodic oxide.
(Fig. 4 (D))

A circuit diagram of a unit pixel of the active matrix circuit is shown in FIG. In this embodiment, two transistors 415 and 416 are connected in series as switching elements. Then, as in the second embodiment, the island region and the wiring 4 are formed.
A MOS capacitor 419 is formed by the element 17. In addition, the passivation film and the interlayer insulator are etched, and the anodic oxide is used as a dielectric, and the pixel electrode and the wiring 417 are formed.
A capacity 420 was also constructed between them. Similarly to the second embodiment, the wiring 417 is kept at a constant voltage as a capacitance line.
(Fig. 4 (E), (F))

[0038]

According to the present invention, a TFT having required characteristics and reliability is shown in each circuit of a monolithic active matrix circuit, which is useful for improving display characteristics of the matrix circuit.

[Brief description of drawings]

FIG. 1 shows an outline of a sidewall manufacturing process in the present invention.

FIG. 2 shows a method of manufacturing a TFT circuit according to the first embodiment.

FIG. 3 shows a method for manufacturing a TFT circuit according to a second embodiment.

FIG. 4 shows an example of a TFT circuit of Examples 3 and 4.

FIG. 5 shows a block diagram of a monolithic active matrix circuit.

[Explanation of symbols]

101 glass substrate 102 Underlayer oxide film (silicon oxide) 103 island-shaped silicon region (active layer) 104 Gate insulation film 105 Gate electrode (aluminum) 106 Gate wiring (aluminum) 107, 108 Anodic oxide (aluminum oxide) 109 Weak N-type impurity region 110 Insulator coating (silicon oxide) 111,112 Sidewall 113 LDD (low concentration impurity region) 114 source / drain 115 Interlayer insulation film (silicon oxide) 116, 117 Metal wiring / electrode (aluminum)

Continuation of the front page (56) Reference JP-A-1-289917 (JP, A) JP-A-4-177873 (JP, A) JP-A-5-235350 (JP, A) JP-A-5-241201 (JP , A) JP-A-5-259891 (JP, A) JP-A-6-77252 (JP, A) JP-A-6-242433 (JP, A) JP-A-7-146491 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) G02F 1/1368 G02F 1/1345

Claims (5)

(57) [Claims] 1. A display device having a monolithic active matrix circuit including a source driver, a gate driver and an active matrix circuit, wherein the active matrix circuit has a switching element in each of a plurality of pixels and an auxiliary connected to the switching element. The switching element has a capacitance, the switching element has a semiconductor layer including a source region, a drain region, and a channel formation region, a gate insulating film in contact with the semiconductor layer, a gate electrode in contact with the gate insulating film,
Oh it has a electrically connected to the pixel electrode electrically connected to the signal line and the drain regions to the source region
A full set gate structure, the storage capacitor, the capacitor line in the same layer as the gate electrode, the auxiliary first made of an insulating material between a portion of a part and the capacitor line and the semiconductor layer of said semiconductor layer Capacity and the capacity
Line, between the pixel electrode and the capacitance line and the pixel electrode
The source driver and the gate driver have a second auxiliary capacitance made of an insulator,
CMO including channel type TFT and P channel type TFT
The semiconductor layer of the N-channel type TFT has a source region, a drain region, a channel forming region and a low concentration impurity region, and the semiconductor layer of the P-channel type TFT has a source region, a drain region and a channel. Ri Do from the formation region, a source region and a drain region of the switching element
Contains only P-type impurities,
The source region and the drain region have N-type impurities and P-type impurities.
A source region of the switching element, including both pure ones
And the concentration of the P-type impurity contained in the drain region is
Included in the source and drain regions of P-channel TFT
Lower than the concentration of P-type impurities contained in the source region and drain region of the N-channel TFT
The concentration of the N-type impurity contained in the
N-type dopant included in the source and drain regions of the FT
The concentration of the N-channel TFT is lower than that of the pure substance.
A display device characterized in that the concentration is high by the concentration of N-type impurities contained in the pure region . 2. A display device having a monolithic active matrix circuit including a source driver, a gate driver, and an active matrix circuit, wherein the active matrix circuit has a switching element in each of a plurality of pixels and an auxiliary connected to the switching element. The switching element has a capacitance, the switching element includes a semiconductor layer including a source region, a drain region, and two channel forming regions, a gate insulating film in contact with the semiconductor layer, two gate electrodes in contact with the gate insulating film, and the source. an offset gate structure which have a electrically connected to the signal line and electrically connected to the pixel electrode to the drain region to region, the storage capacitor, the capacitance lines of the same layer as the gate electrode, the semiconductor layer some or insulator between the portion of the capacitive line and the semiconductor layer The first auxiliary capacitor and the capacitor that
Line, between the pixel electrode and the capacitance line and the pixel electrode
The source driver and the gate driver have a second auxiliary capacitance made of an insulator,
CMO including channel type TFT and P channel type TFT
The semiconductor layer of the N-channel type TFT has a source region, a drain region, a channel forming region and a low concentration impurity region, and the semiconductor layer of the P-channel type TFT has a source region, a drain region and a channel. Ri Do from the formation region, a source region and a drain region of the switching element
Contains only P-type impurities,
The source region and the drain region have N-type impurities and P-type impurities.
A source region of the switching element, including both pure ones
And the concentration of the P-type impurity contained in the drain region is
Included in the source and drain regions of P-channel TFT
Lower than concentration of Murrell P-type impurity, a source region and a drain region of the N-channel type TFT
The concentration of the N-type impurity contained in the
N-type dopant included in the source and drain regions of the FT
The concentration of the N-channel TFT is lower than that of the pure substance.
A display device characterized in that the concentration is high by the concentration of N-type impurities contained in the pure region . 3. A display device according to claim 1 or claim 2 characterized by having a sidewall on a side surface of the gate electrode. 4. The pixel electrode is a first electrode on the gate electrode.
Is connected to the switching element through a first contact hole provided in the interlayer insulator and a second contact hole provided in a second interlayer insulator on the first interlayer insulator, diameter of first contact holes, a display device according to any one of claims 1 to 3, characterized in that greater than a diameter of the second contact hole. 5. An insulator between the capacitance line and the pixel electrode
Is an oxide of the capacitance line.
The display device according to any one of claims 1 to 4.