JPH05241201A - Vertical driving circuit - Google Patents

Abstract

PURPOSE:To prevent the malfunction of the vertical driving circuit to be built into an active matrix type liquid crystal display device, etc. CONSTITUTION:The vertical driving circuit to be built into the active matrix type liquid crystal display device includes a shift register 1 and successively generates vertical driving pulses. At least a part of the plural transistors constituting the shift register 1, for example, a switching transistor 8, is made into an LDD structure, by which the voltage resistance of sources/drains is improved and leak currents are suppressed. This LDD structure has regions LS, LD which are adjacent to at least one region of the source region S and drain region D, are of the same conduction type as the conduction type of the source region S or drain region D and is low in impurity concn.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical drive circuit incorporated in an active matrix type liquid crystal display device or the like.
More specifically, it relates to a source / drain breakdown voltage structure of a transistor that constitutes a shift register or the like of a vertical drive circuit.

[0002]

2. Description of the Related Art To clarify the background of the present invention, FIG.
The general configuration of the active matrix type liquid crystal display device will be briefly described with reference to FIG. This type of display device has a plurality of scan electrodes X1, X2, ... Arranged in parallel with the X-axis direction.
And a plurality of signal electrodes Y1, which are arranged parallel to the Y-axis direction.
Y2, ... And. Pixel transistors T11, T12, T21, T22, ... Composed of polycrystalline silicon thin films or the like are formed at the intersections of the scanning electrodes and the signal electrodes. In addition, a liquid crystal element L corresponding to each pixel transistor
11, L12, L21, L22, ... Are provided.
The liquid crystal element includes a pixel electrode and a common electrode C which are arranged to face each other.
It is composed of a liquid crystal layer sandwiched between the OM and the OM. The drain of each pixel transistor is connected to the pixel electrode of the corresponding liquid crystal element, the source is connected to the corresponding signal electrode, and the gate is connected to the corresponding scan electrode. The plurality of scan electrodes X1, X2, ...
01 is connected. Also, a plurality of signal electrodes Y1, Y
2 are connected to the common video signal line SIG via the corresponding gate transistors S1, S2 ,. The gates of the gate transistors S1, S2, ... Are connected to the horizontal drive circuit 102.

The vertical drive circuit 101 sequentially supplies vertical drive pulses to the scan electrode group to selectively drive the pixel transistors for each row. The operating frequency of this vertical drive circuit is, for example, 16
It is about kHz. On the other hand, the horizontal drive circuit 102 sequentially supplies horizontal drive pulses to the gate transistors S1, S2, ... To extract the video signal from the signal line SIG and distribute it to the signal electrode group. The pixel transistors located in the selected row drive the liquid crystal element by sequentially sampling the video signal from the corresponding signal electrode. When the selection period has elapsed, the pixel transistor becomes non-conductive and holds the sampled video signal. In this way, real-time image display based on the video signal is performed. The operating frequency of the horizontal drive circuit is higher than that of the vertical drive circuit, which is about 3 MHz.

A shift register is generally used to sequentially output vertical drive pulse signals from the vertical drive circuit 101. A general configuration of the shift register will be briefly described with reference to FIG. The shift register 103 has a structure in which D-type flip-flops 104 are connected in multiple stages, and only the first stage and the second stage are shown in the figure. Each flip-flop 104 has a pair of inverters 105 and 106 whose output terminals are connected to each other. Each inverter is connected to the power supply line side via a P-channel type switching transistor 107 and connected to the ground line side via an N-channel type switching transistor 108. Each switching transistor performs a switching operation in response to clock pulses φ1, φ2 and their inverted clock pulses. The input terminal of the third inverter 109 is connected to the commonly connected output terminals of the pair of inverters 105 and 106. The output terminal of the third inverter 109 outputs the shift pulse of the relevant stage and is also given as an input to the D-type flip-flop of the next stage. The shift pulses P1, P2, ... Sequentially output from each stage are subjected to desired logical processing and then supplied to the scan electrode group as vertical drive pulses.

The operation of the shift register shown in FIG. 6 will be briefly described with reference to FIG. A start pulse P0 having a predetermined width is supplied to the head stage of the shift register. Further, clock pulses φ1 and φ2 having a predetermined cycle and their inversion pulses are supplied to each switching transistor connected to the pair of inverters. The clock pulses φ1 and φ2 are out of phase with each other by a half cycle, and a predetermined space period F is provided between the two pulses. Since the vertical drive circuit has a lower operating frequency than the horizontal drive circuit, the period F is relatively long.

The start pulse P0 is the first inverter 1
Switching transistors 108, 1 connected to 05
It is latched when 07 becomes conductive in response to the clock pulse φ1 and its inverted pulse. Therefore, the pair of inverters 1
The potential A1 appearing at the common output terminals of 05 and 106 is switched to the low level. The switching transistor 10 is again activated according to the next clock pulse φ1 and its inverted pulse.
This low level potential is held until 8 and 107 operate. When the next clock pulse φ1 and its inverted pulse are supplied, the leading inverter 105 is activated again.
At this time, since the start pulse P0 has already fallen, it is at the low level, and the potential A1 switches to the high level. The change in the potential A1 is taken out through the third inverter 109, and the first-stage shift pulse P1 is output.
Further, the D of the next stage which receives the input of the first output pulse P1
The type flip-flop also performs the same operation and outputs the shift pulse P2 of the relevant stage. The operation of the second-stage flip-flop is controlled by the clock pulse φ2 shifted by a half cycle and its inverted pulse. Therefore,
Shift pulses P1, P2, ...
Will be output sequentially.

[0007]

As described above, the predetermined space period F is interposed between the clock pulses φ1 and φ2. During this period, all the switching transistors are in a non-conducting state, so that the inverter pair becomes floating. At this time, there is a problem that the source / drain withstand voltage of each transistor element forming the D-type flip-flop is not sufficient and the leak current is large, so that the potential held at the common output terminal of the inverter pair fluctuates. This potential fluctuation may cause the shift register to stop operating. Particularly, unlike the horizontal drive circuit, the operating frequency of the vertical drive circuit is low and the floating period is long, so that this defect becomes remarkable.

Generally, in an active matrix type liquid crystal display device or the like, when a pixel transistor is formed of a polycrystalline silicon thin film, a transistor element included in a peripheral circuit such as a vertical drive circuit also uses the polycrystalline silicon thin film on the same substrate. Consists of In this case, since many trap levels are localized at the crystal grain boundaries in the polycrystalline silicon thin film, a considerably large amount of leak current will flow through this trap.

[0009]

In view of the above-mentioned problems or problems of the prior art, the present invention provides a transistor included in a shift register which constitutes a vertical drive circuit integrally incorporated in an active matrix type liquid crystal display device or the like. The purpose is to improve the source / drain breakdown voltage of the device and suppress the leakage current to prevent malfunction. In order to achieve such an object, a means has been taken in which at least a part of a plurality of transistors forming a shift register for sequentially generating vertical drive pulse signals has a so-called LDD structure. This LDD structure has a region adjacent to at least one of a source region and a drain region of a transistor and having the same conductivity type as the source region or the drain region and a low impurity concentration.

Such a structure is applicable to, for example, an active matrix type liquid crystal display device. This liquid crystal display device includes a plurality of scanning electrodes arranged in parallel in the X-axis direction, a plurality of signal electrodes arranged in parallel in the Y-axis direction, a vertical drive circuit connected to the scanning electrodes, and the signal electrodes. And a horizontal driving circuit connected to the pixel electrode, a pixel transistor arranged at the intersection of the scanning electrode and the signal electrode, and a liquid crystal element driven by the pixel transistor.
In such a liquid crystal display device, the peripheral transistors that form the vertical drive circuit and the pixel transistors that drive the liquid crystal elements are each formed of a polycrystalline semiconductor thin film. At least a part of the peripheral transistor has an LDD structure and has a low concentration region adjacent to at least one of the source / drain regions and having the same conductivity type as the source / drain regions. The pixel transistor also has an LDD structure and has a low concentration region of the same conductivity type as the source / drain region adjacent to at least one of the source / drain regions.

[0011]

In the LDD structure of the polycrystalline silicon thin film transistor, the low concentration impurity region is interposed between the source / drain high concentration impurity region and the channel region. When this region is interposed, PN in the polycrystalline silicon thin film
The width of the energy barrier of the junction is widened. Therefore, the strength of the electric field applied to the PN junction is weakened, and the leak current can be effectively suppressed. Therefore, the malfunction of the flip-flop in the floating state can be effectively prevented.

In particular, the present invention can be effectively applied to a monolithic active matrix type liquid crystal display device including peripheral circuits. In the active matrix type liquid crystal display device, the pixel transistor has an LDD structure in order to improve the point defect of the pixel and enhance the display quality. At this time, the peripheral thin film transistor included in the vertical driving circuit can also have an LDD structure by a common process.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 schematically shows a shift register that constitutes a vertical drive circuit incorporated in a monolithic active matrix type liquid crystal display device. The vertical drive shift register 1 has a configuration in which D-type flip-flops 2 are connected in multiple stages. Only one stage of D-type flip-flop is shown for the sake of clarity.
This flip-flop has a pair of inverters 3 and 4 whose output terminals are commonly connected. Each inverter has an N-channel type transistor 5 and a P-channel type transistor 6.
It consists of a series connection of. One end of each inverter is connected to the power supply line via the P-channel type switching transistor 7, and the other end is connected to the ground line side via the N-channel type switching transistor 8. The common output terminal of the inverter pair 3 and 4 is connected to the output terminal O of the stage via the third inverter 9.
It is connected to the UT. Such D-type flip-flop 2
Since it has a typical circuit structure, its operation will be easily understood.

At least a part of the transistors and the switching transistors forming the inverter has an LDD structure. Since these transistors are connected in series between the power supply line and the ground line, if at least some of the transistors have the LDD structure, the leak current can be effectively suppressed. Of course, all transistors are L
It may be a DD structure. In the figure, the N-channel switching transistor 8 is taken out and its LDD structure is schematically shown. This switching transistor 8
Are integrally formed on the insulating substrate 10. This insulating substrate 10 is used as a driving substrate for an active matrix type liquid crystal display device. The transistor 8 has a laminated structure and is formed by using a polycrystalline silicon thin film 11 which is patterned in a predetermined shape.
A gate electrode G is formed on the polycrystalline silicon thin film 11 via a gate insulating film 12 made of silicon dioxide or the like. The transistor 8 including the gate electrode G is P
It is covered with an interlayer insulating film 13 made of SG or the like.
Contact holes are formed in the interlayer insulating film 13 and are connected to the wiring 14 made of a metal film or the like.

In the polycrystalline silicon thin film 11, the source region S
Also, a drain region D and a channel region C interposed between both regions are formed. In the case of an N-channel thin film transistor, impurities such as phosphorus are ion-implanted at a high concentration to form the source region S and the drain region D. In addition, according to the present invention, the low-concentration impurity region LS is provided between the high-concentration impurity region S and the channel region C, and the low-concentration impurity region is also provided between the high-concentration impurity region D and the channel region C. LD is provided. These regions LS and LD are similarly obtained by ion-implanting impurities such as phosphorus at a relatively low concentration.

The provision of such low-concentration impurity regions LS and LD widens the energy barrier width of the PN junction in the polycrystalline silicon thin film 11. Therefore, the electric field strength applied to the PN junction is weakened, and the leak current can be suppressed. Equivalently, the low-concentration impurity region has a predetermined electric resistance (hereinafter referred to as LDD resistance), and the leak current between the source / drain can be reduced. In addition, the source /
Since the voltage between the drains is apparently divided by the LDD resistance, the effective breakdown voltage can be increased. Therefore, it is possible to eliminate the cause that has conventionally caused a malfunction of the vertical drive circuit, so that an operation margin can be secured and reliability is improved.

FIG. 2 is a schematic plan view showing the structure of an active matrix type liquid crystal display device. This display device is monolithic, and a display unit 15, a vertical drive circuit 16, and a horizontal drive circuit 17 are integrally formed on the same substrate. The vertical drive circuit 16 has an internal structure shown in FIG.
The shift register 1 described in 1. is included. Display 1
Reference numeral 5 is composed of a plurality of pixels arranged in a matrix. Only one pixel portion is shown for the sake of clarity. X
The pixel transistor 20 is provided at the intersection of the scanning electrode 18 extending in the Y direction and the signal electrode 19 extending in the Y direction. A pixel electrode 21 is connected to the drain region D of the transistor 20 via a contact hole H. A liquid crystal element is constituted by the pixel electrode 21 and a common electrode (not shown) arranged so as to face it. A signal electrode 19 is connected to the source region S of the pixel transistor 20 via a contact hole H. The gate electrode G is formed integrally with the scan electrode 18. A low-concentration impurity region LD is provided between the channel region directly below the gate electrode G and the drain region D. Similarly, a low-concentration impurity region LS is provided between the channel region and the source region S as well.

The pixel transistor 20 is a thin film transistor made of polycrystalline silicon. Also, in order to obtain a large drive current, an N channel type is adopted. By adopting the LDD structure, the leak current can be suppressed and the video signal charge retention characteristic for the pixel electrode 21 is improved.

The horizontal drive circuit 17 is connected to each signal electrode 19 of the display section 15 and sequentially distributes video signals. On the other hand, the vertical drive circuit 16 is connected to each scan electrode 18 of the display unit 15, and sequentially supplies a vertical drive pulse to selectively drive the pixel transistors 20 for each row. Such operation is typical and will be readily understood. The vertical drive circuit 16 includes the shift register 1 shown in FIG. 1 and the like, and is composed of a large number of peripheral transistors. To facilitate understanding, the peripheral transistor N shown in FIG. 1 is used.
A channel type switching transistor 8 is exemplified.
This peripheral transistor also has an LDD structure, a low-concentration impurity region LS is provided between the source region S and the channel region immediately below the gate electrode G, and a low-concentration impurity region is also provided between the drain region D and the channel region. An impurity region LD is provided. In this example, the pixel transistor 20 and the peripheral transistor 8 have the same N-channel type, and the low-concentration impurity regions also have the same conductivity type. Therefore, the pixel transistor 20 and the peripheral transistor 8 can be formed into the LDD structure without particularly increasing the number of processes. The LDD structure can also be applied to the P-channel peripheral transistor, for example, the P-channel switching transistor. As is clear from FIG. 1, by forming the P-channel type switching transistor 7 in the LDD structure, the leakage from the power supply line side can be suppressed, so that the reliability can be further improved.

By providing the low-concentration impurity regions on both the source side and the drain side, the LDD resistance is doubly inserted, so that the transistor drive current or the on-current is reduced. Normally, the vertical drive circuit has a slow operation speed, and therefore the reduction of the on-current due to the LDD resistance does not have much influence. However, an asymmetric LDD structure may be used in order to prevent a decrease in on-current and inoperability due to deterioration of the transistor over time. An example of this is shown in FIG. Here, the low-concentration impurity region LD is provided only on the drain side of the N-channel switching transistor 8. When the switching transistor 8 is connected as the D-type flip-flop 2, the low concentration impurity region LD is arranged on the power supply line side. In the flip-flop, electric field concentration occurs on the power supply line side of the switching transistor 8 in terms of operating characteristics, which is advantageous in terms of leakage current suppression measures. In addition, in order to clearly show the above-mentioned asymmetric structure, the equivalent circuit is L
The DD resistor R is shown.

Finally, referring to FIG. 4, a flip-flop 2 incorporating a switching transistor having an asymmetric LDD structure is shown. In this example, the asymmetric LDD structure is adopted for the N-channel type switching transistor 8 and the N-channel type transistor 5 forming the inverter.
However, the present invention is not limited to this, and P
An asymmetric LDD structure may be adopted for the channel type switching transistor 7 and the P channel type inverter transistor 6. Alternatively, it may be adopted for all transistors.

[0022]

As described above, according to the present invention, in the active matrix type liquid crystal display device, the transistor constituting the shift register or the transfer part of the vertical drive circuit has the LDD structure, so that the source / drain breakdown voltage can be improved. By improving and suppressing the leak current, the operation margin and the reliability can be improved. Further, if the LDD structure is adopted only for the N-channel peripheral transistor in addition to the pixel transistor, there is an effect that an increase in the number of semiconductor processes can be avoided. In addition, it is possible to suppress the amount of leak current not only in the display section but also in the peripheral circuit section, so that there is an effect that power consumption can be reduced. Further, since the source / drain breakdown voltage is improved, the power supply voltage can be set higher than in the conventional case, so that the image quality such as display contrast can be improved. In addition, there is an effect that the reliability of the vertical drive circuit is improved.

[Brief description of drawings]

FIG. 1 is a schematic explanatory view showing a configuration of a vertical drive circuit according to the present invention.

FIG. 2 is a schematic plan view showing an example of an active matrix type liquid crystal display device incorporating a vertical drive circuit according to the present invention.

FIG. 3 is a schematic diagram showing an example of a transistor included in a vertical drive circuit according to the present invention.

FIG. 4 is a partial circuit diagram showing a configuration example of a shift register included in a vertical drive circuit.

FIG. 5 is a block diagram showing a configuration of a general active matrix type liquid crystal display device.

FIG. 6 is a circuit diagram showing a configuration of a shift register included in a conventional vertical drive circuit.

7 is a timing chart for explaining the operation of the shift register shown in FIG.

[Explanation of symbols]

 1 shift register 2 D-type flip-flop 7 switching transistor 8 switching transistor 10 insulating substrate 11 polycrystalline silicon thin film 15 display 16 vertical drive circuit 17 horizontal drive circuit 18 scan electrode 19 signal electrode 20 pixel transistor 21 pixel electrode D drain region G gate electrode S source region LD low concentration impurity region LS low concentration impurity region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location G09G 3/36 7319-5G H01L 27/12 A 8728-4M 29/784

Claims (2)

[Claims] 1. A source region, wherein at least a part of a plurality of transistors forming a shift register for sequentially generating a vertical drive pulse signal is adjacent to at least one of a source region and a drain region of the transistor. Alternatively, a vertical drive circuit having a structure having the same conductivity type as the drain region and a low impurity concentration. 2. A plurality of scan electrodes arranged parallel to the X-axis direction, a plurality of signal electrodes arranged parallel to the Y-axis direction, a vertical drive circuit connected to the scan electrodes, and the signal electrode. A horizontal drive circuit connected to the pixel electrode, and a pixel transistor arranged at the intersection of the scan electrode and the signal electrode,
In a liquid crystal display device including a liquid crystal element driven by the pixel transistor, a peripheral transistor that constitutes the vertical drive circuit and a pixel transistor that drives the liquid crystal element are each made of a polycrystalline semiconductor thin film. The portion is adjacent to at least one of the source / drain regions and has a low concentration region of the same conductivity type as the source / drain regions, and the pixel transistor is adjacent to at least one of the source / drain regions, The sauce /
A liquid crystal display device having a low concentration region having the same conductivity type as the drain region.