JPH08116063A - Thin-film transistor and liquid crystal display device - Google Patents

Abstract

PURPOSE: To prevent the concentration of an electric field in the edge parts of a source region and a drain region by providing a low-concentration impurity region having the same conductivity type as those of the source region and the drain region and lower impurity concentration than those of the source region and the drain region or an offset region in which the impurity concentration is zero. CONSTITUTION: A channel region 11a is formed in the part of a polycrystalline silicon thin film 11 right under a gate electrode 13. Next, high-concentration impurity regions 11b, 11b are formed as a source and a drain regions in the part of the polycrystalline silicon thin film on both sides of the channel region 11a. Further, a low-concentration impurity region 11c which has the same conductivity type as that of the high-concentration impurity region 11b and lower impurity concentration than that of the high-concentration impurity region 11b are provided in the vicinity of the boundary part between the channel region 11a and the high-concentration impurity region 11b. Thereby, the electric field concentration of the edge parts of the source and the drain regions can be prevented, thereby being able to obtain a high withstand voltage between the source and the drain.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT) and a liquid crystal display device using this thin film transistor.

[0002]

2. Description of the Related Art The structure of a conventional TFT is shown in a vertical sectional view of FIG. 8 and a plan view of FIG.

When manufacturing a TFT, first, the insulating substrate 5 is used.
A polycrystalline silicon thin film 51 is formed on 0. then,
A gate insulating film 52 is formed on the polycrystalline silicon thin film 51, and a gate electrode 53 is formed. After that, predetermined ions are implanted from above the gate electrode 53. If an NMOS (N-channel metal-oxide-semiconductor) transistor is to be manufactured, for example, P ⁺ is implanted as ions,
If a PMOS (P-channel type metal-oxide-semiconductor) transistor is to be manufactured, for example, B ⁺ is implanted. As a result, the channel region 51a is formed in the portion of the polycrystalline silicon thin film 51 immediately below the gate electrode 53, and at the same time, the source region is formed on both sides of the channel region 51a.
High concentration impurity regions 51b and 51b as drain regions
Is formed.

Then, an interlayer insulating film 54 is formed, contact holes 55, 55 are formed, and the contact hole 5 is formed.
The source electrode 56 and the drain electrode 57 are obtained by filling 5/55 with a low-resistance metal. Since the TFT having such a structure has a large on-current, it is used in a peripheral drive circuit of a driver-integrated liquid crystal display device.

[0005]

However, in the above-mentioned conventional structure, the on-current is large, but the withstand voltage of the TFT is small. Therefore, when the TFT is used in the peripheral circuit of the driver-integrated liquid crystal display device, There is a problem that the peripheral circuits cannot operate normally.

Therefore, in the liquid crystal display device disclosed in Japanese Patent Publication No. 3-38755, the TFT is LDD (Lightly
High breakdown voltage is achieved by adopting the Doped Drain structure. However, when these structures are adopted, the on-current becomes small. Therefore, when a peripheral drive circuit is configured using this TFT, it becomes difficult to secure an operating frequency of 2 MHz or higher, which causes a new problem that high-quality image display cannot be supported.

[0007]

In order to solve the above problems, a thin film transistor according to the invention of claim 1 is formed with an active layer formed on an insulating substrate or an insulating layer and an active layer. A gate insulating film, a gate electrode formed on the gate insulating film, a channel region formed in a portion of the active layer located directly below the gate electrode, and an active layer portion located on both sides of the channel region. In a thin film transistor having a formed source region and drain region, in the portion of the active layer located near the boundary between the channel region and the source region or drain region, and near the edge of the source region or drain region. ,
A low-concentration impurity region having the same conductivity type as that of the source region and the drain region and having a lower impurity concentration than the source region and the drain region, or an offset region having an impurity concentration of zero is provided.

In order to solve the above problems, a thin film transistor according to a second aspect of the present invention is the thin film transistor according to the first aspect, in which the gate electrode portion located immediately above both ends in the width direction of the channel region is provided. It is characterized in that the gate length is set to be shorter than the gate length of the gate electrode portion located immediately above the central portion of the channel region.

In order to solve the above problems, the thin film transistor according to the invention of claim 3 is the thin film transistor of claim 1 or 2, wherein the size of the impurity region or the offset region is 2 μm □ or less. It is characterized by that.

In order to solve the above problems, a thin film transistor according to a fourth aspect of the present invention includes an active layer formed on an insulating substrate or an insulating layer, and a gate insulating film formed on the active layer. A gate electrode formed on the gate insulating film, a channel region formed in a portion of the active layer located directly below the gate electrode, and a source region formed in a portion of the active layer located on both sides of the channel region, In a thin film transistor having a drain region, the gate length of the gate electrode portion located directly above both ends in the width direction of the channel region is larger than the gate length of the gate electrode portion located directly above the central portion of the channel region. The feature is that it is set to be long.

In order to solve the above problems, a thin film transistor according to a fifth aspect of the present invention is the thin film transistor according to the fourth aspect, wherein the difference between the gate lengths is set to 4 μm or less. I am trying.

In order to solve the above problems, a liquid crystal display device according to a sixth aspect of the present invention is a liquid crystal display integrated with a driver, which includes a liquid crystal display portion on a substrate and a driver for driving the liquid crystal display portion. In the device, the driver comprises the thin film transistor according to claim 1, 2, 3, 4 or 5.

[0013]

According to the structure of claim 1, in the vicinity of the boundary between the channel region and the source region or the drain region, and
In the portion of the active layer located near the edge of the source region or the drain region, a low concentration impurity region having the same conductivity type as the source region and the drain region and a lower impurity concentration than the source region and the drain region, or the impurity concentration Since the zero offset region is provided, electric field concentration at the edge portion of the source region or the drain region is prevented. As a result, a high breakdown voltage between the source and drain can be obtained. Moreover, it is possible to obtain a high on-current similar to that of a conventional single-gate thin film transistor.

According to the second aspect of the invention, the gate length of the gate electrode portion located directly above both ends in the width direction of the channel region is equal to the gate length of the gate electrode portion located directly above the central portion of the channel region. Since the length is set shorter than that of the first embodiment, the thin film transistor can be downsized in addition to the effect of the first aspect.

According to the structure of claim 3, the size of the impurity region or the offset region is set to 2 μm □ or less. Therefore, in addition to the operation of claim 1 or 2, the thin film transistor of the conventional single gate structure is almost the same. The on-current can be secured.

According to the structure of claim 4, the gate length of the gate electrode portion located directly above both ends of the channel region in the width direction is equal to the gate length of the gate electrode portion located directly above the central portion of the channel region. Since the length is set longer than that of the source region, electric field concentration is prevented at the edge portion of the source region or the drain region. As a result, a high breakdown voltage between the source and drain can be obtained. Moreover, it is possible to obtain a high on-current similar to that of a conventional single-gate thin film transistor.

According to the structure of claim 5, the difference between the gate lengths is set to 4 μm or less. Therefore, in addition to the effect of claim 4, an ON current substantially equal to that of a conventional single-gate thin film transistor is secured. it can.

According to the structure of claim 6, since the driver comprises the thin film transistor according to claim 1, 2, 3, 4 or 5, the driver integrated liquid crystal display device can be normally operated. Moreover, since the operating frequency can be increased, it is possible to display a high quality image. Furthermore, since the area occupied by the thin film transistors can be reduced, the liquid crystal display device can be downsized.

[0019]

The first embodiment of the present invention will be described below with reference to FIGS.

The structure of the TFT of this embodiment is shown in FIGS.
Shown in 2 is a plan view, and FIG. 1 is AA ′ of FIG.
FIG. As shown in these figures, the TFT of this embodiment has an insulating substrate 10 such as a glass substrate or a quartz substrate.
It has a structure in which a polycrystalline silicon thin film 11 as an active layer, a gate insulating film 12, a gate electrode 13, and an interlayer insulating film 14 are laminated on top. A channel region 11a is formed in a portion of the polycrystalline silicon thin film 11 directly below the gate electrode 13, and a high concentration impurity region 11b as a source region and a drain region is formed in a portion of the polycrystalline silicon thin film 11 on both sides of the channel region 11a. 11b is formed.

Furthermore, in the TFT of this embodiment, the polycrystalline silicon thin film 11 is located near the boundary between the channel region 11a and the high-concentration impurity region 11b and near the edge of the high-concentration impurity region 11b. , The high-concentration impurity region 11b, which has the same conductivity type as the high-concentration impurity region 11b,
A low-concentration impurity region 11c having a lower impurity concentration than that is provided.

In manufacturing the above TFT, first, the polycrystalline silicon thin film 11 is formed on the insulating substrate 10. Then, the gate insulating film 12 is formed on the polycrystalline silicon thin film 11.
Then, the gate electrode 13 is formed. After that, as a first ion implantation step, predetermined ions are implanted from above the gate electrode 13 at a predetermined concentration using the gate electrode 13 as a mask. As a result, the channel region 11a is formed in the portion of the polycrystalline silicon thin film 11 immediately below the gate electrode 13. At this time, the region other than the channel region 11a in the polycrystalline silicon thin film 11 becomes a low concentration impurity region.

Further, a resist pattern is formed so as to cover the portion of the polycrystalline silicon thin film 11 where the low concentration impurity region 11c is to be formed. Then, as a second ion implantation step, the same ions as the above are implanted at a higher concentration than the above using this resist pattern as a mask.
As a result, the low-concentration impurity regions 11c ... Are formed in the square of the channel region 11a, and at the same time, the high-concentration impurity regions 11b and 11b are formed on both sides of the channel region 11a.

Then, the interlayer insulating film 14 is formed, the contact holes 15 are formed, and the contact hole 1 is formed.
The source electrode 16 and the drain electrode 17 are obtained by filling 5 and 15 with a low resistance metal.

FIG. 3 is a graph in which the source-drain breakdown voltage (BVdss) in the TFT of this embodiment is plotted against the channel length. Here, the source-drain breakdown voltage is defined as the source-drain voltage at which the source-drain current becomes 1 μA when the gate voltage is set to 0V.

[0026] Curve 1 in Figure 3, the P ⁺ in the first ion implantation process described above was injected at a concentration of 10 ¹³ cm ^-2, the concentration of P ⁺ a 10 ¹⁵ cm ^-2 in the second ion implantation step The characteristics of the TFT manufactured by injecting are shown. The channel width was 20 μm, and the size of the low concentration impurity region 11c was ΔX = ΔY = 2 μm. Here, ΔX is the length of one side measured along the channel direction, and ΔY is
It is the length of one side measured along the channel width direction.

For comparison, a curve 3 obtained with a conventional TFT having a single gate structure and a curve 4 obtained with a TFT having an LDD structure are also shown.

As is apparent from the figure, the TFT of this embodiment
Then, similarly to the LDD structure TFT, a higher source-drain breakdown voltage was obtained as compared with the conventional single gate structure TFT.

This is the low-concentration impurity region 1 at the boundary between the channel region 11a and the high-concentration impurity region 11b and at the portion corresponding to the edge of the high-concentration impurity region 11b.
Due to the provision of 1c. That is, by providing the low concentration impurity region 11c, electric field concentration at the edge portion of the high concentration impurity region 11b is prevented. As a result, a high breakdown voltage between the source and drain can be obtained.

Next, 10 V was applied between the source and drain, and the ON current was measured when the gate voltage was 15 V. As a result, in the TFT of this example, a higher on-current was obtained as compared with the TFT of the LDD structure, similarly to the TFT of the single gate structure.

As described above, according to the TFT of this embodiment, the same high source-drain breakdown voltage as that of the LDD structure TFT can be obtained, and further, the single gate structure TFT.
Similarly, a high on-current can be obtained.

The size of the low concentration impurity region 11c is
That is, ΔX and ΔY need only be 1 μm,
In order to secure a high on-current, it is desirable to set ΔY ≦ 2 μm.

Further, in this embodiment, the low concentration impurity regions 15c are provided at four locations around the channel region 11a, but the same result can be obtained even if the low concentration impurity regions 11c are replaced with offset regions which are non-doped regions. Was obtained. The low concentration impurity region 11c or the offset region is
It is not always necessary to provide it at four locations, and it was effective even if it was provided at two locations.

Since the low-concentration impurity region 11c or the offset region is provided, when high-concentration ion implantation is performed in the second ion-implanting step, at the boundary between the channel region 11a and the high-concentration impurity region 11b, In addition, discharge breakdown is less likely to occur in the portion corresponding to the edge portion of the high concentration impurity region 11b. This improves the yield of the TFT.

Further, in the TFT of this embodiment, since the breakdown voltage can be increased by providing the low concentration impurity region 11c, the gate electrode 13 can be made shorter than before. As a result, the area of the TFT can be made smaller than before.

Further, as shown in FIG. 4, the gate electrode 1 located immediately above both ends in the width direction of the channel region 11a.
The gate length of the portion 3 (the length of the gate electrode 13 measured along the channel direction) is set to be shorter than the gate length of the portion of the gate electrode 13 located directly above the central portion of the channel region 11a. However, the low-concentration impurity region 11c may be provided in the portion where the gate electrode 13 is shortened.

An inverter and a clock-to-inverter were constituted by the TFT of this example, a shift register was produced by these, and the maximum operating frequency was measured. For n-type TFTs, set channel width / channel length = 20/7, and for p-type TFTs,
The channel width / channel length was set to 20/5.

As a result, in the shift register using the TFT of this embodiment, the maximum operating frequency of 7 MHz was obtained as in the shift register using the single gate structure TFT.

The second embodiment of the present invention will be described below with reference to FIGS. 5 and 6. In addition,
For convenience of explanation, members having the same functions as the members shown in the drawings of the above-described embodiment are designated by the same reference numerals, and the description thereof will be omitted.

The structure of the TFT of this embodiment is shown in FIGS.
Shown in FIG. 6 is a plan view, and FIG. 5 shows AA ′ of FIG.
FIG. In the TFT of this embodiment, the structure of the polycrystalline silicon thin film 11 and the shape of the gate electrode 13 are different from those of the above embodiment.

In the polycrystalline silicon thin film 11, a channel region 11a is formed immediately below the gate electrode 13, and the polycrystalline silicon thin film 11 on both sides of the channel region 11a has high concentration impurities as a source region and a drain region. Regions 11b and 11b are formed. The channel region 11a is formed such that the channel length at both ends is longer than the channel length at the central part.

In the case of manufacturing the above-mentioned TFT, the gate electrode 13 (gate electrode 13 having rectangular protrusions 13a at both ends) having a long gate length at both ends with respect to the gate length at the center is polycrystalline. After being formed on the silicon thin film 11, predetermined ions are implanted at a predetermined concentration from above the gate electrode 13 using the gate electrode 13 as a mask. As a result, the polycrystalline silicon thin film 11 immediately below the gate electrode 13 is formed.
At the same time as the above-mentioned channel region 11a is formed in the portion, the high-concentration impurity regions 11b and 11b are formed.

For the TFT of this embodiment, the source-drain breakdown voltage was measured in the same manner as in the above embodiment. The results are also shown in FIG. 3 of the above embodiment.

Curve 2 is a T produced by implanting P ⁺ at a concentration of 10 ¹⁵ cm ^{-2 in} the above ion implantation process.
The characteristic of FT is shown. The size of the rectangular protrusions 13a on both ends of the gate electrode 13 was ΔX = ΔY = 2 μm. Here, ΔX is the length of one side measured along the channel direction, and ΔY is the length of one side measured along the channel width direction.

As is apparent from the figure, the TFT of this embodiment
Then, similarly to the LDD structure TFT, a higher source-drain breakdown voltage was obtained as compared with the conventional single gate structure TFT.

The size of the rectangular protrusions on both ends of the gate electrode 13, that is, ΔX and ΔY is sufficient to be 1 μm, and ΔY ≦ 2 in order to secure a high on-current.
It is desirable to set to μm.

An inverter and a clock-to-inverter were constituted by the TFT of this example, and a shift register was produced by these, and the maximum operating frequency was measured in the same manner as in the above example. For n-type TFT, set channel width / channel length = 20/7,
In p-type TFT, channel width / channel length =
It was set to 20/5.

As a result, in the shift register using the TFT of this embodiment, a maximum operating frequency of 5 MHz was obtained, which is almost the same as the shift register using the single gate structure TFT.

Next, as an application example of the TFT shown in the first and second embodiments, a liquid crystal display device integrated with a driver will be cited and explained with reference to FIG.

In the driver integrated liquid crystal display device, a gate drive circuit 22, a source drive circuit 23, and a TFT array section 24 are formed on a substrate 21 made of glass or quartz. The TFT array section 24 includes a number of parallel gate bus lines 22 extending from the gate drive circuit 22.
a ... is arranged. From the source drive circuit 23, a large number of source bus lines 23a ... Are arranged orthogonally to the gate bus lines 22a. Then, the gate bus wiring 22a,
A TFT 25, a pixel 26, and an additional capacitor 27 are provided in a rectangular area surrounded by the source bus line 23a and the additional capacitor common line 28. The gate electrode of the TFT 25 is connected to the gate bus line 22a, and the source electrode is connected to the source bus line 23a. The drain electrode of the TFT 25 is connected to one electrode of the pixel 26,
A liquid crystal is sealed between the other electrode of the picture element 26 arranged on the substrate 21 and the counter electrode to form the picture element 26.
Further, the additional capacitance common wiring 28 is connected to an electrode having the same potential as the counter electrode of the picture element 26.

In the above structure, a data signal having an amplitude of about 10 V is applied from the source drive circuit 23 to the picture element electrode through the TFT 25 provided for each picture element 26. Therefore, the gate electrode of the TFT 25 is connected to the gate drive circuit 2
A gate pulse signal of 2 to 15 V or higher is applied.

Therefore, the power supply voltage of the peripheral drive circuits such as the gate drive circuit 22 and the source drive circuit 23 is 15 V or higher. When an inverter or a clock-to-inverter is composed of NMOS and PMOS TFTs, a voltage of about 15V may be applied between the source and drain of the TFT which constitutes the inverter. Therefore, in order for the inverter to operate normally, the
The breakdown voltage between drains must be at least 15V or higher.

The TFTs of the first and second embodiments have a source-drain breakdown voltage that sufficiently satisfies this condition. In addition, since the TFT of the above-described embodiment can have a high breakdown voltage without increasing the gate length, not only can the area of the peripheral drive circuit be reduced, but also T
The area of the liquid crystal cell including the FT 25, the picture element 26, and the additional capacitor 27 can also be reduced.

Further, in the TFT of the above embodiment, the gate length can be shortened by providing the low concentration impurity region 11c, so that the area of the liquid crystal cell and the area of the peripheral drive circuit can be further reduced. .

When a protection circuit is provided in the signal input section to protect the peripheral drive circuit from external electrostatic stress,
Although it is necessary to pass a sufficient current as a countermeasure against static electricity in the protection circuit, the TFTs of the first and second embodiments can pass an on-current that sufficiently clears this condition.

Furthermore, HDTV (high quality television)
When displaying a high-quality image such as, it is necessary to increase the operating frequency of the peripheral drive circuit, but the TFTs of the first and second embodiments can provide an operating frequency that sufficiently clears this condition.

[0057]

As described above, the thin film transistor according to the first aspect of the present invention is located near the boundary between the channel region and the source or drain region and near the edge of the source or drain region. A low-concentration impurity region having the same conductivity type as the source region and the drain region and a lower impurity concentration than the source region and the drain region, or an offset region having an impurity concentration of zero is provided in the active layer portion. .

According to this, electric field concentration is prevented at the edge portion of the source region or the drain region. As a result, a high breakdown voltage between the source and drain can be obtained. Moreover,
Similar to a conventional thin film transistor having a single-gate structure, a high on-current can be obtained.

As described above, the thin film transistor according to the invention of claim 2 is the thin film transistor according to claim 1, wherein the gate length of the gate electrode portion located immediately above both ends in the width direction of the channel region is: The gate length is set to be shorter than the gate length of the gate electrode portion located directly above the central portion of the channel region.

According to this, in addition to the effect of the first aspect, there is an effect that the thin film transistor can be downsized.

As described above, the thin film transistor according to the invention of claim 3 is the thin film transistor according to claim 1 or 2, wherein the size of the impurity region or the offset region is 2 μm □ or less.

According to this, in addition to the effect of the first or second aspect, there is an effect that an ON current substantially equal to that of the conventional single-gate structure thin film transistor can be secured.

As described above, in the thin film transistor according to the fourth aspect of the present invention, the gate length of the gate electrode portion located directly above both ends in the width direction of the channel region is located directly above the central portion of the channel region. The gate length is set longer than the gate length of the gate electrode portion.

According to this, electric field concentration is prevented at the edge portion of the source region or the drain region. As a result, a high breakdown voltage between the source and drain can be obtained. Moreover,
Similar to a conventional thin film transistor having a single-gate structure, a high on-current can be obtained.

As described above, the thin film transistor according to the invention of claim 5 is the thin film transistor of claim 4, wherein the difference between the gate lengths is set to 4 μm or less.

According to this, in addition to the effect of the fourth aspect, there is an effect that an ON current substantially equal to that of the conventional single-gate structure thin film transistor can be secured.

A liquid crystal display device according to a sixth aspect of the present invention is a driver-integrated liquid crystal display device comprising a liquid crystal display unit and a driver for driving the liquid crystal display unit on the substrate as described above. Claims 1, 2, 3, 4
Alternatively, the thin film transistor described in 5 is included.

According to this, the driver integrated liquid crystal display device can be operated normally. Moreover, since the operating frequency can be increased, it is possible to display a high quality image. Further, since the area occupied by the thin film transistor can be reduced, the liquid crystal display device can be downsized. In particular, when the above-mentioned thin film transistor is used for a protection circuit of a signal input section of a liquid crystal display device, a great effect is exhibited due to its characteristics.

[Brief description of drawings]

FIG. 1 shows a first embodiment of the present invention and is a vertical cross-sectional view showing the structure of a thin film transistor.

FIG. 2 is a plan view of the thin film transistor of FIG.

FIG. 3 is a graph in which the source-drain breakdown voltage of a thin film transistor is plotted against the channel length.

FIG. 4 is a plan view showing a configuration of a thin film transistor.

FIG. 5 shows a second embodiment of the present invention and is a vertical cross-sectional view showing the structure of a thin film transistor.

FIG. 6 is a plan view of the thin film transistor of FIG.

FIG. 7 is a configuration diagram showing an outline of a liquid crystal display device using a thin film transistor.

FIG. 8 is a vertical cross-sectional view showing the structure of a conventional thin film transistor.

9 is a plan view of the thin film transistor of FIG.

[Explanation of symbols]

10 substrate 11 polycrystalline silicon thin film (active layer) 11a channel region 11b high concentration impurity region (source region, drain region) 11c low concentration impurity region 12 gate insulating film 13 gate electrode 13a protrusion 25 thin film transistor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location 9056-4M H01L 29/78 617 A

Claims (6)

[Claims] 1. An active layer formed on an insulating substrate or an insulating layer, a gate insulating film formed on the active layer, a gate electrode formed on the gate insulating film, and a position directly below the gate electrode. In a thin film transistor having a channel region formed in a portion of an active layer and a source region and a drain region formed in portions of the active layer located on both sides of the channel region, a channel region and a source region or a drain region are formed. In the portion of the active layer located near the boundary between the source region and the drain region and near the edge of the source region or the drain region, the conductivity type is the same as that of the source region and the drain region, and the impurity concentration is lower than that of the source region and the drain region. Concentration impurity region,
Alternatively, a thin film transistor having an offset region having an impurity concentration of zero is provided. 2. The gate length of a gate electrode portion located directly above both ends of the channel region in the width direction is set to be shorter than the gate length of a gate electrode portion located directly above the central portion of the channel region. The thin film transistor according to claim 1, wherein the thin film transistor is provided. 3. The thin film transistor according to claim 1, wherein the impurity region or the offset region has a size of 2 μm □ or less. 4. An active layer formed on an insulating substrate or an insulating layer, a gate insulating film formed on the active layer, a gate electrode formed on the gate insulating film, and a position directly below the gate electrode. In a thin film transistor having a channel region formed in a portion of the active layer, and a source region and a drain region formed in portions of the active layer located on both sides of the channel region, both ends of the channel region in the width direction are formed. The thin film transistor, wherein the gate length of the gate electrode portion located directly above the gate electrode portion is set to be longer than the gate length of the gate electrode portion located directly above the central portion of the channel region. 5. The thin film transistor according to claim 4, wherein the difference between the gate lengths is set to 4 μm or less. 6. A driver integrated liquid crystal display device comprising a liquid crystal display unit and a driver for driving the liquid crystal display unit on a substrate, wherein the driver is a thin film according to claim 1, 2, 3, 4 or 5. A liquid crystal display device comprising a transistor.