JPH04211156A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a MOS integrated circuit having high-breakdown MOS transistors connected to external terminals by using a structure in which these transistors have a different impurity concentration in their diffused regions from that in the diffused regions for internal MOS transistors. CONSTITUTION:A semiconductor substrate 10 includes a MOS transistor 11 connected directly or through a resistor to an external terminal 1 and a MOS transistor 12 (internal transistor) that is not directly connected to the external terminal. The lightly-doped diffused layer LDDN-extending from the heavily-doped diffused layer of the transistor 11 has a different impurity concentration from that of the lightly-doped diffused layer LDDN-of the internal transistor 12, so as to increase breakdown voltage. To maintain the reliability of transistors, the channel length L1 of the transistor 11 may be made longer than the channel length L2 of the transistor 12.

Description

[Detailed description of the invention]

[00011

[Field of Industrial Application] The present invention relates to a semiconductor device provided with a protection device against static electricity applied to external terminals such as input terminals, output terminals, or input/output terminals. [0002] Electrostatic discharge causes characteristic deterioration, junction breakdown, oxide film breakdown, etc., so preventing electrostatic breakdown is important throughout the manufacturing, assembly, and use of semiconductor devices. Particularly in the current situation where semiconductor devices such as ICs and LSIs are becoming increasingly finer as they become more dense and highly integrated, even the slightest electrostatic discharge can cause a failure. Especially M
Since an OS type semiconductor device is an integrated field effect transistor (FET) having an insulated gate electrode, it is particularly vulnerable to electrostatic discharge damage. This tendency is particularly strong in logic circuits such as CMOSIC. Conventionally, a static electricity protection circuit has been used as a protection circuit for static electricity applied to external terminals connected to the outside of a MOS semiconductor integrated circuit device, that is, input terminals, output terminals, input/output terminals (hereinafter referred to as I10 terminals), etc. Many protection elements are used that operate bipolarly during discharge. This type of semiconductor device is disclosed in Japanese Patent Application Laid-Open No. 61-2175.
No. 77, USP 4,734,752. [0003] FIG. 14 shows a cross-sectional view of a conventional silicon semiconductor substrate on which a protection element and a MOS semiconductor integrated circuit constituting a protection circuit against static electricity are mounted. As shown in this figure, in conventional MOS semiconductor integrated circuits, LDD (Lightly Doped D
A rain-source structure is often adopted. In a device with a MOS structure, when the channel length becomes as short as about 1.2 μm, problems arise such as the generation of hot carriers and a decrease in breakdown voltage, but this structure can prevent these problems. The semiconductor substrate 10 includes
A plurality of N-channel MOS transistors are formed, and as shown in the figure, they have an LDD structure, and the drains 1, which are high concentration diffusion layers of these transistors 7 and 8, are formed.
4. The source 15 is a low concentration diffusion layer LDDN −
It is equipped with The transistor 7 is a protection element, and is a MOS transistor directly connected to an external terminal whose drain region 14 is connected to the external terminal (I10 terminal) 1. Further, the transistor 8 is a MOS transistor (hereinafter referred to as an internal transistor) whose diffusion layer such as the train region 14 is not directly connected to the I10 terminal 1, that is, not directly connected to an external terminal. Internal transistors are used, for example, as elements constituting integrated circuits such as inverters. The impurity concentration (dose amount) of this low concentration diffusion layer LDDN - can take an appropriate value as required, but currently it is 1018 to 1019
/cm3. Note that here, a MOS transistor in which an external terminal is directly connected to a diffusion layer such as a source or drain region is referred to as a MOS transistor that is directly connected to an external terminal, but a resistor is interposed between the external terminal and the diffusion layer. Things are also included in this category. [0004] Conventionally, low concentration diffusion layers of a plurality of MOS transistors formed on one semiconductor substrate usually have the same impurity concentration. Of course, for example, if a high voltage circuit is included in the same semiconductor substrate, the impurity concentration of the low concentration diffusion layer of the MOS transistor included in that circuit will be the same as the impurity concentration of the low concentration diffusion layer of the MOS transistor in another region. There are exceptional cases where the concentration differs. However, if the impurity concentrations of the low-concentration diffusion layers of multiple MOS transistors on the same semiconductor substrate are made to differ from each other, ion implantation to form the diffusion layers must be performed differently depending on the difference in impurity concentration. It is also necessary to increase the number of masks for the low concentration diffusion layer, and the benefits of varying the impurity concentration of the low concentration diffusion layer are not particularly recognized, so the impurity concentration is usually kept the same as described above. [0005] FIG. 10 shows the substrate current (Isu
FIG. 3B is a characteristic diagram showing the relationship between the impurity concentration (QLDDN) of the low concentration diffusion layer of the MOS transistor formed on this substrate. The vertical axis represents the substrate current (A), and the horizontal axis represents the impurity concentration (70 m3) of the low concentration diffusion layer. In this figure, curve L2 is an example of this conventional technique. L2 is M
It also shows the channel length of the transistor (OS), and it can be seen that the relationship between substrate current and impurity concentration depends on this channel length. A typical example of carriers that become hot in a channel flying out of the channel without being confined therein is substrate current, and this generation indicates characteristic deterioration. Therefore, it is better for such substrate current to be as small as possible. The impurity concentration of the low concentration diffusion layer LDDN- of the N-channel MOS transistor shown in FIG. 14 is set to a value (Q2) that minimizes the substrate current in view of the reliability of the semiconductor device and the requirements for the power supply voltage. As mentioned above, this value is the current value 1018
~1019/cm". The curve L1 is
Set the channel length of the MOS transistor to Ll, which is longer than L2.
This is a curve showing the substrate current vs. impurity concentration characteristics when . The reliability level of transistors (MOS) is affected by various phenomena such as shifts in VTH due to the generation of hot carriers and deterioration in GM.
Devices, p. 38.14-5, published by Baifukan," it is possible to evaluate it in a first-order approximation using the substrate current Isub. Reliability is impurity concentration QLDDN
- and the channel length, and the impurity concentration Q
Although reliability decreases when LDDN- is increased or decreased, sufficient reliability can be ensured by increasing the channel length. Therefore, it can be seen that the longer the channel length, the smaller the minimum value of the substrate current, as shown in the figure. However, MOS transistors used in low voltage circuits such as watches and calculators, for example, are not affected by hot carriers so much and are therefore not so affected by substrate current-impurity concentration characteristics. [0006] Furthermore, the channel length of the conventional MOS transistor is set to a length that can be processed using microtechnology, and the channel lengths of transistors 7 and 8 shown in FIG. 14 are both the same. The longer the channel length, the higher the reliability, but as mentioned above, with the strong demand for miniaturization of semiconductor devices, it is unthinkable to lengthen the channel, and in fact, the trend is to shorten it, which reduces reliability. There was a possibility of damage. [0007]

As described above, as semiconductor devices become smaller, their channel lengths become shorter and their resistance to electrostatic damage becomes smaller. Therefore, a MOS transistor directly connected to an external terminal constituting a protection circuit or the like cannot obtain sufficient electrostatic withstand voltage. Therefore, conventionally, the channel width (W) of a MOS transistor directly connected to an external terminal has been increased in order to increase the electrostatic withstand voltage. but,
In order to effectively increase the breakdown voltage, for example, the channel length (
When L) is 1.2 μm, the channel width W is usually 400 μm.
Although it is about μm, it is necessary to increase it to about 800 to 1200 μm. Since this method cannot cope with the trend toward miniaturization of semiconductor devices, this method cannot be said to be an effective means for increasing the breakdown voltage. [0008] The present invention solves the problems of the conventional semiconductor device described above, and provides a semiconductor device that can obtain sufficient electrostatic withstand voltage and ensure reliability equivalent to that of the conventional semiconductor device. This is what I am trying to do. [0009]

[Means for Solving the Problems] A semiconductor device of the present invention includes:
A semiconductor substrate has an external terminal, a low concentration diffusion layer with a low impurity concentration, and a high concentration diffusion layer continuously in contact with the low concentration diffusion layer, and the high concentration diffusion layer is directly connected to the external terminal. an insulated gate field effect transistor; an insulated gate field effect transistor comprising a low concentration diffusion layer and a high concentration diffusion layer continuously in contact with the low concentration diffusion layer, the high concentration diffusion layer not being directly connected to the external terminal; and an insulated gate field effect transistor in which the impurity concentration of the low concentration diffusion layer of the insulated gate field effect transistor that is directly connected to at least some of the external terminals is not directly connected to at least some of the external terminals. The impurity concentration is different from the impurity concentration of the low concentration diffusion layer of the transistor. The low concentration diffusion layer is a diffusion layer having an LDD structure or a double diffusion structure. The impurity concentration of the low concentration diffusion layer of the transistor directly connected to the external terminal is made higher than the impurity concentration of the low concentration diffusion layer of the transistor not directly connected to the external terminal, for example, the impurity concentration of the low concentration diffusion layer of the transistor not directly connected to the external terminal. When the impurity concentration of the low concentration diffusion layer of the transistor is 1018 to 1019/Cm3, the impurity concentration of the low concentration diffusion layer of the transistor directly connected to the external terminal is 3×1019 to 3×
1020/Cm3. When increasing the impurity concentration, the channel length of the transistor directly connected to the external terminal is made longer than the channel length of the transistor not directly connected to the external terminal. For example, the channel length of the transistor not directly connected to the external terminal is 1.2 μm.
In this case, the channel length of the transistor directly connected to the external terminal is 1.9 μm or more.
μm, the channel length of the transistor directly connected to the external terminal is 1.5 μm or more, and in the case of 0.8 μm, the channel length of the transistor directly connected to the external terminal is 1.5 μm or more. .2μm
That's all. It is also possible to make the impurity concentration of the low concentration diffusion layer of the transistor directly connected to the external terminal lower than the impurity concentration of the low concentration diffusion layer of the transistor not directly connected to the external terminal. For example, the impurity concentration of the low concentration diffusion layer of a transistor in which the high concentration diffusion layer is not directly connected to an external terminal is 1018~
1019/Cm3, the impurity concentration of the low concentration diffusion layer of the transistor in which the high concentration diffusion layer is directly connected to the external terminal is set to 3 x 101V/cm" or less. In this case, Make the channel length of the connected transistor the same as the channel length of the transistor not directly connected to an external terminal. [00101

[Operation] That is, the present invention reduces the impurity concentration of the low concentration diffusion layer of the MOS transistor that is directly connected to at least one part of the external terminals, and the impurity concentration of the low concentration diffusion layer of the MOS transistor that is not directly connected to at least one part of the external terminal. By making the impurity concentration different, the electrostatic withstand voltage of the MOS transistor directly connected to the external terminal is improved. This is based on the knowledge of the inventor of the present invention that the relationship between the impurity concentration QLDDN- of a MoS transistor and the electrostatic breakdown voltage of the transistor has characteristics as shown in FIG. As is clear from the figure, even if the impurity concentration QLDDN- is increased from the conventionally used concentration Q2 (Q,) or decreased (Q3), the structure approaches the conventional structure and the electrostatic breakdown voltage improves. In this example,
Ql is 3×1019/cm3, Q2 is 3×101
8/cm3, Q3 is 3×1017/cm3. [0011] FIG. 12 shows the relationship between the impurity concentration QLDDN- of the low concentration diffusion layer LDDN- and the electric field in the lateral direction of the substrate. The vertical axis is the electric field strength (X 105V/c
m), and the horizontal axis indicates the position in the horizontal direction of the substrate surface where the low concentration diffusion layer LDDN, the high concentration diffusion layer N0, the gate, etc. are formed, and the boundary between both diffusion layers is set to 0. As shown in the figure, the electric field distribution to the gate in the substrate changes depending on the impurity concentrations Q1, Q2, and Q3. In particular, the peak positions of the electric field appear 0.15 μm inside and 0.02 μm outside the gate edge in the case of Ql and Q3, respectively. And in the case of Q2, the gate edge is 0.0
Appears 5 μm inside. By the way, a bird's beak is formed approximately 0.15 μm inside the gate edge. This part is usually not uniform in shape and often has notches. In the manufacturing process of a MoS transistor, after patterning a polysilicon gate, when post-oxidation progresses on the polysilicon gate, the edge portion at the bottom of the gate is oxidized along the gate width direction. This oxidized area is called a geta hole, and multiple notches are formed here. The notches seem to correspond to grain boundaries of polysilicon. [0012] When a high voltage is applied, breakdown occurs where the electric field is concentrated, so
Breakdowns often occur at the above peak positions. Q
In case 2, since it is a notch part, there are fewer breakdown points than in the other two cases, and the amount of current per unit area at the time of breakdown is large, so that the transistor is destroyed by a low voltage. This is the reason why the breakdown voltage varies depending on the impurity concentration of the low concentration diffusion layer. Increasing the breakdown voltage by changing the impurity concentration may cause a decrease in reliability of the transistor due to generation of substrate current, but in such cases, it is possible to prevent the decrease by changing the channel length or channel width. I can do it. [0013] Examples of the present invention will be described below with reference to the drawings. [0014] FIG. 1 shows an N-channel MOS transistor 11 that is directly connected to external terminals such as input/output terminals, and an internal transistor and N-channel MOS transistor 12 that are not directly connected to input/output terminals.
A DD structure is adopted. Each transistor includes a source 15 and a drain 14 which are high concentration diffusion layers, and a low concentration diffusion layer LDDN- which is in continuous contact with these. Further, the length of the gate 13, that is, the channel length, is different from each other, such that the transistor 12 is L2 and the transistor 11 is L1. Train 14 of transistors 11 is directly connected to I10 terminal 1. [0015] FIGS. 2 to 6 show examples of protection elements that operate in a bipolar manner. Figure 2 shows a P-channel MO8) transistor 2 diode-connected to the I10 terminal 1,
FIG. 3 shows an input protection circuit to which an N-channel Mo8) transistor 3 is connected, and FIG.
It has an input/output circuit consisting of an output P-channel MOS transistor 4 and an N-channel MOS transistor 5. Furthermore, Figure 4 shows an N-channel MO for pull-down.
An input protection circuit with an S transistor 6 is shown. Furthermore, as shown in FIG. 5, there is a case where only the input/output circuit is directly connected to the I10 terminal 1. [0016] FIG. 6 shows a semiconductor substrate 10 of the circuit shown in FIG.
It is a schematic plan view of the upper pattern. A bonding pad as an external terminal (I10 terminal) 1 is formed on the semiconductor substrate 10, and the external terminal 1 is connected to a train 14 of a P-channel MOS transistor 2 and an N-channel MOS transistor 3. This transistor 3 uses a MOS transistor 11 directly connected to the external terminal shown in FIG.
Together with the S transistor 2, it constitutes an input protection circuit. This input protection circuit is connected to an internal circuit such as an inverter circuit IV via an aluminum wiring 9 and a resistor R made of polysilicon. Aluminum wiring 9 connects drain 14 of P-channel MOS transistor 2 and resistor R, and further connects resistor R to gate 13 of Mo8) transistor of inverter circuit IV. The transistors of the inverter circuit IV are, for example, 6
P-channel MOS transistor 21 with MO8 structure
and an N-channel MoS transistor 22. These transistors are internal transistors,
The N-channel transistor 22 uses the MOS transistor 12 described above. Note that in this embodiment, the P-channel transistor does not have an LDD structure. [0017] FIG. 7 shows a semiconductor substrate 10 of the circuit shown in FIG.
It is a schematic plan view of the upper pattern. Here, only MOS transistors directly connected to external terminals are shown, and internal transistors used in internal circuits such as inverter circuits are omitted. The external terminal 1 is directly connected to the input protection circuit and the input/output circuit. The drain 14 of the P-channel MO8) transistor 2.4 constituting these circuits is connected to an internal circuit, for example, an inverter circuit, by an aluminum wiring 9 via a polysilicon resistor R. N-channel MOS transistor 11 shown in FIG. 1 is applied to transistor 3.5 in this figure. [00181 FIG. 8 shows the semiconductor substrate 10 of the circuit shown in FIG.
It is a schematic plan view of the upper pattern. Here, only MOS transistors directly connected to external terminals are shown. In addition to the input protection circuit, an N-channel MOS transistor 6 for pull-down is directly connected to the external terminal 1 to maintain a constant voltage. A train 14 of P-channel MOS transistors 2 constituting these circuits is connected to an internal circuit, for example, an inverter circuit, by an aluminum wiring 9 via a polysilicon resistor R. The N-channel Mo3) transistor 11 shown in FIG. 1 is applied to the transistor 3.6 in this figure. [0019] FIG. 5 shows a semiconductor substrate 10 of the circuit shown in FIG.
It is a schematic plan view of the upper pattern. Here, only MOS transistors directly connected to external terminals are shown. External terminal 1 has no input protection circuit, and is directly connected to P-channel MOS transistor 4 and N-channel MOS transistor 5, which constitute an input/output circuit, and this circuit also serves as a protection circuit. P-channel MO8) Drain 14 of transistor 4 that constitutes these circuits
to an internal circuit, for example, an inverter circuit, are connected via a polysilicon resistor R and an aluminum wiring 9. N-channel Mo8) transistor 1 shown in Figure 1
1 is applied to transistor 5 in this figure. 6 to 9, the source 15 of transistor 2.4
and gate 13 are connected to power supply VDD, and source 15 and gate 13 of transistor 3.5 are connected to power supply VDD.
Connected. In addition, the source 15 of the transistor 6 is
, gate 13 are respectively connected to VDD. [00201] In such a circuit, an LDD structure is employed in the N-channel MOS transistor, for example, in order to prevent deterioration of the characteristics of the MOS transistor due to hot carriers. [00211 In this example, as described above,
The electrostatic breakdown voltage is improved by making the impurity concentrations of the low concentration diffusion layers LDDN - that constitute the LDD structure of these MOS transistors 11 and 12 different from each other. M
The impurity concentration range of the low concentration diffusion layer of the OS transistor 12 is 1018 to 1019/cm'', but the impurity concentration of the low concentration diffusion layer of the MOS transistor 11 for improving the electrostatic breakdown voltage is 3×1019 ~1020/cm3
and 3×1017/cm3 or less. That is, the relationship between the impurity concentration QLDDN- and the electrostatic breakdown voltage has a characteristic as shown in FIG. As is clear from the figure, whether the impurity concentration QLDDN- is increased or decreased, the structure approaches a conventional structure and the electrostatic breakdown voltage improves. In this embodiment, the impurity concentration of the low concentration diffusion layer LDDN - for the MOS transistor 11 is set to Ql, 3×10 19 /cm 3 in the case of a 1.2 μ process, and the MOS
The impurity concentration of the low concentration diffusion layer LDDN- for the transistor 12 is set to Q2.3×10 18 /cm 3 . If the impurity concentration of the low concentration diffusion layer of the MOS transistor 11 remains at Q2, the breakdown voltage is about 50■, but
When Ql and Q3 are reached, the withstand voltage improves to 350■ or more. [0022] MO8) To change the impurity concentration of the low concentration diffusion layer LDDN - of the transistor 11.12, for example,
First, impurity ions are implanted into the MOS transistors 11 and 12 at a dose equal to that of the MOS transistor 12. After this, the low concentration diffusion layer LDDN − of the MOS transistor 11
Impurity ions are implanted only into the In this way, the dose (impurity concentration) for the MOS transistor 11 is adjusted to
If the number of MOS transistors 11 and 12 is the same as L2, as shown in FIG.
It may be larger than 2. [0023] Therefore, as shown by Ll in FIG.
The channel length of the MOS transistor 11 is set to M such that the substrate current Isub of the MOS transistor 11 is the same as that of the MOS transistor 12 when the impurity concentration is Ql.
Reliability can be improved by making the channel length longer than the channel length L2 of the OS transistor 12. MOS) When the channel length L2 of the transistor 12 is 1.2 μm, M
The channel length L1 of the OS transistor 11 is 1.9μ
m or more is suitable, and the optimum value is 1.9 μm. L2
When is 1°0 μm, Ll is suitably 1.5 μm or more, and the optimum value is 1.5 μm. L2 is 0. 8μm
In this case, Ll is suitably 1.2 μm or more. However, if the impurity concentration is made as thin as Q3, the influence of hot carriers will be reduced, so there is no particular need to change the channel length when used in a low voltage circuit. MOS connected to external terminals such as I10 terminal)
Increasing only the channel length of the transistor does not pose a particular problem in terms of design, and although the output current decreases, in reality, it is designed with a sufficient margin, so in many cases it does not pose a problem in practice. [0024]Although the above embodiment has been described with reference to an N-channel MOS transistor, the LDD structure may be applied to a P-channel MOS transistor, or a high breakdown voltage MO similar to the LDD structure, such as a double diffusion structure, may be used.
The present invention may also be applied to S transistors and the like. Figure 1
3 shows a double-diffusion structure MOS) transistor. Both the transistor 11 directly connected to the external terminal and the internal transistor 12 have a drain 14 and a source 1 consisting of a high concentration region n0 and a low concentration region n− outside of the high concentration region n0.
5. The channel length of the transistor 11 is set to L2, and the channel length of the transistor 12 is set to Ll. In order to increase the electrostatic breakdown voltage, the impurity concentrations of the low concentration diffusion layers n- of the transistors 11 and 12 may be made different from each other based on FIG. [0025] Furthermore, the present invention does not need to be applied to all MOS transistors connected to external terminals such as the I10 terminal, and may be applied only to some MOS transistors. For example, N for the input/output circuit shown in Figure 3.
Channel MO8) The impurity concentration of the low concentration diffusion layer of the transistor 5 can be made the same as that of the internal transistor. Since the impurity concentration is the same as that of the internal transistor, reliability is sufficiently ensured. Therefore, although the channel length is not made long, the channel width needs to be appropriately widened in order to improve the withstand voltage. Since the channel width is widened by MOS transistors that are directly connected to only a few external terminals, there is no problem in practical use. [0026] It goes without saying that various other modifications can be made without departing from the gist of the invention. In the embodiment, an inverter is shown as a circuit constituting an internal transistor, but the inverter is not limited to this, and NOR, I'J
There are no particular limitations on the circuits to be applied, such as AND and transmission gates. Further, it is suitable for application to, for example, a microcontroller. [0027]

[Effects of the Invention] As detailed above, according to the present invention, the impurity concentration of the low concentration diffusion layer of the MOS transistor directly connected to the external terminal can be made different from the impurity concentration of the low concentration diffusion layer of the internal transistor. Accordingly, it is possible to provide a semiconductor device that can obtain sufficient electrostatic withstand voltage and at the same time ensure reliability equivalent to that of the conventional semiconductor device.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of essential parts showing an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a circuit according to the present invention.

FIG. 3 is a configuration diagram showing a circuit according to the present invention.

FIG. 4 is a configuration diagram showing a circuit according to the present invention.

FIG. 5 is a configuration diagram showing a circuit according to the present invention.

FIG. 6 is a schematic plan view of a semiconductor device in which the circuit of FIG. 2 is applied to a semiconductor substrate.

FIG. 7 is a schematic plan view of a semiconductor device in which the circuit of FIG. 3 is applied to a semiconductor substrate.

8 is a schematic plan view of a semiconductor device in which the circuit of FIG. 4 is applied to a semiconductor substrate.

9 is a schematic plan view of a semiconductor device in which the circuit of FIG. 5 is applied to a semiconductor substrate.

FIG. 10 is a characteristic diagram showing the relationship between impurity concentration and substrate current corresponding to channel length.

FIG. 11 is a characteristic diagram showing the relationship between impurity concentration and electrostatic breakdown voltage.

FIG. 12 is a diagram showing the relationship between impurity concentration and internal electric field distribution.

FIG. 13 is a sectional view of essential parts showing an embodiment of the present invention.

FIG. 14 is a sectional view of a main part of a conventional semiconductor device.

[Explanation of symbols]

■External terminals (■10 terminals) 2 P-channel MOS transistor 3 N-channel MOS transistor 4 P-channel MO8) transistor 5 N-channel MOS transistor 6
Pull-down N-channel MOS transistor 7
Transistor 8 directly connected to external terminal Internal transistor 9 Aluminum wiring 10 Semiconductor substrate 11 Transistor 12 directly connected to external terminal
Internal transistor 13 Gate 14 Drain 15 Source 21 Internal transistor (P channel MOS transistor) 22 Internal transistor (N channel MOS transistor)

[Figure 1]

[Figure 2]

[Figure 3]

[Figure 5]

[Figure 4]

[Figure 6]

[Figure 10]

[Figure 7]

[Figure 8]

[Figure 9]

[Figure 11]

[Figure 12]

[Figure 14] (72) Inventor Saito Tomotaka

Claims (14)

[Claims] 1. A semiconductor substrate comprising a semiconductor substrate, an external terminal formed on the semiconductor substrate, a low concentration diffusion layer formed on the semiconductor substrate, and a high concentration diffusion layer continuously in contact with the low concentration diffusion layer, an insulated gate field effect transistor in which the high concentration diffusion layer is directly connected to the external terminal; a low concentration diffusion layer formed on the semiconductor substrate; and a high concentration diffusion layer continuously in contact with the low concentration diffusion layer. and an insulated gate field effect transistor in which the high concentration diffusion layer is not directly connected to the external terminal, and the low concentration diffusion layer of the insulated gate field effect transistor is directly connected to at least some of the external terminals. The semiconductor device is characterized in that the impurity concentration of the semiconductor device is different from the impurity concentration of the low concentration diffusion layer of the insulated gate field effect transistor that is not directly connected to at least some of the external terminals. 2. The impurity concentration of the low concentration diffusion layer of the insulated gate field effect transistors that are directly connected to all the external terminals is the same as the impurity concentration of the low concentration diffusion layer of the insulated gate field effect transistors that are not directly connected to all the external terminals. 2. The semiconductor device according to claim 1, wherein the impurity concentration is different from that of the concentration diffusion layer. 3. The impurity concentration of the low concentration diffusion layer of the insulated gate field effect transistor that is directly connected to at least some of the external terminals is such that the impurity concentration of the low concentration diffusion layer of the insulated gate field effect transistor that is directly connected to at least some of the external terminals is lower than that of the insulated gate field effect transistor that is not directly connected to all of the external terminals. 2. The semiconductor device according to claim 1, wherein the impurity concentration is different from the impurity concentration of the low concentration diffusion layer. 4. The semiconductor device according to claim 1, wherein the low concentration diffusion layer is also a diffusion layer of an LDD structure or a double diffusion structure. 5. The impurity concentration of the low concentration diffusion layer of the transistor directly connected to the external terminal is higher than the impurity concentration of the low concentration diffusion layer of the transistor not directly connected to the external terminal. A semiconductor device according to any one of claims 1 to 3. 6. The impurity concentration of the low concentration diffusion layer of a transistor directly connected to the external terminal is lower than the impurity concentration of the low concentration diffusion layer of a transistor not directly connected to the external terminal. A semiconductor device according to any one of claims 1 to 3. 7. The semiconductor device according to claim 5, wherein the channel length of the transistor directly connected to the external terminal is longer than the channel length of the transistor not directly connected to the external terminal. 8. The semiconductor device according to claim 6, wherein the channel length of the transistor directly connected to the external terminal is the same as the channel length of the transistor not directly connected to the external terminal. 9. The impurity concentration of the low concentration diffusion layer of the transistor not directly connected to the external terminal is 1018 to 1.
019/cm3, the impurity concentration of the low concentration diffusion layer of the transistor directly connected to the external terminal is 3 x 1019 to 3 x 1020/cm3. Device. 10. In a transistor in which the high concentration diffusion layer is not directly connected to an external terminal, the low concentration diffusion layer has an impurity concentration of 1018 to 1019/cm3, and the high concentration diffusion layer is directly connected to the external terminal. The impurity concentration of the low concentration diffusion layer of the transistor is 3×1017
7. The semiconductor device according to claim 6, wherein the semiconductor device has a temperature of /Cm3 or less. 11. In the case where the channel length of the transistor not directly connected to the external terminal is 1.2 μm, the channel length of the transistor directly connected to the external terminal is 1.9 μm or more. The semiconductor device according to claim 7. 12. In the case where the channel length of the transistor not directly connected to the external terminal is 1.0 μm, the channel length of the transistor directly connected to the external terminal is 1.5 μm or more. The semiconductor device according to claim 7. 13. In the case where the channel length of the transistor not directly connected to the external terminal is 0.8 μm, the channel length of the transistor directly connected to the external terminal is 1.2 μm or more. The semiconductor device according to claim 7. 14. The transistor directly connected to the external terminal constitutes an input protection circuit consisting of a pair of N-channel and P-channel insulated gate field effect transistors whose drains are connected to the external terminal. The transistors that are not directly connected to the input protection circuit constitute an inverter circuit consisting of a pair of N-channel and P-channel insulated gate field effect transistors whose gates are connected via a resistor. N
The impurity concentration of the low concentration diffusion layer of the channel insulated gate field effect transistor is 3 x 1019/Cm3, the channel length is 1.9 μm, and the impurity of the low concentration diffusion layer of the N channel insulated gate field effect transistor of the inverter circuit is Concentration: 3×1018/Cm3, channel length: 1.2
6. The semiconductor device according to claim 5, wherein the semiconductor device has a diameter of μm.