JP3231305B2 - Active matrix substrate manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a driver-integrated active matrix substrate, and more particularly to a method of manufacturing signal wiring or signal electrodes provided on the active matrix substrate.

[0002]

2. Description of the Related Art FIG. 9 schematically shows a structure of a liquid crystal display device using a conventional driver-integrated active matrix substrate. In the figure, reference numeral 21 denotes a glass substrate or a quartz substrate, on which a gate drive circuit 22, a source drive circuit 23, and a TFT (ThinFilm Transistor) are provided.
(tor) Array section 24 is formed. A large number of mutually parallel gate bus lines 1 extending from the gate drive circuit 22 are arranged in the TFT array section 24. A large number of mutually parallel source bus lines 2 extending from the source drive circuit 23 are arranged orthogonally to the gate bus lines 1. An additional capacitance common line 3 is provided in parallel with each gate bus line 1.

Here, a thin film transistor (hereinafter referred to as TFT) 25, a picture element 26, and a rectangular area surrounded by an adjacent source bus wiring 2, an opposing gate bus wiring 1 and an additional capacitance common wiring 3 are provided. And an additional capacity 27 are provided. The gate electrode of the TFT 25 is connected to the gate bus line 1, and its source electrode is connected to the source bus line 2. Liquid crystal is sealed between a pixel electrode connected to the drain electrode of the TFT 25 and a counter electrode on the counter substrate, thereby forming a pixel 26. The additional capacitance common line 3 commonly connected to the additional capacitance 27 is connected to an electrode having the same potential as the counter electrode.

[0004]

By the way, in such a liquid crystal display device, as the driver section of the liquid crystal panel becomes smaller and higher definition, the wirings are diversified, the intersections of the wirings are increased, and the wirings are lengthened. .

FIG. 10 shows a part of the configuration of a conventional source driver (source drive circuit). In this drive circuit, four series of shift registers A to D are driven by four series of clocks 13 to 16 in order to increase the operating frequency. Here, A1 to A3, B1 to B3, C
1 to C3, D1 to D3 are unit shift registers,
It is composed of one inverter and two clocked inverters. In each unit shift register, input / output of a shift signal and output of a bit signal are performed.

For example, in a D-series shift register, pulses input to an input node D _in are sequentially transmitted to unit shift registers D ₁ , D ₂ , and D ₃ by clocks φ _D and / φ _{D having} phases opposite to each other. And output to the output node D _out . Also, individual unit shift registers D ₁ , D ₂ , D
Another output (bit signal output) from ₃ is sent to the analog switch AS.

FIG. 11 shows a part of the layout of the shift register shown in FIG. 10 on a substrate. In this figure, reference numerals 17 and 18 denote N-channel TFTs and P-channel TFTs disposed adjacently on an insulating substrate, and these constitute a clocked inverter. A low-voltage power supply line 11 is connected to one end of the transistor region 17a of the N-channel TFT 17 via the contact hole 5, and a high-voltage power supply line 12 is connected to one end of the transistor region 18a of the P-channel TFT 18. It is connected via a contact hole 5. The other ends of the transistor regions 17a and 18a are
It is connected to one signal wiring 19 via the contact hole 5.

In the vicinity of the transistor region,
Clock lines 13 to 16 are arranged in parallel with the trunk line of the low-voltage side power supply line 11.

Here, on the island-shaped transistor region 17a of the N-channel TFT 17, a signal line 27 having one end connected to the non-inverting side φ _D of the clock line 16 is provided.
Is extended. Further, on the island-shaped transistor region 18a of the P-channel TFT 18, one end extends the other end portion of the inverted side / phi signal wiring 28 connected to the _D of the clock line 16. Further, a signal wiring 29 is provided so as to extend over both the transistor regions 17a and 18a.

In the portions A, B and C in FIG. 11, poly-Si or Al used for the gate electrode is used.
The wiring consisting of is longer. In a structure in which one end of such a long wiring is directly located on the channel region of the TFT, when ions such as P ⁺ and B ⁺ are implanted into the transistor region to determine the N channel and the P channel, Dielectric breakdown often occurred in the gate insulating film.

This often occurs especially on a signal input unit from a clock generation unit in a clocked inverter used for a shift register or on an N-channel or P-channel island constituting a CMOS inverter.
A situation has occurred in which a shift register subsequent to the destructive shift register does not operate.

Next, dielectric breakdown of the gate insulating film will be described with reference to an ion implantation process for forming a CMOS inverter as an example. FIG. 12 is a plan view showing a layout of a simple inverter, and FIGS.
FIG. 3D is a diagram illustrating a structure of a cross section taken along line ee ′ in FIG. 12 in order of process.

On the glass substrate 21, polycrystalline silicon thin films 111 and 112 serving as an N channel and a P channel, a gate insulating film 113 and a gate electrode 114 are sequentially formed. The gate electrode 114 serves as an input of the inverter, and a part thereof is located on the N and P channels. In this figure, the left side is an N-channel transistor, and the right side is a P-channel transistor (FIG. 13).
(A)).

A resist pattern 115 is formed so as to cover the P-channel TFT portion, and P ⁺
To form a channel portion 116 (FIG. 13).
(B)).

A resist pattern 117 is formed so as to cover the N-channel TFT portion, and B ⁺
To form a channel portion 118 (FIG. 13).
(C)).

After forming an interlayer insulating film 119 on the entire surface and forming a contact hole 120 in the interlayer insulating film 119, electrodes 121, 122 and 123 are formed by forming and patterning a metal film. Here, the N-channel electrode 121 is connected to the low-voltage power supply, the P-channel electrode 123 is connected to the high-voltage power supply line, and the electrode 122 becomes the output terminal of the inverter (FIG. 13D).

Therefore, at the time of ion implantation, the island of the polycrystalline thin film and the gate electrode are present, and the metal layer has not been formed yet. The cause of the TFT breakdown is that the wiring made of the same material as the gate located on the polycrystalline thin film is long, so that charges tend to leak from the wiring portion to the resist at the time of ion implantation. It is considered that the potential of the resist causes the potential difference between the gate electrode being implanted and the polycrystalline thin film sandwiching the gate insulating film, resulting in the destruction of the gate insulating film.

Such destruction of the gate insulating film is a problem not only in the transistors constituting the inverters and clocked inverters of the shift register, but also in the transistors constituting the analog switches and the transistors for picture elements. Will be described.

FIG. 14A is a layout diagram showing the vicinity of an analog switch in a conventional example, and FIG.
It is a figure which shows the structure of the ff 'line cross section of (a). In the figure, 133 is an analog switch formed on the insulating substrate 21, and 131 is a signal wire having one end connected to the output of the shift register. The other end of the signal wiring 131 passes through the buffer section and further below the three B, G, and R video lines 134 to form a transistor region (polycrystalline silicon thin film) 133a constituting the analog switch 133.
Extending over the channel. The video signal is supplied from each video line 134 to the analog switch 133 through the wiring 135. The video signal sampled by the analog switch 133 is written to the picture element of the display unit 24 through the wiring 132. The insulating substrate 2
The process of forming the analog switch 133 on the transistor 1 is basically the same as the process of forming one transistor of the CMOS inverter shown in FIG.

In such a configuration, the signal wiring whose one end side is the gate electrode of the transistor forming the analog switch has a long wiring length, and thus the gate insulating film is broken as described above. Becomes

FIG. 15 is an enlarged view of one picture element in a conventional active matrix substrate. In this figure, the additional capacitance common wiring is omitted for simplification. Here, 2a and 2b are source bus lines, 1a and 1
b is a gate bus line, 25a is a picture element electrode, 25 is a picture element TFT, and each symbol corresponds to that in FIG.

In this configuration, since the gate bus line connected to the gate electrode of each pixel TFT has a very long wiring length, the gate insulating film of the pixel TFT is destroyed by charge-up in the ion implantation step. Will be invited.

As an example of a method for preventing such charge-up at the time of ion implantation of a TFT, as shown in JP-A-59-104173, a conductive film is formed on the entire surface of an insulating substrate at the time of ion implantation into a TFT. A method of reducing damage to a TFT by depositing a conductive thin film and discharging charges generated during ion implantation to the outside has been taken.

However, this method not only requires an additional step of forming a conductive film, but also requires a process such as thermal oxidation of the conductive thin film.

Further, as disclosed in Japanese Patent Application Laid-Open No. Hei 5-198807, there is known a method in which all the gate electrodes of the thin film transistor are short-circuited and the atmosphere pressure is controlled in a state where the gate electrodes are integrated on the outer periphery of the substrate, and ions are implanted. However, this method has a problem that a process for separating the short-circuited gate electrode must be performed later, which increases the number of steps.

The present invention has been made in order to solve the above-mentioned problems, and a driver capable of suppressing the destruction of a gate insulating film of a TFT during ion implantation without increasing the number of processing steps. It is an object of the present invention to provide a method for manufacturing an integrated active matrix substrate.

[0027]

According to the present invention, there is provided a method of manufacturing an active matrix substrate, comprising: a plurality of top gate thin film transistors formed on an insulating substrate; and a signal wiring for supplying a signal to a gate electrode of each thin film transistor. Forming a semiconductor layer and a gate insulating film patterned in a predetermined shape on an insulating substrate, and a wiring body of a signal wiring having an isolation portion by using the same layer material as the gate electrode. Forming a portion, performing ion implantation on the semiconductor layer using the wiring main body as a mask, and forming a wiring connecting portion connecting portions sandwiching the separation portion of the wiring main body. It is characterized by doing.

Further, according to the method for manufacturing an active matrix substrate of the present invention, a plurality of top gate thin film transistors constituting a shift register formed on an insulating substrate, and a signal for supplying a clock signal to each of the thin film transistors from a clock line. A method for manufacturing an active matrix substrate having wiring, a step of forming a semiconductor layer and a gate insulating film patterned into a predetermined shape on an insulating substrate, and a signal wiring having an isolation portion by the same layer material as the gate electrode Forming a wiring body portion, performing ion implantation using the wiring body portion as a mask, and forming a wiring connection portion that connects portions of the wiring body portion sandwiching the separation portion. It is characterized by the following.

Further, according to the method of manufacturing an active matrix substrate of the present invention, a plurality of top gate thin film transistors forming an analog switch, which are formed on an insulating substrate, are arranged so as to intersect with a video line, and a shift register is provided. A method for manufacturing an active matrix substrate having a signal wiring for supplying an output to a gate electrode of a thin film transistor as an analog switch, comprising: forming a semiconductor layer and a gate insulating film patterned in a predetermined shape on an insulating substrate; A step of forming a wiring main body of a signal wiring having a separation part by using the same layer material as the gate electrode; a step of performing ion implantation using the wiring main body as a mask; Forming a wiring connection portion to be connected.

Further, the method of manufacturing an active matrix substrate according to the present invention is characterized in that a plurality of top-gate N-channel thin-film transistors and P-channel thin-film transistors constituting an inverter or a clocked inverter included in a shift register are formed on an insulating substrate. Connected to the inverter or clocked inverter,
What is claimed is: 1. A method of manufacturing an active matrix substrate having a signal wiring extending on one channel of one of N-channel and P-channel transistors constituting the same, the semiconductor being patterned into a predetermined shape on an insulating substrate. A step of forming a layer and a gate insulating film; a step of forming a wiring main body of a signal wiring having an isolation portion by using the same layer material as the gate electrode; a step of performing ion implantation using the wiring main body as a mask; Forming a wiring connection portion connecting portions sandwiching the separation portion of the main body portion.

Further, according to the method of manufacturing an active matrix substrate of the present invention, there is provided an active matrix having a picture element thin film transistor constituting a display portion and a gate bus line for supplying a signal to a gate electrode of the thin film transistor on an insulating substrate. A method for manufacturing a substrate, comprising: forming a semiconductor layer patterned into a predetermined shape and a gate insulating film on an insulating substrate; and forming a wiring body portion of a gate bus line having an isolation portion by using the same layer material as the gate electrode. Forming a wiring, a step of performing ion implantation using the wiring main body as a mask, and a step of forming a wiring connecting part connecting signal wiring parts sandwiching the separation part of the wiring main body. Features.

A separation section of the wiring main body section is provided for each picture element at the intersection of the source bus lines.

The separating portion of the wiring main body is provided for each picture element between adjacent source bus lines.

In the method of manufacturing an active matrix substrate according to the present invention, a plurality of thin film transistors are provided on an insulating substrate, and at least a part of the plurality of thin film transistors is provided in plural in the channel width direction. A method for manufacturing a divided active matrix substrate, wherein a step of forming a semiconductor layer and a gate insulating film patterned into a predetermined shape on an insulating substrate and a step of forming an electrode main body of a gate electrode having an isolation portion And a step of performing ion implantation using the electrode main body as a mask, and a step of forming an electrode connecting part connecting portions of the electrode main body sandwiching the separation part.

Further, in the method of manufacturing an active matrix substrate according to the present invention, a plurality of top gate thin film transistors are provided on an insulating substrate, and a signal electrode is connected to a gate electrode of at least a part of the plurality of thin film transistors. A method of manufacturing an active matrix substrate to which a dummy signal wiring to which no application is applied is connected, by forming a continuous wiring pattern by patterning a predetermined wiring layer of the same layer material as the gate electrode. It is characterized by having to have.

In the present invention, at least a part of the plurality of thin film transistors constituting the driver-integrated active matrix substrate is connected to a signal wiring having one end serving as a gate electrode of the thin film transistor. A wiring main body having an isolation portion near the region is formed by patterning a first wiring layer, and a wiring connection portion for connecting portions of the wiring main body arranged with the separation portion interposed therebetween is formed by the first wiring layer. Since the second wiring layer is formed by patterning the second wiring layer different from the wiring layer, the ion implantation that causes charge-up of the signal wiring is performed in a state where the wiring main body is formed, and then the wiring connection section is formed. By connecting the portions arranged with the separating portion of the wiring body portion therebetween by the formation of The breakdown of the gate insulating film of the TFT can be suppressed in.

Therefore, it is possible to drastically reduce defects in the shift register including the TFT as a circuit element in the liquid crystal display device with a built-in driver.

In the present invention, for at least a part of the plurality of thin film transistors constituting the driver-integrated active matrix substrate, a signal wiring for inputting a clock signal from a clock line to a gate electrode of the thin film transistor is provided. After the formation of the wiring main body having the separation portion, the formation of the wiring connection portion connecting the portions arranged with the separation portion interposed therebetween not only prevents the breakdown of the gate insulating film but also reduces the length of the separation portion. By adjusting the resistance of the wiring body and the wiring connection, the wiring resistance from each clock line to the shift register can be made uniform.

Therefore, the clock signal is hardly out of synchronization, and the shift register does not malfunction.

In the present invention, a gate bus line, part of which is a gate of a TFT of each picture element, is formed by forming a wiring main body having a separation section for each picture element, and then sandwiching the separation section. The structure is such that a wiring connection part connecting the parts arranged in is formed, so that the gate bus line is made to have a low resistance by using a low-resistance material for the wiring connection part as well as preventing the breakdown of the gate insulating film. It can also prevent signal delay.

In the present invention, for at least some of the plurality of thin film transistors constituting the driver-integrated active matrix substrate, a dummy signal wiring to which no signal is applied is connected to the gate electrode of the thin film transistor. Since the dummy signal wiring is formed into a structure having a continuous wiring pattern by patterning a predetermined wiring layer of the same layer material as the gate electrode, the dummy wiring is charged by the signal wiring generated at the time of ion implantation after the formation of the signal wiring. The destruction of the gate insulating film can be concentrated on the dummy signal wiring by making the length of the gate wiring in the dummy signal wiring longer than the length of the gate wiring of the normal signal wiring. As a result, the breakdown of the gate insulating film in the normal signal wiring can be almost avoided.

[0042]

(Embodiment 1) FIG. 1 is a schematic plan view for explaining a driver-integrated active matrix substrate of a liquid crystal display device according to a first embodiment of the present invention. Shift register 1
The part is shown. FIG. 2A is a cross-sectional view of a picture element TFT constituting the driver-integrated liquid crystal display device. FIG. 2B is a diagram showing a cross-sectional structure of a portion X in FIG. Although only the X portion in FIG. 1 is shown here, the Y and Z portions in FIG. 1 also have the same cross-sectional structure as the X portion. In the figure, the same reference numerals as those in FIG.
This is a signal line for inputting a non-inverted clock signal φD from the clock line 16 to the gate electrode of the thin film transistor 17. The signal wiring 127 is formed by patterning a polycrystalline silicon film (first wiring layer), and is formed by patterning a wiring main body 107 having an isolation portion 107a near an active layer 17a of the thin film transistor and an aluminum film. And a wiring connecting portion 117 for connecting portions of the wiring main body which are arranged with the separating portion 107a interposed therebetween.

Reference numeral 128 denotes the thin film transistor 18
And a signal line for inputting the inverted clock signal / φD from the clock line 16 to the gate electrode of the signal line 127.
Similarly to the above, the active layer 18 is formed by patterning a polycrystalline silicon film (first wiring layer).
The wiring body 108 includes a wiring portion 108 having a separating portion 108a in the vicinity of a, and a wiring connecting portion 118 formed by patterning an aluminum film and connecting the portions of the wiring body disposed with the separating portion 108a interposed therebetween.

Reference numeral 129 is a signal wiring provided so as to extend over both the transistor regions 17a and 18a. The signal wiring 129 is formed by patterning a polycrystalline silicon film (first wiring layer), and is formed by patterning a wiring body 109 having an isolation portion 109a between the transistor regions 17a and 18a and an aluminum film. And a wiring connection portion 119 for connecting portions arranged on both sides of the separation portion 109a of the main body.

Here, each of the wiring bodies 107, 108, 1
09 and the wiring connection portions 117, 118, 119 are connected via the contact hole 5.

FIG. 16 shows another part of the shift register in the driver section of the liquid crystal display device of the first embodiment. X1 part and Z1 part of FIG.
It has the same cross-sectional structure as the X part of FIG. 1 shown in (b). In this figure, reference numerals 37 and 38 denote N-channel TFTs and P-channel TFTs arranged adjacently on an insulating substrate, and these constitute a clocked inverter. The low-voltage side power supply line 11 is connected to one end of the transistor region 37a of the N-channel TFT 37 through the contact hole 5, and the P-channel TFT
The high voltage side power supply line 12 is connected to one end of the transistor region 38 a of the FT 38 via the contact hole 5. Further, the two transistor regions 37a, 38
The other end of “a” is connected to one signal wiring 19 via the contact hole 5.

527 is the thin film transistor 37
Is a signal line for inputting the inverted clock signal / φA from the clock line 13 to the gate electrode of the first embodiment. The signal wiring 527
Is formed by patterning a polycrystalline silicon film (first wiring layer), and is formed by patterning a wiring body 507 having a separation portion 507a near an active layer 37a of the thin film transistor, and by patterning an aluminum film. And a wiring connection portion 517 for connecting portions arranged with the portion 507a therebetween.

Reference numeral 48 denotes a signal line for inputting a non-inverted clock signal φA from the clock line 13 to the gate electrode of the thin film transistor 38. This signal line has a gate line length, that is, a clock signal from the gate electrode of the thin film transistor 38. Since the distance to a signal line such as a line is shorter than other signal wirings, a separation portion as in the signal wiring 527 is not provided.

Numeral 529 is a signal wiring provided so as to extend over both the transistor regions 37a and 38a. The signal wiring 529 is formed by patterning a polycrystalline silicon film (first wiring layer), and is formed by patterning a wiring body 509 having an isolation portion 509a between the transistor regions 37a and 38a and an aluminum film. And a wiring connection portion 519 for connecting portions disposed on both sides of the separation portion 509a of the main body.

Although the inverter constituting the shift register of the present embodiment is not shown, at least some of the plurality of inverters in the shift register are clocked inverters shown in FIG. 1 or FIG. Similarly to the above, a signal wiring provided so as to extend over both the N-channel TFT and the P-channel TFT constituting the inverter is formed by patterning a polycrystalline silicon film (first wiring layer). And a wiring connection portion formed by patterning the aluminum film and connecting portions of the wiring body sandwiching the separation portion.

Next, the manufacturing method will be described.

First, the semiconductor layer 6 is formed on the entire surface of the insulating substrate 21.
02 is formed by a CVD method. Next, an insulating film to be a gate insulating film 603 is formed by a CVD method, a sputtering method, or thermal oxidation of the upper surface of the polycrystalline thin film. The thickness of the gate insulating film 603 is about 100 nm
It is.

Next, the polycrystalline thin film and the insulating film are patterned to form a semiconductor layer 602 having a thickness of 40 nm to 80 nm.
To form The above-described formation of the gate insulating film 603 may be performed after pattern formation of the semiconductor layer. Before the formation of the insulating film, a process such as laser annealing or annealing in a nitrogen atmosphere can be performed to enhance the crystallinity of the polycrystalline silicon thin film.

Next, a polycrystalline silicon thin film which will later become the gate bus wiring 1 is formed to a thickness of about 450 nm by the CVD method and is doped. Thus, a low-resistance polycrystalline silicon thin film is obtained.

Thereafter, signal wirings 127 and 12 having the shape shown in FIG. 1 are formed by patterning low-resistance polycrystalline silicon.
8, 129, and 507, 509 of the signal wires 527, 529 having the shape shown in FIG. 16, and the signal wire 48 shown in FIG. A part of the wiring main bodies 107, 108, 109 is composed of the transistors 17,
18 and the wiring body 507,
A part of 509 and a part of the signal wiring 48 are gate electrodes of the transistors 37 and 38 constituting the shift register. At this time, the gate electrode 604 is formed in the picture element TFT. The gate electrode may be formed of a metal such as Al.

Next, using the gate electrode 604 as a mask,
Using a resist mask formed by a photolithography method, ions are implanted into portions of the semiconductor layer 602 other than below the gate electrode 604 to determine the N-type and P-type of the TFT. As a result, a channel portion 602a is formed. At this time, a channel portion is also formed in each of the transistor regions 17a, 18a, 37a, and 38a.

Thereafter, a first interlayer insulating film 605 is formed on the entire surface of the substrate to a thickness of 700 nm, and a contact hole 606 for the interlayer insulating film is formed. At this time, the transistor regions 17a and 18a and the wiring body 10
7, 108, 109, the separation units 107a, 108a, 1
The contact hole 5 is also formed on the end near the area 09a, and the isolation portions 507a, 509 of the transistor regions 37a, 38a and the wiring main bodies 507, 509 are formed.
A contact hole 5 is also formed on the end near “a”.

Next, a wiring pattern 607 is formed to a thickness of about 600 nm using a low-resistance metal such as A1. At this time, the separation unit 1 of the wiring main bodies 107, 108, 109
Wiring connector 11 for connecting 07a, 108a, 109a
7, 118 and 119 are formed, and wiring connection portions 517 and 519 for connecting the separation portions 507a and 509a of the wiring main portions 507 and 509 are also formed. This time, picture element T
In the FT portion, a contact hole 606 for connecting the drain electrode of the TFT and the pixel electrode 611 after forming the first interlayer insulating film 605 to prevent a contact failure.
Is formed and embedded with a metal such as A1. Thereby, the step between the drain electrode and the picture element electrode 611 is reduced.

After that, a second interlayer insulating film 608 is formed to a thickness of 600 nm, and a contact hole 609 is formed in this. This contact hole 609 has A1 and IT
TiW, WSi, to make O ohmic contact
A metal layer 610 of Mo, W, or the like is embedded and formed.

Next, a pixel electrode 611 is formed to a thickness of about 150 nm by patterning the transparent electrode ITO.
The picture element portion is manufactured by such a process, and the TFTs 17, 18, 37, and 38 of the shift register portion are manufactured.

As described above, in the present embodiment, of the plurality of thin film transistors constituting the liquid crystal display device, a part of the predetermined thin film transistors is used as the signal lines 127, 128, and 12 which are the gate electrodes of the thin film transistors.
9, 517 and 519 are provided near isolation regions 107a, 108a, 109a, 507a and 5
Wiring body 10 made of polycrystalline silicon and having 09a
7, 108, 109, 507, 509, and wiring connecting portions 117, 118, 119, 517 made of aluminum for connecting the portions arranged with the separating portion of the wiring body therebetween.
519, the ion implantation that causes charge-up of the signal wiring is performed in a state where the wiring main body is formed, and then, by forming the wiring connecting portion, the portion arranged with the separating portion of the wiring main body interposed therebetween. The connection between them can prevent the gate insulating film of the TFT from being broken at the time of ion implantation.

Therefore, it is possible to drastically reduce defects in the shift register including the TFT as a circuit element in the liquid crystal display device with a built-in driver.

A signal line 12 for inputting a clock signal from a clock line to the gate electrode of the thin film transistor
7, 128, and 517 are composed of the wiring body having the above-mentioned separating portion and the wiring connecting portion connecting the portions arranged with the separating portion of the wiring body therebetween, so that not only the prevention of the gate insulating film from being broken, but also the By adjusting the length of the separation part and the resistance of the wiring body and the wiring connection part, the wiring resistance from each clock line to the shift register can be made uniform.

The present inventor prepared a 300-stage shift register in which the distance from the TFT to the wiring connection portion made of aluminum (the length of the gate wiring from the transistor) was changed to 10 μm, 100 μm, and 200 μm. Evaluated the yield of the shift register. In FIG. 3, the horizontal axis represents the length from the TFT to the connection portion made of metal, and the vertical axis represents the yield of a 300-stage shift register. According to this experiment, 30% when the distance from the TFT to the connection portion is 200 μm, 85% when the distance is 100 μm, 1
At 0 μm, a 98% yield was obtained. Also in this experiment, it was confirmed that the yield of the shift register was increased by shortening the distance from the TFT to the connection portion made of metal.

(Embodiment 2) FIG. 4 is a view for explaining an active matrix substrate of a liquid crystal display according to a second embodiment of the present invention. In the above embodiment, the gate line input to the clocked inverter is separated from the clock line of the shift register. However, in this embodiment, at least a part of the plurality of analog switches constituting the driver in the liquid crystal display device is used. In this analog switch, a structure having a separation unit similar to that of the first embodiment is realized at the gate input part.

In the figure, the same reference numerals as those in FIG. 14A denote the same parts, and 227 denotes a B, G, R video line 1
The signal wiring is arranged so as to intersect with 34 and supplies the output from the shift register to the analog switch 133. The signal wiring 227 is formed by patterning a polycrystalline silicon film or the like. The signal wiring 227 is formed by patterning a wiring body 207 having an isolation portion 207a near an active layer of a thin film transistor constituting the analog switch 133 and an aluminum film. And a wiring connection part 217 for connecting parts arranged on both sides of the separation part 207a of the main body.

Also in the second embodiment having such a structure, in the state where the wiring body 207 of the gate wiring 227 to the analog switch is formed, ion implantation for setting the conductivity of the transistor is performed. Separation part 2
By connecting 07a with a metal used in a later step, the analog switch 133 can be prevented from being damaged by charge-up of the gate insulating film.

(Embodiment 3) FIG. 5 is a view for explaining an active matrix substrate of a liquid crystal display according to a third embodiment of the present invention.

Unlike the other circuit portions of the driver, the buffer portion of the gate driver or the source driver or the analog switch for sampling the video signal in the above liquid crystal display device has a width of 100 μm.
m or more TFTs are used.

In this case as well, compared to a TFT having a small width, T
It has been found that FT is easily broken during ion implantation. In this case, as shown in FIG. 5, a layout having a normal layout (TFT width 2 W) (FIG. 5A) is divided into two layouts having a width W as shown in FIG. The gate electrode is separated between the divided TFTs, and the separated portion is connected by another wiring after the ion implantation process, so that the TF is reduced.
T can be prevented from being destroyed. Here, 121a is a signal input line, 122a is a signal output line, and 123a is a gate electrode.

That is, the thin film transistor 125 constituting the analog switch has a channel width of 100 μm or more and is divided into a plurality in the channel width direction. The gate electrode 22 of the thin film transistor 125
3 is formed by patterning a polycrystalline silicon film or the like, and an adjacent divided portion 125 of the thin film transistor is formed.
electrode body 1 having a separating portion 103a between a and 125b
03 and a portion formed by patterning an aluminum film or the like and arranged with the separation portion 103a of the electrode body portion interposed therebetween.
And an electrode connecting portion 113 for connecting them.

In this case, similarly to the above embodiments, the analog switch can be prevented from being destroyed due to charge-up.

(Embodiment 4) FIG. 6 is a view for explaining an active matrix substrate of a liquid crystal display device according to a fourth embodiment of the present invention, and shows one picture element of the active matrix substrate in an enlarged manner. ing.

When the TFT of the liquid crystal display portion of the liquid crystal display device is destroyed during ion implantation, the main portion of the gate bus line has a structure having a separation portion for each picture element, and a metal layer used in a later step is formed. It is possible to cope with this by connecting the separation section.

In the figure, the same reference numerals as those in FIG. 15 denote the same parts, and in this embodiment, the gate bus line 32
1 is formed by patterning a polycrystalline silicon film or the like, and is formed by patterning a wiring body 301 having an isolation portion 301a for each picture element at an intersection 57 with a source bus line, and an aluminum film or the like. And a wiring connection unit 311 for connecting the separation unit 301a. Similarly to the gate bus line 321, the gate bus line 322 also includes a wiring body 302 having a separation portion 302a for each picture element at the intersection 58, and a portion of the wiring body 302 which is disposed with the separation portion 302a interposed therebetween. And a wiring connection unit 312 to be connected.

Here, since the isolation portion 301a of the gate bus line 321 cannot be connected with the same layer of metal film as the source bus line 2a, the wiring body 301 of the gate bus line 321 and the aluminum layer 607 as shown in FIG. And
Contact hole 606 in first interlayer insulating film 605
The separation portion 301a at the intersection 57 of the source bus line and the gate bus line is connected by a metal layer 610 such as TiW or Mo.

As described above, also in the present embodiment, the gate bus line 3 partly serving as the gate electrode of the pixel TFT is formed.
21 and 322, in the state where ion implantation is performed,
Only the wiring main bodies 301 and 302 having a separation part for each picture element can be formed. By doing so, it is possible to prevent discharge breakdown of the gate insulating film in the pixel TFT during ion implantation.

When the metal material of the wiring connection portion has a lower resistance than the gate electrode, it is possible to prevent a signal delay in the gate bus line.

In FIG. 6, the separation of the gate bus line is connected at the intersection of the gate bus line and the source bus line, but the present invention is not limited to this. For example, as shown in FIG. 8, the gate bus line 421 is
A wiring main body 401 formed by patterning the wiring layer of FIG. 1 and having a separation portion 401a for each pixel between adjacent source bus lines, and a second wiring layer 401 different from the first wiring layer.
And a wiring connecting portion 411 connecting the portions of the wiring main body that are arranged with the separating portion 401a interposed therebetween . Similarly to the gate bus line 421, the gate bus line 422 has a wiring body 402 having a separation portion 402a for each picture element.
And a wiring connection portion 412 that connects portions of the wiring main body 402 that are arranged with the separation portion 402a interposed therebetween.

(Embodiment 5) FIG. 17 is a diagram showing a part of the configuration of a source driver in a driver-integrated active matrix substrate of a liquid crystal display device according to a fifth embodiment of the present invention. The same reference numerals denote the same parts as those of the conventional shift register. D4 denotes the last part of the D series shift register, that is, a dummy unit shift register provided on the output side of the unit shift register D3. Unlike D3 to D3, the output pulse is not supplied to the analog switch.
In this case, the dummy signal wiring connected to the gate electrode of the thin film transistor constituting the thin film transistor has a pattern in which the gate insulating film is easily broken. The other unit shift registers have the same configuration as the first embodiment.

FIG. 18 is a plan view showing a part of the shift register constituting the source driver, and shows a layout of the dummy unit shift register D4 on the substrate. In the figure, the same reference numerals as those in FIG. 11 denote the same components, and the dummy signal wirings 727 and 729 are not provided with the wiring connection portions as in the conventional one in order to easily cause discharge breakdown. Here, the dummy signal wiring 728 has a meandering portion 728 in order to more easily cause discharge breakdown.
a. The meandering portion 72
Instead of the dummy signal wiring 728 having 8a, a dummy signal wiring 728 having the same structure as that of the related art and having no wiring connection portion may be used.
Here, a contact hole for electrically connecting the dummy signal wirings 727 and 728 to the clock line 16 is not formed.

In the present embodiment having such a configuration, a dummy unit shift register D4 that does not send an output pulse to the analog switch is provided at the last part of the D-series shift register, and this dummy unit shift register is liable to be damaged by discharge. Since a structure having a signal wiring pattern is employed, when a discharge occurs, a discharge breakdown occurs in this portion, and the T inside the shift register for transferring a signal.
It is possible to make it difficult for the FT to be destroyed by electric discharge.

That is, in the present embodiment, the dummy signal lines 727 and 72 in the dummy unit shift register D4
No wiring connection portion is provided in the dummy signal wiring 728.
Meandering portion 728 for facilitating discharge breakdown
a, the length of the gate wiring in the dummy signal wiring forming the dummy unit shift register is longer than the length of the gate wiring in the signal wiring having the wiring connection part forming the normal unit shift register. In addition, discharge breakdown in the dummy unit shift register is likely to occur, thereby suppressing discharge breakdown in a normal unit shift register.

Since no contact hole for electrically connecting the dummy signal wirings 727 and 728 to the clock line 16 is formed, even if discharge breakdown occurs in the TFTs 17 and 18 of the dummy unit shift register D4, the clock line is not affected. It does not affect φD and / φD.

In the present embodiment, a dummy unit shift register, which is more susceptible to discharge breakdown than a normal unit shift register, is provided at the last part of the shift register to suppress discharge breakdown in the normal unit shift register. However, a dummy picture element pattern which is not involved in display is provided in the periphery of the display section of the liquid crystal display device, and the TFT corresponding to this picture element pattern is more likely to cause a discharge breakdown than the TFT of the liquid crystal display section. If the pattern is easy, it is possible to make it difficult for the discharge breakdown of the TFT in the liquid crystal display portion to occur.

For example, the gate bus line corresponding to the dummy picture element pattern is different from the gate bus line of the liquid crystal display section in a structure having a meandering portion as shown in FIG. The gate bus line corresponding to the gate bus line having a separation portion in the liquid crystal display portion has a structure without the separation portion, thereby making it possible to reduce the discharge breakdown of the TFT in the liquid crystal display portion. .

[0087]

As described above, according to the method of manufacturing an active matrix substrate of the present invention, at least a part of the plurality of thin film transistors is used.
After forming a signal line, one end of which is a gate electrode of a thin film transistor, by forming a wiring body portion having a separation portion near an active region of the transistor by patterning a first wiring layer, the separation portion of the wiring body portion is formed. Is formed by patterning a second wiring layer different from the first wiring layer by connecting a wiring connection portion connecting the portions arranged with the interposition therebetween. Is performed in a state where the wiring main body portion is formed, and then, by forming the wiring connecting portion, by connecting the separating portion of the wiring main body portion, the destruction of the gate insulating film of the TFT at the time of ion implantation can be suppressed.

Therefore, in the liquid crystal display device with a built-in driver, the defect of the shift register including the TFT as a circuit element can be drastically reduced.

According to the method of manufacturing an active matrix substrate of the present invention, for at least a part of the plurality of thin film transistors, a signal wiring for inputting a clock signal from a clock line to a gate electrode of the thin film transistor is provided. after forming the wiring main body having a separating unit, in order to form a wiring connection portion that connects the portion disposed between across the separation portion of the wiring main body, not only the breakdown prevention of the gate insulating film By adjusting the length of the separation part and the resistance of the wiring body and the wiring connection part, the wiring resistance from each clock line to the shift register can be made uniform.

Therefore, there is an effect that a shift of the synchronization of the clock signal hardly occurs and the shift register does not malfunction.

Further, in the present invention, a gate bus line, part of which is a gate of a TFT of each picture element, is formed into a wiring main body having a separating portion for each picture element, and then the wiring bus section is formed. Since it is manufactured by forming a wiring connection part that connects the parts arranged with the separation part in between, it not only prevents breakage of the gate insulating film, but also uses a low-resistance material for the wiring connection part to make the gate bus The line can have low resistance, and signal delay can be prevented.

According to the method of manufacturing an active matrix substrate according to the present invention, for at least a part of the plurality of thin film transistors, a dummy signal wiring to which no signal is applied is connected to a gate electrode of the thin film transistor. Since the dummy signal wiring is formed into a structure having a continuous wiring pattern by patterning a predetermined wiring layer of the same layer material as the gate electrode, the signal wiring generated at the time of ion implantation after the formation of the signal wiring is charged. The breakdown of the gate insulating film due to the above can be concentrated on the dummy signal wiring by making the gate wiring length of the dummy signal wiring longer than the gate wiring length of the normal signal wiring. As a result, the breakdown of the gate insulating film in the normal signal wiring can be almost avoided.

[Brief description of the drawings]

FIG. 1 is a plan view showing a part of a shift register constituting a driver-integrated active matrix substrate of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining a driver-integrated active matrix substrate of the liquid crystal display device.
2A shows a cross-sectional structure of a picture element TFT constituting the active matrix substrate, and FIG. 2B shows a cross-sectional structure of a portion X in FIG.

FIG. 3 is a graph showing a yield of a shift register with respect to a length of a gate wiring connected to a TFT of the shift register.

FIG. 4 is a layout diagram showing an analog switch constituting a driver-integrated active matrix substrate of a liquid crystal display device according to a second embodiment of the present invention and a structure in the vicinity thereof;

FIG. 5 is a diagram for explaining an analog switch constituting a driver-integrated active matrix substrate of a liquid crystal display device according to a third embodiment of the present invention.
FIG. 5A is a layout diagram showing a structure of a TFT having a large width, which constitutes a conventional analog switch, and FIG. 5B is a view showing a structure of an analog switch according to the present embodiment.
It is a layout diagram showing FT.

FIG. 6 is an enlarged view showing a configuration of a portion corresponding to one picture element that constitutes a driver-integrated active matrix substrate of a liquid crystal display device according to a fourth embodiment of the present invention.

FIG. 7 is a sectional view taken along line d-d 'of FIG.

FIG. 8 is an enlarged view showing a configuration of a portion corresponding to one picture element constituting a driver-integrated active matrix substrate of a liquid crystal display device as a modification of the fourth embodiment of the present invention.

FIG. 9 is a diagram schematically showing a configuration of a driver-integrated liquid crystal display device.

FIG. 10 is a diagram showing a part of a source driver constituting an active matrix substrate of the driver-integrated liquid crystal display device.

FIG. 11 is a plan view showing a part of the configuration of a conventional source driver.

FIG. 12 is a layout diagram showing a CMOS inverter constituting a conventional source driver.

13 is a diagram showing a structure in a section taken along line ee ′ of FIG. 12 in the order of manufacturing steps;

FIG. 14 is a view for explaining an analog switch constituting a conventional driver-integrated liquid crystal display device, and FIG.
4 (a) is a layout diagram showing the structure of the analog switch and its vicinity, and FIG.
It is f 'line sectional drawing.

FIG. 15 is an enlarged view showing a configuration of a portion corresponding to one picture element which constitutes an active matrix substrate of a conventional driver-integrated liquid crystal display device.

FIG. 16 is a plan view showing another portion of the shift register constituting the active matrix substrate of the driver-integrated liquid crystal display device according to the first embodiment.

FIG. 17 is a diagram showing a part of a source driver constituting an active matrix substrate of a driver-integrated liquid crystal display device according to a fifth embodiment of the present invention.

FIG. 18 is a plan view showing a part of the configuration of the source driver according to the fifth embodiment.

[Explanation of symbols]

Reference Signs List 5 contact hole 11 low voltage side power supply line 12 high voltage side power supply line 13-16 clock line 17 N-channel TFT 17a, 18a transistor region 18 P-channel TFT 21 insulating substrate 22 gate drive circuit 23 source drive circuit 24 TFT array 25 picture element TFT 26 for picture element 27 additional capacity 48,127,128,129,227,527,52
9 signal wiring 103 electrode main body 107, 108, 109, 207, 301, 507, 5
09 wiring body 103a, 107a, 108a, 109a, 207a,
301a, 507a, 509a Separating part 113 Electrode connecting part 117, 118, 119, 217, 311, 312, 5
17,519 Wiring connection part 133 Analog switch 134 Video line 223 Gate electrode 321,322,421,422 Gate bus line 602 Semiconductor layer 602a Channel part 603 Gate insulating film 604 Gate electrode 605 First interlayer insulating film 606,609 Contact hole 607, 610 Metal layer 608 Second interlayer insulating film 611 Pixel electrode 727, 728, 729 Dummy signal wiring 728a Meandering portion

──────────────────────────────────────────────────続 き Continuation of front page (51) Int.Cl. ⁷ Identification symbol FI H01L 29/78 612B (56) References JP-A-1-289917 (JP, A) JP-A-4-280231 (JP, A) JP-A-1-283517 (JP, A) JP-A-3-175430 (JP, A) JP-A-3-293641 (JP, A) JP-A-62-252964 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G02F 1/1368 G09F 9/30 G09G 3/36

Claims (9)

(57) [Claims] 1. A method for manufacturing an active matrix substrate, comprising: a plurality of top gate thin film transistors formed on an insulating substrate; and a signal wiring for supplying a signal to a gate electrode of each thin film transistor. A step of forming a semiconductor layer and a gate insulating film patterned in a shape; a step of forming a wiring main body of a signal wiring having an isolation portion using the same layer material as the gate electrode; A method for manufacturing an active matrix substrate, comprising: a step of implanting ions into a layer; and a step of forming a wiring connection portion that connects portions sandwiching a separation portion of a wiring main body portion. 2. A method for manufacturing an active matrix substrate, comprising: a plurality of top-gate thin film transistors forming a shift register formed on an insulating substrate; and a signal line for supplying a clock signal from a clock line to each of the thin film transistors. Forming a semiconductor layer and a gate insulating film patterned in a predetermined shape on an insulating substrate; forming a wiring main body of a signal wiring having an isolation portion by using the same layer material as the gate electrode; A method for manufacturing an active matrix substrate, comprising: a step of performing ion implantation using a wiring main body as a mask; and a step of forming a wiring connecting part that connects portions sandwiching a separation part of the wiring main body. . 3. A plurality of top-gate thin film transistors forming an analog switch, which are formed on an insulating substrate, and are arranged so as to intersect with a video line, and output from a shift register is applied to a gate electrode of the thin film transistor as an analog switch. A method of manufacturing an active matrix substrate having a signal wiring to be supplied and a step of forming a semiconductor layer and a gate insulating film patterned into a predetermined shape on an insulating substrate, and forming an isolation portion by the same layer material as the gate electrode. A step of forming a wiring body of the signal wiring having; a step of performing ion implantation using the wiring body as a mask; and a step of forming a wiring connection section that connects portions sandwiching the separation section of the wiring body. A method for manufacturing an active matrix substrate, comprising: 4. A plurality of top-gate N-channel thin-film transistors and P-channel thin-film transistors constituting an inverter or a clocked inverter included in a shift register formed on an insulating substrate and connected to the inverter or the clocked inverter. And
What is claimed is: 1. A method for manufacturing an active matrix substrate having a signal wiring extending on one channel of one of N-channel and P-channel transistors constituting the semiconductor device, the semiconductor being patterned into a predetermined shape on an insulating substrate. A step of forming a layer and a gate insulating film; a step of forming a wiring body of a signal wiring having an isolation portion using the same layer material as the gate electrode; a step of performing ion implantation using the wiring body as a mask; Forming a wiring connection portion connecting portions sandwiching the separation portion of the main body, and a method of manufacturing an active matrix substrate. 5. A method for manufacturing an active matrix substrate having a picture element thin film transistor forming a display portion and a gate bus line for supplying a signal to a gate electrode of the thin film transistor on an insulating substrate, the method comprising: Forming a semiconductor layer and a gate insulating film patterned in a predetermined shape, forming a wiring main body of a gate bus line having an isolation portion by using the same layer material as the gate electrode; A method of manufacturing an active matrix substrate, comprising: a step of performing ion implantation as a mask; and a step of forming a wiring connection portion that connects signal wiring portions sandwiching a separation portion of a wiring main body portion. 6. The method of manufacturing an active matrix substrate according to claim 5, wherein the separation portion of the wiring main body is provided at each intersection of the source bus lines for each picture element. 7. The method for manufacturing an active matrix substrate according to claim 5, wherein the separation portion of the wiring body is provided for each picture element between adjacent source bus lines. 8. A method for manufacturing an active matrix substrate, wherein a plurality of thin film transistors are provided on an insulating substrate, and at least a part of the plurality of thin film transistors is divided into a plurality in the channel width direction. Forming a semiconductor layer and a gate insulating film patterned into a predetermined shape on an insulating substrate; forming an electrode body of a gate electrode having an isolation portion; and ion-implanting using the electrode body as a mask. And a step of forming an electrode connection portion connecting portions sandwiching the separation portion of the electrode body portion. A method of manufacturing an active matrix substrate, comprising: 9. A plurality of top-gate thin film transistors are provided on an insulating substrate, and a dummy signal wiring to which no signal is applied is connected to a gate electrode of at least a part of the plurality of thin film transistors. Wherein the dummy signal wiring is formed so as to have a continuous wiring pattern by patterning a predetermined wiring layer of the same layer material as the gate electrode. A method for manufacturing a matrix substrate.