JP3300023B2 - Signal input circuit and active matrix panel - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal input circuit having an input protection circuit for protecting an active matrix drive circuit and the like formed on an insulating substrate from an abnormal potential generated by static electricity or the like, and an active matrix having the same. The present invention relates to a liquid crystal display panel, and particularly to a wiring connection structure between a signal input line side and an input protection circuit side.

[0002]

2. Description of the Related Art When a semiconductor integrated circuit or the like is formed on the front side of an insulating substrate, unlike a case where an integrated circuit is formed on the front side of the semiconductor substrate, there is no common substrate that should have the same potential. It is necessary to provide an input protection circuit for protection from the like. For example, in an active matrix liquid crystal display panel, which is a typical flat display panel, a pixel matrix circuit for displaying the screen, a source line driving circuit and a gate line driving circuit are all provided on the surface of an insulating transparent substrate. Since it is formed on the side, the input protection circuit shown in FIG. 6 is conventionally provided. In the figure, the input protection circuit 70 corresponding to the first and second signal input lines 71 and 72 formed in parallel on the front surface side of the insulating transparent substrate is a part of the side position of the second signal input line 72. Is formed at a side position opposite to the position where the first signal input line 71 is formed.
The signal input line 71 is connected by a first abnormal potential lead line 73, and the second signal input line 72 and the input protection circuit 70 are connected by a second abnormal potential lead line 74. Here, the first and second abnormal potential extraction lines 73 and 74 are
In both cases, as shown in FIG.
The second signal input line 7 of the second abnormal potential extracting line 74 is conductively connected to the middle of the signal input lines 71 and 72 of the
The position of the conductive connection 72a to the second terminal 2 is closer to the output end 75 (the side in the signal direction indicated by arrow D) than the conductive connection position 71a of the first abnormal potential extraction line 73 to the first signal input line 71. It is in. For this reason, the first abnormal potential extraction line 73 is
At the intersection 76, the first abnormal potential extraction line 73 is connected to the signal input line 72 shown in FIG.
As shown in (b), since the second signal input lines 72 are formed on the surface of the interlayer insulating film 77 on the upper layer side, their insulating properties are ensured.

[0003]

However, in the conventional signal input circuit, the first abnormal potential extracting line 73 is not provided.
The intersection 76 between the second signal input line 74 and the second signal input line 74 forms an input terminal of the second signal input line 72 when viewed from the conductive connection position 72a between the second signal input line 72 and the second abnormal potential extraction line 74. 7
Since it is located on the side of 2b, there are the following problems. That is, a capacitor C ₂ is formed between the first abnormal potential extraction line 73 and the second signal input line 72 by the interlayer insulating film 77 at the intersection 76 thereof, and the capacitor C ₂ is parasitic on the wiring. Larger than the parasitic capacitance. Therefore, when an abnormal voltage is generated in the second signal input line 72 due to static electricity or the like,
Stored the charge in the capacitor C ₂ before the abnormal potential is absorbed by the input protection circuit 70, a state in which a high voltage is applied between the first abnormal voltage lead wire 73 and the second signal input line 72 Becomes Here, if the voltage between the first abnormal potential extraction line 73 and the second signal input line 72 exceeds the withstand voltage of the interlayer insulating film 77, the interlayer insulating film 77 at the intersection 76 is destroyed and the first And the second signal input line 72 is short-circuited, and the integrated circuit does not function.

[0004] In view of the above problems, the object of the present invention is to:
By improving the arrangement of the extraordinary potential lead line connecting the signal input line and the input protection circuit, the abnormal potential is absorbed and mitigated by the input protection circuit, and the extra potential potential line between the other signal input line and the extraordinary potential lead line An object of the present invention is to realize a signal input circuit and an active matrix display panel capable of improving reliability by being transmitted to an intersection.

[0005]

In order to solve the above-mentioned problems, a signal input circuit according to the present invention comprises a first signal input line and a second signal input line formed in parallel on a substrate surface side. It is formed at a position opposite to the formation position of the first signal input line among the side positions of the line, and protects a circuit at an output end side of the signal supplied to the first and second signal input lines. an input protection circuit, respectively connected conductively via an interlayer insulating film in the first and second signal input line, the signal input line and the input protection times
And first and second lead lines for conducting connection between the first and second paths, respectively .
That the second signal input line intersects the second signal input line at the output end side of the second signal input line with respect to the position where the second signal input line is conductively connected to the second signal input line.
Features .

Here, the first and second signal input lines are
Thin film transistor in drive circuit of active matrix panel
It is conductively connected to the gate of the transistor. And
The active matrix panel has a signal input circuit according to the above configuration.
And a drive conductively connected to the first and second signal input lines.
A moving circuit and a pixel matrix are formed on a substrate .

Note that the first and second signal input lines in the present invention include not only two signal input lines but also three or more signal input lines,
In the case where one signal input line has the configuration of the first and second signal input lines, any one of the three or more signal input lines is connected to another signal input line by the above-described method. And the first and second signal input lines.

[0008]

In the signal input circuit and the active matrix panel according to the present invention provided with the above means, the first signal input line and the second signal input line formed in parallel on the surface of the substrate have an abnormal potential due to static electricity or the like. Is supplied to the input protection circuit via the first or second lead wire, the abnormal potential is not output from the output terminal. Here, the first lead line is located at a position where the second lead line is conductively connected to the second signal input line .
Because remote intersecting the second signal input line at the output end of the second signal input line, when viewed from the second signal output end, a first lead line and the second signal input line The input protection circuit is conductively connected to the preceding stage side via the second lead line as compared with the intersection of. Therefore, the abnormal potential supplied to the second signal input line is first sent out to the output terminal side in a state of being absorbed and reduced in the input protection circuit. For this reason, even if a capacitor is formed at the intersection of the second signal input line and the first lead line, no high voltage is generated between the second signal input line and the first lead line. Therefore, since the interlayer insulating film at the intersection is not damaged, these input lines are not short-circuited, and the reliability of the signal input circuit and the active matrix panel is improved.

[0009]

Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a configuration diagram showing a configuration of a signal input circuit according to a first embodiment of the present invention, FIG. 2A is a plan view showing an arrangement of the signal input line and an abnormal potential lead line, and FIG. FIG. 5B is a cross-sectional view taken along line VV ′ of FIG.

Since the signal input circuit of the present embodiment is formed on an active matrix liquid crystal display panel, before describing the configuration of the signal input circuit, the active matrix liquid crystal display will be described with reference to FIGS. The configuration of the display panel will be described.

FIG. 3 is a block diagram of an active matrix liquid crystal display panel having the signal input circuit of this embodiment, and FIG. 4 is a circuit diagram of the source line driving circuit.

In the active matrix liquid crystal display panel 10 shown in FIG. 3 and FIG.
2. Source line drive circuit 12 and gate line drive circuit 21
Are formed on an insulating transparent substrate 11 (insulating substrate). Among them, a source line driving circuit 12 includes a shift register 13, a sample and hold circuit 17, and video signal lines 14, 15, and 16, , The gate line driving circuit 21 includes a shift register 20 and a buffer circuit 23 as necessary. The pixel matrix 22
, A plurality of source lines 26, 27, 28,... Connected to the source line driving circuit 12, a plurality of gate lines 24, 25,. , And a plurality of pixels 32, 33,... Formed at the intersections of the source lines. Each pixel 32, 33,. Further, a clock signal line 34 for inputting a clock signal to the shift register 13 is disposed on the side of the source line driving circuit 12, while a clock signal is supplied to the shift register 20 on the side of the gate line driving circuit 21. A clock signal line 37 to which the signal CKA is to be input is arranged. Reference numerals 35 and 36 denote start signal lines for inputting start signals to the source line drive circuit 12 and the gate line drive circuit 21. Here, as shown in FIG. 4, the shift register 13 has one inverter 13a per bit.
And two clocked inverters 13b and 13c. Among them, the inverter 13a has a CMOS structure composed of a p-type TFT and an n-type TFT, while the clocked inverters 13b and 13c have two p-type TFTs. TF
It is composed of T and two n-type TFTs. Also,
Each analog switch 17a of the sample hold circuit 17
Is also formed of n-type TFTs, and its buffer circuit is also formed of inverter circuits 17b and 17c formed of complementary TFTs. Reference numeral 18 denotes a positive power supply line for driving each circuit section of the active matrix liquid crystal display panel 10, and its potential is maintained at _Vdd , while 19 is its negative power supply line. Is held at V _ss . Here, the active matrix liquid crystal display panel 10
The liquid crystal cell 30 is formed in such a state that a counter substrate (not shown) faces the transparent substrate 11, and liquid crystal sealed between them is used.

In the active matrix liquid crystal display panel 10 having such a configuration, since each circuit portion is formed on the front side of the insulating transparent substrate 11, a semiconductor having an integrated circuit formed on the front side of the semiconductor silicon substrate is formed. Unlike the device, there is no conductive common substrate having the same potential. For this reason,
During a manufacturing process such as a dicing process or after completion, the circuit is liable to be damaged by the influence of static electricity or the like.

Therefore, in the active matrix liquid crystal display panel 10 of the present embodiment, the transparent substrate 11
As shown in FIG. 1, the signal input circuit 1 includes an input protection circuit 2 together with the pixel matrix 22 (pixel matrix circuit), the source line drive circuit 12, the gate line drive circuit 21, and the like. Here, the signal input circuit 1 is provided in any one of the gate input circuits formed of TFTs in the source line driving circuit 12 shown in FIG.

In FIG. 1, a signal input circuit 1 outputs an abnormal potential supplied to a first signal input line 3 and a second signal input line 4 which are formed in parallel on the front surface of a transparent substrate 11 to an output terminal side ( The input protection circuit 2 for protecting the main circuit 5 (the gate input circuit of the source line drive circuit 12) on the signal direction side indicated by the arrow A is the first signal of the side position of the second signal input line 4. The first input protection circuit 2a and the first signal input line 3 of the input protection circuit 2 are formed at a side position opposite to the position where the input line 3 is formed. 6, the second input protection circuit 2b and the second signal input line 4 are connected by a second abnormal potential extraction line 7. Here, the first input protection circuit 2a and the second input protection circuit 2b are connected to the positive power supply line 18 of the active matrix liquid crystal display panel 10, the first and second abnormal signal input lines 6, 7, respectively. A p-type TFT 201 whose source and drain are conductively connected to each other, and n whose source and drain are conductively connected to the negative power supply line 19 and the first and second abnormal signal input lines 6 and 7 of the active matrix liquid crystal display panel 10. And the TFT 202. Also, a p-type TFT 2
01 is electrically connected to the positive power supply line 18, and the n-type T
The gate of the FT is conductively connected to the negative power supply line 19.

Here, the first abnormal potential extraction line 6 and the first abnormal potential
2A, the conductive connection position 3a with the signal input line 3 is compared to the conductive connection position 4a of the second abnormal potential extraction line 7 with the second signal input line 4 as shown in FIG. The first abnormal potential extraction line 3 is located on the output end side of the second signal input line 4a.
Crosses the second signal input line 4 at the output end side of the second signal input line 4 as compared with the conductive connection position 4a of the second abnormal potential extraction line 7 to the second signal input line 4. ing. For this reason,
When viewed from the input terminal 4b side of the second signal input line 4, the second
The input protection circuit 2b is connected to the second signal input line 4 at the preceding stage (on the side of the input terminal 4b) as compared with the intersection 8 of the second signal input line 4 and the first abnormal potential extraction line 6. Conductive connection.
Note that the first abnormal potential lead line 6 is connected to the second signal input line 4
However, the first and second abnormal potential extraction lines 6 and 7 are formed on the surface of the interlayer insulating film on the upper layer side of the first and second signal input lines 3 and 4, as shown in FIG. As shown in b), the first abnormal potential lead line 6 and the second signal input line 4 are interposed at the intersection 8 with the interlayer insulating film 9 interposed therebetween, so that their insulation is ensured. However, intersection 8
As shown in FIG. 1, between the first abnormal potential extraction line 6 and the second signal input line 4,
A state where the capacity C ₁ is parasitic.

The operation of the input protection circuit 2 in the signal input circuit 1 having such a configuration will be described with reference to FIGS. 5 (a), 5 (b) and 5 (c), taking the operation of the second input protection circuit 2b as an example. ).

FIG. 5A is a circuit diagram showing the configuration of the second input protection circuit 2b, and FIG. 5B is a diagram showing the p-type TFT 201.
FIG. 5C is a graph showing the relationship between the gate-source voltage V _gs and the source-drain current _Isd .
FIG. 7 is a graph showing a relationship between a gate-source voltage V _gs and a drain-source current I _{ds of} T202. In the following description, the positive power supply potential of the positive power supply line 18 is V _dd , the negative power supply potential of the negative power supply line 19 is V _ss , and the second signal input line 4
The potential second through abnormal voltage lead lines 7 second input potential drawn in the input protection circuit 2b of the V _in. The input stage of the main circuit 5 shown in FIG.
This is a gate input circuit of the source line drive circuit 12 including the inverter 5a constituted by the TFT having the S structure.

[0020] First of all, V _ss ≦ V _in ≦ V in the case of a _dd, the potential V _gs between the gate and the source in TFT201 of the p-type 0
V, its drain-to-source voltage V _ds (V _in -V _dd)
v, and V _ds ≦ 0. Therefore, the p-type TFT 20
1 functions as a resistor, along a line shown by the solid line 41 in FIG. 3 (b), the source-drain current I _sd flows corresponding to the input voltage V _in. On the other hand, the potential V _gs between the gate and the source in the n-type TFT 202 is 0 V,
The source-to-source voltage V _ds is (V _in −V _ss ) v, and V _ds ≧ 0
It is. Therefore, TFT 202 of n-type also functions as a resistor, along a line indicated by the solid line 42 in FIG. 3 (c), the source-drain current I _sd corresponding to the input voltage V _in is generated.

On the other hand, when V _dd <V _in , that is, when an abnormal potential higher than the positive power supply potential V _dd of the positive power supply line 18 is applied to the second signal input line 4, Is that the gate-source potential V _gs of the p-type TFT 201 is (V _dd −V _in ) v, V _gs <0 V, the drain-source voltage V _ds is (V _dd −V _in ) v, V _ds <0. Therefore, as the input potential V _in (abnormal potential) increases, the gate-source potential V _gs and the drain-source voltage V _{ds shift} to the negative side, and the characteristic shown by the solid line 43 in FIG. The p-type TFT 201 is turned on. In this case, the characteristics of the n-type TFT 202 remain as shown by the solid line 42 in FIG. Therefore, when an abnormal potential higher than the positive power supply potential _Vdd of the positive power supply line 18 is applied to the second signal input line 4 due to static electricity or the like,
A current passes through the positive power supply line 18 via the p-type TFT 201.

On the other hand, when V _in <V _ss ,
When an abnormal potential lower than the negative power supply potential V _ss of the negative power supply line 19 is applied to the signal input line 4 of
The gate-source potential V _{gs at} 202 is (V _ss −V
_in ) v, V _gs > 0 V, drain-source voltage V
_ds is a (V _ss -V _in) v, is a V _ds> 0. Therefore, as the input potential V _in (abnormal potential) is lower, the gate-source potential V _gs and the drain-source voltage V _ds are _shifted to the plus side, and the characteristic shown by the solid line 44 in FIG. The n-type TFT 202 is turned on. In this case, the p-type TFT 201 keeps the characteristics indicated by the solid line 41 in FIG. Therefore, when an abnormal potential lower than the negative power supply potential V _ss of the negative power supply line 19 is supplied to the second signal input line 4, a current is supplied to the negative power supply line 19 via the n-type TFT 202. Passes.

In this manner, the main circuit 5 is protected by the second input protection circuit 2b from an abnormal potential generated on the second signal input line 4 due to static electricity or the like. Similarly, it is protected from the abnormal potential generated on the first signal input line 3.

In the active matrix liquid crystal display panel 10 including the signal input circuit 1 of the present embodiment, the first
Of the second signal input line 2 at the output end side of the second signal input line 2 as compared with the conductive connection position 4a of the second abnormal potential extraction line 7 to the second signal input line 4 The second input protection circuit 2b includes the second signal input line 4 and the first abnormal potential extraction line when viewed from the input terminal 4b side of the second signal input line 4 because it intersects with the line 4. 6 is located before the capacitor C ₁ parasitic at the intersection 8 with the capacitor 6. Therefore, even when an abnormal potential is supplied to the second signal input line 4 due to static electricity or the like, the abnormal potential is reliably absorbed and mitigated by the second input protection circuit 2b. At the intersection 4a between the signal input line 4 and the first abnormal signal input line 6. Therefore, even if the capacitance C ₁ is formed at the intersection 8, the voltage generated between the second signal input line 4 and the first abnormal potential extracting line 6 is low, so that the interlayer insulating film at the intersection 8 is not formed. 9 is not damaged. Therefore, due to the abnormal voltage, the second signal input line 4
And the first abnormal potential extraction line 6 do not short-circuit,
The reliability of the signal input circuit 1 and the active matrix liquid crystal display panel 10 including the same is improved.

In this embodiment, a signal input circuit having two rows of signal input lines has been described. However, the present invention is not limited to this, and can be applied to a signal input circuit having three or more rows of signal input lines. In this case, for two of the signal input lines, the signal input lines on the input protection circuit side are connected to the second line.
And the other signal input line on the other side as a first signal input line, and the first and first abnormal potential extraction lines having the above-described configuration are arranged respectively. Further, the configurations of the input protection circuit side and the main circuit side are not limited.

[0026]

As described above, in the input protection circuit according to the present invention and the active matrix panel provided with the same, the first lead line is electrically connected to the second signal input line of the second lead line. characterized in that intersects a second signal input line at the output end of the second signal input line than the position. Therefore, according to the present invention, when viewed from the input end of the second signal input line, the input protection circuit is located at a stage preceding the intersection of the first lead line and the second signal input line. ,
The abnormal potential supplied to the second signal input line due to static electricity or the like to the input end side is absorbed by the input protection circuit.
Reach the intersection in a relaxed state. Therefore, even if a capacitance is formed at the intersection, the voltage generated between the second signal input line and the first lead line is low, and the interlayer insulating film at the intersection is not damaged. Therefore, the second signal input line and the first lead line are not short-circuited, and the effect of improving the reliability of the input protection circuit and the active matrix panel including the same is exhibited.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a configuration of an input protection circuit according to a first embodiment of the present invention.

2A is a plan view showing an arrangement of a signal input line of the input protection circuit shown in FIG. 1 and an abnormal potential extracting line for the protection circuit, and FIG. 2B is a line V-V 'of FIG. 2A. FIG.

3 is a block diagram showing a configuration of an active matrix liquid crystal display panel employing the input protection circuit shown in FIG.

FIG. 4 is a circuit diagram showing a configuration of a source line driving circuit of the active matrix liquid crystal display panel shown in FIG.

5A is a circuit diagram showing a configuration of the input protection circuit shown in FIG. 1, and FIG. 5B is a relationship between a gate-source voltage V _gs and a source-drain current _Isd of the p-type TFT. And (c) is a graph showing the relationship between the gate-source voltage V _gs and the drain-source current I _ds of the n-type TFT.

FIG. 6 is a configuration diagram showing a configuration of a conventional input protection circuit.

7A is a plan view showing an arrangement of a signal input line of the input protection circuit shown in FIG. 6 and an abnormal potential extraction line for the protection circuit, and FIG. 7B is a VI-VI 'line of FIG. 7A. FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Signal input circuit 2,70 ... Input protection circuit 2a ... First input protection circuit 2b ... Second input protection circuit 3,71 ... First signal input line 4, 72 ... second signal input line 5 ... main circuit 6, 74 ... first abnormal potential lead line 7, 75 ... second abnormal potential lead line 8, 76 ... intersection 9, 77 ... interlayer insulating film 10 ... active matrix liquid crystal display panel 11 ... transparent substrate 12 ... source line drive circuit 13, 20 ... shift register 17 ... sample hold circuit 18 ... Positive power supply line 19 Negative power supply line 21 Gate line driving circuit 22 Pixel matrix 30 Liquid crystal cell 34 Clock signal line 201 P-type TFT (p 202) n-type TFT n-type thin film transistor)

Claims (3)

(57) [Claims] 1. A first and a second signal input line formed in parallel on a substrate surface side, and a formation position of the first signal input line among lateral positions of the second signal input line. An input protection circuit formed at an opposite position to protect a circuit on an output end side of a signal supplied to the first and second signal input lines; and an interlayer insulating circuit provided between the first and second signal input lines. respectively connected conductively through the membrane, said input and said signal input line
First and second lead lines for conductively connecting the protection circuit to the protection circuit, respectively , wherein the first lead line is at a position higher than a position at which the second lead line is conductively connected to the second signal input line. Crossing the second signal input line at the output end side of the second signal input line
Signal input circuit characterized by comprising. Wherein said first and second signal input line, A
Claims, characterized in that the conductive connection to the gate of the thin film tiger <br/> Njisuta in the driving circuit of the active matrix panel
Item 2. The signal input circuit according to Item 1 . 3. The signal input according to claim 1 or claim 2.
Power circuit and conductively connected to said first and second signal input lines
Drive circuit and a pixel matrix are formed on a substrate.
An active matrix panel, comprising: