JP3395598B2 - Active matrix substrate manufacturing method and liquid crystal display panel - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an active matrix substrate having a built-in driving circuit, an active matrix substrate manufactured by this manufacturing method, a liquid crystal display panel,
And a projection type liquid crystal display device. More specifically, the present invention relates to a technique for protecting a drive circuit and the like from static electricity generated in the process of manufacturing an active matrix substrate and charges accumulated on the surface of an insulating substrate.

[0002]

2. Description of the Related Art Among active matrix substrates used in liquid crystal display panels, those having a built-in drive circuit include a plurality of scanning lines 20 and a plurality of data lines arranged on an insulating substrate 10, as shown in FIG. A plurality of pixels 40 are formed corresponding to the intersections with the line 30.
The area in which is formed is the pixel portion 11. As shown in FIG. 3, a thin film transistor (hereinafter, referred to as a TFT) 50 for pixel switching, which is connected to the scanning line 20 and the data line 30, is formed in each pixel 40. In addition, a data line driving circuit unit 60 that supplies an image signal to each of the plurality of data lines 30 and a scanning signal to each of the plurality of scanning lines 20 are provided in an area outside the pixel unit 11 on the insulating substrate 10. The scanning line drive circuit unit 70 is configured.

In the active matrix substrate having such a structure, the TFT is formed by using a semiconductor process. When these steps are performed, since the insulating substrate 10 is used as the active matrix substrate, defects due to static electricity or the like are likely to occur. Therefore, conventionally, the insulating substrate 10 is formed when ion-implanting is performed using the gate electrode as a mask by forming the short-circuit wiring 90 that electrically connects to each scanning line 20 also using the step of forming the scanning line 20. The electric charges and static electricity accumulated on the surface of the substrate are diffused to the outer peripheral side of the substrate through the wiring 90 for short circuit so that a sudden excess current does not flow to the TFT 50 or the like through the scanning line 20.

However, since the short-circuit wiring 90 is not necessary after the manufacturing process of the active matrix substrate is completed, the applicant of the present application also uses the process in the middle thereof for the short-circuit wiring 90.
The cutting holes 8 are formed on the
A method has been proposed in which a short circuit wiring 90 is cut at a predetermined position via a wire to separate the short circuit wiring from the scanning line (see Japanese Patent Publication No. 8-14667).

[0005]

However, in the active matrix substrate, the data line driving circuit 60 and the scanning line driving circuit 70 are also desired to be protected from static electricity, but in the conventional active matrix substrate, such measures are taken. Is not applied sufficiently.

In view of such a problem, an object of the present invention is to provide a method of manufacturing an active matrix substrate capable of protecting the data line driving circuit and the scanning line driving circuit from static electricity, etc., and the active matrix manufactured by this manufacturing method. An object is to provide a matrix substrate, a liquid crystal display panel, and a projection type liquid crystal display device.

[0007]

In order to solve the above problems, according to the present invention, a pixel portion including a plurality of scanning lines, a plurality of data lines, and a thin film transistor for pixel switching connected to the data lines and the scanning lines. A data side driving circuit and a scanning line driving circuit respectively connected to the data line and the scanning line, and for supplying a plurality of signals necessary for driving the scanning line driving circuit and the data line driving circuit. A plurality of signal wirings and a plurality of terminals connected to the signal wirings are provided over a substrate, and the thin film transistor is formed in a gate electrode formed at the same time as the scan line and a first interlayer insulating film. A source region electrically connected to the data line through a first contact hole, a first interlayer insulating film, and a second interlayer insulating film on an upper layer side of the first interlayer insulating film. In the production method of the active matrix substrate made the second pixel electrode via a contact hole and a drain region electrically connected,
Forming a first short-circuit wiring electrically connected to each of the signal wirings together with the scanning line and the gate electrode; and forming a first cutting hole on the first short-circuit wiring. And a step of cutting the first short circuit wiring through the first cutting hole.

In the present invention, the signal wirings respectively routed from the plurality of terminals in order to supply the plurality of signals necessary for driving the data line driving circuit and the scanning line driving circuit are connected to the first short circuit wirings. Each step is performed in a state of being electrically connected by. Therefore, even if static electricity is generated or electric charges are accumulated on the surface of the insulating substrate, the electric charges are diffused to the outer peripheral side of the substrate through the first short-circuit wiring, so that an excessive current causes an excess current. It does not suddenly flow into the drive circuit. Therefore, the data line driving circuit and the scanning line driving circuit can be protected. Moreover, contact holes are formed, patterned, and etched in the steps of forming TFTs, forming various wirings, and forming terminals. Therefore, the steps of forming cutting holes and the cutting are performed by using these steps also. A step of cutting the short circuit wiring through the use hole can be performed.

In the present invention, in the step of forming the first short-circuit wiring, the first short-circuit wiring is electrically connected only to the signal wiring located on the terminal side of the electrostatic protection circuit in the signal wiring. It is preferable to make a physical connection. According to this structure, the static electricity that has entered from the position where the first short circuit wiring is cut off is absorbed by the electrostatic protection circuit and does not reach the drive circuit.

In the present invention, in order to separate the scanning lines, after forming the second shorting lines electrically connected to each of the scanning lines in the step of forming the first shorting lines. Performing a step of forming a second cutting hole at a position where the second short circuit wiring is to be cut, and a step of cutting the second short circuit wiring through the second cutting hole. Therefore, it is preferable to prevent an excessive current from suddenly flowing to the scanning line and protect the scanning line and the pixel portion.

In the present invention, a third shorting wiring that intersects with each of the data lines is formed in the step of forming the first shorting wiring, thereby forming the third shorting wiring on the first interlayer insulating film. Through the third contact hole
Electrically connecting the short-circuiting wire of the third embodiment to the data line, and then separating the third data line from each other.
By forming a third cutting hole at a position where the short circuit wiring is to be cut and cutting the third short circuit wiring through the third cutting hole. It is preferable to prevent a sudden current from flowing into the data line and protect the data line, the sample hold circuit, and the pixel portion.

In the present invention, it is preferable that the step of forming the cutting hole also serves as the step of forming the contact hole.

In the present invention, it is preferable that the step of cutting the short-circuit wiring is performed also as an etching step of removing the second interlayer insulating film formed on the surface of the terminal. If the short circuit wiring is cut in a process close to such a final process, the drive circuit and the pixel portion can be effectively protected from static electricity generated in the process performed before that.

In any case, in the step of forming the cut hole, it is preferable to perform wet etching when the surface of the short circuit wiring is finally exposed. In addition, it is preferable that at least wet etching is performed in the step of cutting the short circuit wiring so that no conductive material remains in the cutting hole.

In the present invention, a static electricity countermeasure wiring electrically connected to the short-circuit wiring is formed on the outer peripheral side of the active matrix substrate, and the static electricity countermeasure wiring is formed by a large number of the active matrix substrates. On the mother substrate, the static electricity countermeasure wirings of the adjacent active matrix substrates are electrically connected to each other, and when each active matrix substrate is cut out from the mother substrate, the static electricity countermeasures of the adjacent active matrix substrates are taken. It is preferable that the electrical connection between the wirings is cut off.

A liquid crystal display panel is constructed by using the active matrix substrate to which the present invention is applied, and this liquid crystal display panel is used as, for example, a light valve, and light emitted from a light source section is optically modulated by the liquid crystal display panel. Thus, a projection type liquid crystal display device is constructed in which the modulated light is enlarged and projected on the projection surface by the projection optical means. In such a projection type liquid crystal display device, a display defect tends to be noticed by a user because an image is enlarged and projected. However, the liquid crystal display panel to which the present invention is applied causes a display defect due to electrostatic breakdown. Since it is difficult to do so, it is suitable for constructing a projection type liquid crystal display device.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described with reference to the drawings.

[First Embodiment] (Overall Structure of Active Matrix Substrate) FIG. 1 is a block diagram schematically showing the structure of an active matrix substrate with a built-in drive circuit used in a liquid crystal display panel.
FIG. 4 is an enlarged plan view showing a corner portion of a pixel portion of this active matrix substrate.

As shown in FIGS. 1 and 2, in a drive circuit built-in active matrix substrate AM used in the liquid crystal display panel of the present embodiment, a plurality of scanning lines 20 and a plurality of scanning lines 20 intersecting each other are provided on an insulating substrate 10. Pixels 40 are formed in a matrix by the data lines 30. Scan line 2
0 is formed of a doped silicon film, and the data line 30 is formed of a metal film such as an aluminum film or an alloy film. The area where these pixels 40 are formed is the pixel portion 1
1 (screen display area).

A data line driving circuit section 60 for supplying an image signal to each of the plurality of data lines 30 is formed in the outer region (peripheral portion) of the pixel section 11 on the insulating substrate 10. In addition, at both ends of the scanning line 20,
A scanning line drive circuit unit 70 that supplies a scanning signal for pixel selection to each scanning line 20 is configured.

The data line drive circuit section 60 includes an X side shift register circuit and a TF as an analog switch which operates based on a signal output from the X side shift register circuit.
A sample hold circuit S / H including T, six image signal lines video corresponding to the respective image signals VD1 to VD6 developed in six phases, and the like are configured. In this example,
In the data line driving circuit 60, the X-side shift register circuit is composed of four phases, and a start signal DX, clock signals CLX1 to CLX4, and inverted clock signals CLX1 to CLX4 thereof are externally supplied via terminals. The data line drive circuit 60 is driven by these signals supplied to the X side shift register circuit. Therefore, in the sample hold circuit S / H, each TFT operates based on the signal output from the X side shift register circuit,
Image signal VD supplied via the image signal line video
1 to VD6 can be taken into the data line 30 at a predetermined timing and supplied to each pixel 40. On the other hand, the scanning line driving circuit unit 70 is supplied with a start signal DY, a clock signal CLY, and its inverted clock signal CLY bar from the outside through a terminal, and these signals drive the scanning line driving circuit 70.

In the active matrix substrate AM of this embodiment, the constant power supplies VDDX, VSSX, V are provided on the side of the insulating substrate 10 on the side of the data line drive circuit 60.
DDY, VSSY, modulated image signals (image signals VD1 to VD
D6), a large number of terminals 80, 81, 82 ... Composed of a metal film such as an aluminum film to which various drive signals are input, a metal silicide film, or a conductive film such as an ITO film are formed. , 81, 82 ...
A plurality of signal wirings 72, 73 made of a low resistance metal film such as an aluminum film or a metal silicide film for driving the scanning line driving circuit 60 and the data line driving circuit 70 are respectively routed. Further, electrostatic protection circuits 65 and 75, which will be described later, are formed at intermediate positions of the signal wirings 72 and 73. In the active matrix substrate AM and the counter substrate (not shown), a counter electrode potential LCCOM input from the outside is supplied to the counter substrate by a vertical conducting material.

As can be seen from FIGS. 2 and 3, the pixel 4
At 0, a pixel switching TFT 50 connected to the scanning line 20 and the data line 30 is formed. Also,
A capacitance line 71 is also formed toward each pixel 40. T
The FT 50, as will be described later with reference to FIG.
Source regions 1b and 1d in which the gate electrode 3a formed at the same time as the scanning line 20 and the data line 30 are electrically connected to each other through the first contact hole 5a of the first interlayer insulating film 4.
And the first interlayer insulating film 4 and the first interlayer insulating film 4
Drain regions 1c and 1e electrically connected to the pixel electrode 9a through a second contact hole 8a formed in the second interlayer insulating film 7 on the upper layer side.

As shown in FIGS. 4 and 12B, the terminals 6c (terminals 80, 81, 82 ...) Are pads exposed at the opening 12 of the second interlayer insulating film 7, Connection with the terminal is possible. These terminals 6c are formed in the upper layer of the first interlayer insulating film 4. On the other hand, the short-circuit wiring 3b, which will be described later, is formed simultaneously with the scanning line 20 in the lower layer of the first interlayer insulating film 4, so that the electrical connection between the terminal lower sheet film 3c and the terminal 6c, which is a part of the short-circuit wiring 3b, is reduced. Electrical connection is made by a contact hole 5c formed in the first interlayer insulating film 4.

In the active matrix substrate AM having such a structure, the TFT 50, various wirings, the scanning line drive circuit section 70, and the data line drive circuit 6 are provided.
0 is formed using a semiconductor process. here,
Since the insulating substrate 10 is used as the active matrix substrate AM, defects due to static electricity or the like are likely to occur, and therefore the following countermeasures against static electricity are taken in this embodiment.

First, in the present embodiment, as shown in FIG. 1, the first short circuit for electrically connecting to all the signal wirings 72 and 73 is performed by also using the step of forming the scanning line 20 and the gate electrode of the TFT 50. Wiring 91 is formed. Further, the second short-circuit wiring 92 electrically connected to all the scanning lines 20 is formed by also using the step of forming the scanning lines 20 and the gate electrodes of the TFTs 50. Furthermore, scan line 2
The third short-circuit wiring 93 electrically connected to all the data lines 30 is formed by also using the step of forming 0 and the gate electrode of the TFT 50. Where the first, second,
The third short-circuit wirings 91, 92, 93 are only polysilicon films patterned together with the scanning lines 20 and the gate electrodes of the TFTs 50. Therefore, the first
The third short circuit wirings 91 and 93 are the signal wirings 72,
Since it is located between layers different from 73 and the data line 30, as shown in FIG. 5, the first and third short circuit wirings 91 and 93, the signal wirings 72 and 73, and the data line 30 are the same as those described above. Electrical connection is made via a third contact hole 403 formed in the first interlayer insulating film 4.

In this way, the first, second and third
The short-circuiting wirings 91, 92, 93 are respectively connected to the signal wiring 7
2, 73, the scanning line 20, and the data line 30 are connected to the first, second, and third charges even if static electricity or the like is generated in a process performed after forming these wiring structures. 3 is diffused to the outer peripheral side of the substrate through the short-circuit wirings 91, 92, 93, and a sudden excess current is generated by the scanning line 2.
0, the pixel section 11, the scanning line drive circuit section 70, the sample hold circuit S / H, and the data line drive circuit 60 do not flow, so all these parts can be protected from static electricity.

As shown in FIG. 6, a plurality of active matrix substrates AM may be formed on a mother substrate MM, and each active matrix substrate AM may be cut out from this mother substrate MM. In this case, as shown in a magnified view of the area A in FIG. 6, first, second, and third short-circuit wirings 91, 92, 93 are provided on the outer peripheral side of each active matrix substrate AM. There is a case where a static electricity countermeasure wiring 99 that is electrically connected is provided, and static electricity charges may be diffused to the outer periphery of the substrate. In this case, the anti-static wiring 99 electrically connected to the first, second, and third short-circuit wirings 91, 92, 93 is connected to the final process between the adjacent active matrix substrates AM. The active matrix substrates AM are separated when the mother substrate MM is cut. With this configuration, the static electricity countermeasure wiring 99 can be arranged in a state of being dispersed in a wide range, so that the concentration of electric charges can be prevented and the effect is further improved.

However, the first, second, and third short-circuit wirings 91, 92, 93 are connected to the active matrix substrate AM.
Since it is not necessary after the manufacturing process of the
At the marked position, as will be described later with reference to FIGS. 9 to 12, a cutting hole 8b is formed in the first interlayer insulating film 4 and the second interlayer insulating film 7 by using an intermediate process. Then, the short circuit wiring 3b (first, second, and third short circuit wirings 91, 92, 93) is cut through the cutting holes 8b by etching. For this reason, the first, second, and third short-circuit wires 9 are provided halfway through the manufacturing process.
1, 92, and 93 are connected to the signal wirings 72 and 73, the scanning line 20, and the data line 30, respectively, but after etching through the cutting holes 8b, the signal wirings 72, 73, and
Each of the scan line 20 and the data line 30 will be electrically separated. Thereby, the electrical characteristics can be inspected in the state of the mother substrate MM before the active matrix substrate AM is cut.

The electrostatic protection circuits 65 and 7 shown in FIG.
Various circuits can be used as 5, but in the one shown in FIG. 8, a protective resistor 66, a P-channel type TFT 67 and an N-channel type TFT 68 arranged in a push-pull arrangement are used, and the respective positive power supplies VDD and A diode is formed between it and the negative power supply VSS. In the present embodiment, the first
It is always between the terminal 80 (or 81, 82) and the protective resistor 66 that the short-circuiting wiring 91 of FIG. 1 is connected to the signal wiring 72 (or 73), whereby the terminal 80 (or 81, 82) is connected. , Or static electricity that has entered from the first short circuit wiring 91A, is protected by the protection resistor 66 and the static electricity protection circuit 65.
(Or 75) does not reach the data line driving circuit 60 and the scanning line driving circuit 70. With such a configuration, the static electricity is protected against static electricity 65 (or 7).
5), the data line driving circuit 60 and the scanning line driving circuit 70 can be reliably protected.

(Manufacturing Method of Active Matrix Substrate AM) A method of manufacturing the active matrix substrate AM while taking such electrostatic protection measures will be described with reference to FIGS.
2 will be described. These drawings are process cross-sectional views showing the method for manufacturing the active matrix substrate AM of the present embodiment, and in each of the drawings, the left side thereof is taken along the line AA ′ in FIG. 2 (the cross section of the pixel TFT section). ), A cross section taken along the line BB 'in FIG. 5B (an antistatic wiring section where the short-circuit wiring is cut ("x" in FIG. 1).
The cross section (marked portion)) and the right side portion are C- in FIG.
The cross-section along the line C '(the cross-section of the terminal portion where the terminals 80, 81, 82 ... Are formed) is shown.

First, as shown in FIG. 9 (A), a base protective film formed directly on the surface of a glass substrate, for example, a transparent insulating substrate 10 made of alkali-free glass or quartz, or formed on the surface of the insulating substrate 10 ( (Not shown), and has a thickness of about 200 angstroms to about 2000 angstroms, preferably about 1 angstroms by a low pressure CVD method or the like.
After forming the semiconductor film 1 made of a polysilicon film having a thickness of 000 angstroms, as shown in FIG. 9B, the semiconductor film 1 is patterned by using a photolithography technique to form an island-shaped semiconductor film 1a on the pixel TFT section side. (Active layer) is formed. On the other hand, the semiconductor film 1 is completely removed on the side of the static electricity countermeasure wiring portion and the terminal portion. The formation of the semiconductor film is performed by depositing an amorphous silicon film and then
1 to 72 hours at a temperature of ℃ to 700 ℃, preferably 4
Thermal annealing is performed for 6 hours to 6 hours to form a polysilicon film, or after depositing a polysilicon film, silicon is implanted and amorphized, and then recrystallized by thermal annealing to form a polysilicon film. Any method may be used.

Next, as shown in FIG. 9C, a gate oxide film 2 made of a silicon oxide film having a thickness of about 500 Å to about 1500 Å is formed on the surface of the semiconductor film 1a by a thermal oxidation method or the like. . Alternatively, after forming a thermal oxide film of about 50 angstroms to about 1000 angstroms, preferably 300 angstroms, a silicon oxide film of about 10 is formed on the entire surface by a CVD method or the like.
The gate insulating film 2 may be formed by depositing 0 angstrom to about 1000 angstrom, preferably 500 angstrom. Further, a silicon nitride film may be used to further increase the breakdown voltage of the gate insulating film 2.

Next, as shown in FIG. 9D, the polysilicon film 3 for forming a gate electrode and the like is formed on the insulating substrate 1.
After being formed on the entire 0 surface, phosphorus is thermally diffused to render the polysilicon film 3 conductive. Alternatively, a doped silicon film in which phosphorus is introduced at the same time as the polysilicon film 3 is formed may be used. Next, the polysilicon film 3 is patterned by using a photolithography technique as shown in FIG.
The gate electrode 3a is formed on the side of the pixel TFT section. On the other hand, on the side of the static electricity countermeasure wiring portion and the terminal portion, a polysilicon film is connected to the short-circuit wiring 3b (first, second, and third wirings).
Corresponds to the short-circuit wirings 91, 92, 93. ) And under the terminal sheet film 3c (combined process).

Next, as shown in FIG. 9F, the pixel TF
On the side of the T section and the N-channel TFT section of the drive circuit, using the gate electrode 3a as a mask, about 0.1 × 10 ¹³ / cm 3
Implantation of low-concentration impurity ions 100 (phosphorus ions) is performed with a dose amount of ² to about 10 × 10 ¹³ / cm ² , and a low-concentration source is self-aligned with the gate electrode 3a on the pixel TFT side. A region 1b and a low concentration drain region 1c are formed. Here, since it is located right below the gate electrode 3a, the portion where the impurity ions 100 are not introduced becomes the channel region of the semiconductor film 1a as it is. When the ion implantation is performed in this manner, impurities are introduced into the gate electrode 3a, the short-circuit wiring 3b, and the polysilicon film formed as the under-terminal sheet film 3c, so that they become more conductive. It will be.

Next, as shown in FIG.
In the FT portion, a resist mask 102 having a width wider than that of the gate electrode 3a is formed, and high concentration impurity ions 101 (phosphorus ions) are added in an amount of about 0.1 × 10 ¹⁵ / cm ² to about 10 × 10 5.
Implantation is performed with a dose amount of ¹⁵ / cm ² to form high-concentration source region 1d and drain region 1e.

Instead of these impurity introduction steps, a high concentration impurity (phosphorus ion) is implanted in a state where a resist mask 102 wider than the gate electrode 3a is formed without implanting a low concentration impurity, and an offset structure is formed. The source region and the drain region may be formed. It is needless to say that a high concentration impurity (phosphorus ion) may be implanted on the gate electrode 3a to form the source region and the drain region of the self-aligned structure.

Although not shown, in order to form the P-channel TFT portion of the peripheral drive circuit, the pixel portion and the N-channel TFT portion are covered and protected with a resist, and the gate electrode is used as a mask to set the gate voltage to about 0. By implanting boron ions at a dose of 1 × 10 ¹⁵ / cm ² to about 10 × 10 ¹⁵ / cm ² , P-channel source / drain regions are formed in a self-aligned manner. As in the case of forming the N-channel TFT section, the gate electrode is used as a mask to form about 0.1 ×.
After forming a low-concentration region in the polysilicon film by introducing a low-concentration impurity (boron ion) with a dose amount of 10 ¹³ / cm ² to about 10 × 10 ¹³ / cm ² , the width is wider than that of the gate electrode. A mask is formed to remove high-concentration impurities (boron ions) from about 0.1 × 10 ¹⁵ / cm ² to about 10 × 10 ¹⁵ / c.
Implanted at a dose of m ² , LDD structure (lightly
A source region and a drain region of a doped / drain structure) may be formed. Alternatively, the source region and the drain region of the offset structure may be formed by implanting a high-concentration impurity (phosphorus ion) in a state where a mask wider than the gate electrode is formed without implanting a low-concentration impurity. With these ion implantation processes, CM
The OS can be realized, and the peripheral drive circuit can be built in the same substrate.

Next, as shown in FIG. 10B, the surface of the gate electrode 3a, the short-circuit wiring 3b and the lower terminal sheet film 3c is formed on the surface side thereof by a CVD method or the like under a temperature condition of, for example, about 800.degree. About 5000 angstroms to about 15
A first interlayer insulating film 4 made of an NSG film (a silicate glass film containing no boron or phosphorus) of 000 Å is formed.

Next, as shown in FIG. 10C, the first pixel is formed on the pixel TFT section side by using the photolithography technique.
Of the inter-layer insulating film 4 of the above, the contact hole 5a, in the portion corresponding to the source region 1d and in the portion of the first inter-layer insulating film 4 corresponding to the terminal lower sheet film 3c on the terminal side.
5c are formed respectively.

Next, as shown in FIG. 10D, an aluminum film 6 for forming a source electrode is formed on the surface side of the first interlayer insulating film 4 by a sputtering method or the like. In addition to a metal film such as aluminum, a metal silicide film or a metal alloy film may be used. After that, as shown in FIG. 10E, the aluminum film 6 is patterned by using the photolithography technique, and the data line 30 is formed in the pixel TFT portion.
The source electrode 6a is formed as a part of. In addition, the signal wiring 6b (signal wiring 72, 73) is provided in the static electricity countermeasure wiring section.
And the terminal 6c (terminals 80, 81,
82 ...).

By utilizing these steps of FIGS. 10C to 10E, the first and third short circuit wirings 91 and 93, the signal input lines 72 and 73, and the data described with reference to FIG. 5 are used. A wiring connection with the line 30 is made.

Next, as shown in FIG. 11A, C is formed on the surface side of the source electrode 6a, the signal wiring 6b and the terminal 6c.
By the VD method or the like, for example, under a temperature condition of about 400 ° C., a BPSG film (silicate glass film containing boron or phosphorus) having a thickness of about 500 Å to about 15,000 Å, and about 100 Å to about 300 Å.
A second interlayer insulating film 7 including at least two layers of 0 Å NSG film is formed.

Next, as shown in FIG. 11B, the pixel T
On the FT portion side, the second contact hole 8a is formed in a portion of the second interlayer insulating film 7 and the first interlayer insulating film 4 corresponding to the drain region 1e by using a photolithography technique and a dry etching method. To form. At the same time, on the side of the static electricity countermeasure wiring portion, the cutting hole 8b is formed on the short circuit wiring 3b (corresponding to the first, second, and third short circuit wirings 91, 92, 93).

Next, as shown in FIG. 11C, an ITO film 9 (having a thickness of about 400 angstroms to about 2000 angstroms) for forming a drain electrode is formed on the surface side of the second interlayer insulating film 7. Indium Tin Ox
ide) is formed by a sputtering method or the like, and then, FIG.
As shown in, IT using photolithography technology
By patterning the O film 9, the pixel electrode 9 is formed in the pixel TFT section.
a is formed. In the static electricity countermeasure wiring section and terminal section, I
The TO film 9 is completely removed. Here, the pixel electrode 9a is not limited to the ITO film, and it is also possible to use a transparent electrode material made of a metal oxide having a high melting point such as a SnOx film or a ZnOx film. Step coverage in the contact hole is also practical.

Next, as shown in FIG. 12A, a resist mask 10 in which a region to be exposed as the terminal 6c in the terminal portion is opened on the surface side of the second interlayer insulating film 7 is opened.
3 is formed. The resist mask 103 also has a window opening portion at the position corresponding to the cutting hole 8b on the side of the static electricity countermeasure wiring portion. In this static electricity countermeasure wiring section,
The window opening portion of the resist mask 103 is larger than the cutting hole 8b.

After that, etching is performed through the resist mask 103 to expose the terminal 6c from the opening 12 in the terminal portion as shown in FIG. At the same time, the short-circuit wiring 3b is cut on the side of the static electricity countermeasure wiring portion, and the wiring is separated by the cutting portion 19.

Since the short-circuit wiring 3b is cut in the final process of the manufacturing process as described above, it is effective against static electricity generated in many processes before that.

(Optimal example of the above process) In the manufacturing method of such an active matrix, as shown in FIG.
When the cutting hole 8b is formed in the step shown in FIG. 3, dry etching and wet etching are used together, and underetching just below the resist mask causes the dimension L of the upper opening to be lower than the lower dimension, as shown in FIG. It is preferable to form a cutting hole 8b wider than M. And FIG.
In the step shown in FIG. 2A, as shown in FIG.
The window opening portion 103A of the resist mask 103 is made larger than the cutting hole 8b, and then, in the step shown in FIG. 12B, first, dry etching is performed as shown in FIG. Wet etching is performed as shown in FIG. 14 (C), and thereafter, dry etching is performed again as shown in FIG. 14 (D) to cut the short circuit wiring 3b. In this way, when the resist mask 103 is not covered with the inner wall of the cutting hole 8b and the wet etching is performed after the dry etching, FIG.
It is possible to completely remove the residue Q of the ITO film attached to the inner wall of the cutting hole 8b without being completely removed by the etching step shown in (D). Therefore, since no conductive substance remains inside the cutting hole 8b, a short circuit at this portion can be reliably prevented. When dry etching is performed as described above and wet etching is performed thereafter, as shown in FIG. 15, the resist mask 103 and the second interlayer insulating film 7 are formed.
In anticipation of the etching solution entering through the gap between
It is necessary to determine the dimensions as follows. This is because if the second interlayer insulating film 7 is not wet-etched next to the signal wiring 6b, the signal wiring 6b will be exposed and the reliability will be deteriorated. As shown in FIG. 15, the inventor of the present application has the following relationship c <8t ... (1) c <10k ... (2) between the dimensions c, k, and t as shown in FIG. It was found that it is possible to prevent the second interlayer insulating film 7 from disappearing beside the signal wiring 6b. Specifically, the active matrix substrate AM was manufactured by setting the dimension c so as to satisfy the above expressions (1) and (2) under the following conditions t = 2 to 10 µm k = 1 to 8 µm.

(Effect of this Embodiment) As described above, in this embodiment, the data line driving circuit 60 and the scanning line driving circuit 7 are provided.
A plurality of terminals 6c (80, 81, 82 ...
..) signal wiring 6b (72,
73) is electrically connected with the first short circuit wiring 91, and each step is performed. Therefore, even if static electricity is generated or electric charges are accumulated on the surface of the insulating substrate, the electric charges are diffused to the outer peripheral side of the substrate through the first short-circuit wiring 91, so that an excessive current causes the data line driving circuit 60 and Scan line drive circuit 7
It does not suddenly flow to 0. Therefore, the data line drive circuit 60
Further, the scan line driver circuit 70 can be protected. Moreover, contact holes are formed, patterned, and etched in the steps of forming TFTs, forming various wirings, and forming terminals. Therefore, the steps of forming cutting holes and the cutting are performed by using these steps also. A step of cutting the short circuit wiring through the use hole can be performed.

Further, since the second shorting wiring 92 electrically connected to each of the scanning lines 20 is used to prevent an excessive current from suddenly flowing into the scanning lines 20, the scanning lines 20 are prevented.
The pixel portion 11 can be protected. Further, a third short circuit wiring 93 electrically connected to each of the data lines 30.
Is used to prevent an excessive current from suddenly flowing to the data line 30, so that the data line 30, the sample hold circuit S / H, and the pixel section 11 can be protected.

[Second Embodiment] In the first embodiment, the first, second, and third short-circuit wirings 91, 92,
93 are connected to the signal wirings 72 and 73, the scanning line 20, and the data line 30, respectively, and the active matrix substrate A
The wires were separated after the manufacturing process of M was completed. On the other hand, in the present embodiment, as shown in FIG. 16 and FIG.
A plurality of terminals 6c for supplying a plurality of signals for driving the data line driving circuit 60 and the scanning line driving circuit 70.
(80, 81, 82 ...) Of the plurality of signal wirings routed from (80, 81, 82 ...), the signal wiring located closer to the terminal 6c (80, 81, 82 ...) than the electrostatic protection circuits 65, 75. The first short circuit wiring 91 is formed only for 72 and 73. These first short circuit wirings 91 are the scanning lines 2
0 and the data line 30 are not electrically connected. Other configurations and manufacturing methods are the same as those in the first embodiment except that the second and third short circuit wirings 92 and 93 are not formed. Therefore, common portions are shown in FIGS. Are denoted by the same reference numerals and the description thereof will be omitted.

Even with such a structure, even if static electricity is generated or electric charges are accumulated on the surface of the insulating substrate 10, the electric charges are diffused to the outer peripheral side of the substrate through the first short circuit wiring 91. Excessive current does not suddenly flow to the data line driving circuit 60 and the scanning line driving circuit 70. Therefore,
The data line driving circuit 60 and the scanning line driving circuit 70 can be protected.

[Third Embodiment] In the first embodiment, the first to third short circuit wirings 91, 92 and 93 are connected to the signal wirings 72 and 73, the scanning line 20 and the data line 30, respectively. Each line was separated after the manufacturing process of the active matrix substrate AM was completed. On the other hand, in the present embodiment, as shown in FIGS. 18 and 19, from the plurality of terminals (80, 81, 82 ...) To the data line driving circuit 60 and the scanning line driving circuit 70, respectively. A first short circuit wiring 91 is formed for the routed signal wirings 72 and 73. Further, the second short circuit wiring 92 is also formed for the scanning line 20. Other configurations and manufacturing methods are the same as in the first embodiment except that the third short circuit wiring 93 is not formed. Therefore, common portions are denoted by the same reference numerals in FIGS. 18 and 19.
The description thereof will be omitted.

Even with such a structure, even if static electricity is generated or electric charges are accumulated on the surface of the insulating substrate, the electric charges are transferred to the outer peripheral side of the substrate through the first and second short-circuit wirings 91 and 92. Since it is diffused, an excessive current does not suddenly flow to the data line driving circuit 60, the scanning line driving circuit 70, and the scanning line 20. Therefore, the data line driving circuit 60, the scanning line driving circuit 70, and the scanning line 20 can be protected.

(Modification of Third Embodiment) In the third embodiment shown in FIG. 18, of the second short-circuit wirings 92 formed for the scanning lines 20, the short-circuit wiring 92A that crosses the signal wiring 73. The part corresponding to is the signal wiring 7 that intersects with it.
Electrically connected to all three. On the other hand, in the present embodiment, as shown in FIG. 20, the portion corresponding to the short-circuit wiring 92A is not electrically connected to the signal wiring 73 intersecting therewith, and thus the second short-circuit wiring 92 is formed. Signal wiring 7
Of the three, the connection is made only to the portion located closer to the terminals 80 and 82 than the electrostatic protection circuit 75. This is because static electricity that has entered through the connection hole of the short-circuiting wiring 92A may enter the scanning line driving circuit 70 without passing through the electrostatic protection circuit and destroy the scanning line driving circuit 70. Embodiment 1
Then, the scanning line driving circuit 70 and the cutting hole 8b were connected without passing through the static electricity protection circuit. However, this is because the signal wiring 73 is wired long on the outer peripheral side of the active matrix substrate. The effect is to collect static electricity, and the signal wiring 66 is intentionally short-circuited at many places to prevent electrostatic breakdown. The antenna effect becomes remarkable as the wiring length becomes longer as the size of the active matrix substrate becomes larger. According to the research conducted by the inventor of the present application, it has been found that the effect becomes particularly large when the size is 1.8 inches or more.

In the first embodiment, the electrostatic protection circuit (see FIG.
reference. 20) may be configured between the cutting hole of the short circuit wiring 92A and the scanning line driving circuit 70 in FIG. With this configuration, as shown in FIG. 8, the terminal 80 (or 8
1, 82), or static electricity entering from the short-circuiting wiring 92A, the protection resistor 66 and the static electricity protection circuit 65 (or 7).
If it does not pass 5), it does not reach the data line driving circuit 60 and the scanning line driving circuit 70. Therefore, the static electricity is surely absorbed by the static electricity protection circuit 65 (or 75), and the data line driving circuit 60 and the scanning line driving circuit 70 can be surely protected.

(Manufacturing Method of Third Embodiment and its Modifications) In the first embodiment, a cutting hole is formed in the step shown in FIG. 11B, and a short circuit is made in the step shown in FIG. 12B. The wiring 3b was cut, but here, the cutting hole is formed in the step shown in FIG. 10C, and the second step is performed by using the etching step as the post-treatment in the step shown in FIG. An example of cutting the short circuit wiring 92 will be described.

In this example, as shown in FIG.
After forming the resist mask 105 on the surface of the first interlayer insulating film 4, first, dry etching is performed, and then wet etching is performed as illustrated in FIG. 21A to form the cutting hole 5b. As a result, the cutting hole 5b having a wide upper end opening can be formed.

On the other hand, after the step shown in FIG.
As a subsequent process, as shown in FIG. 22 (A), silicon powder contained in aluminum adheres to the surface of the first interlayer insulating film 4 as shown in FIG. 22 (B). Etch silicon by dry etching containing, for example, fluorine or chlorine. At this time, at the same time, the second
The short circuit wiring 92 is cut. Also in this method, since the conductive substance does not remain inside the cutting hole 5b, it is possible to reliably prevent a short circuit at this portion.

[Other Method of Forming Cutting Holes / Cutting Short-Circuiting Wiring] Incidentally, forming the cutting holes / short-circuiting wiring 3b
As a cutting method of, for example, in the etching step for exposing the terminal 6c in the step shown in FIG. 12B, both dry etching and wet etching are used, or only one etching is performed to expose the terminal 6c. The holes for forming may be formed, and thereafter, the short circuit wiring 3b may be selectively cut by using both dry etching and wet etching, or by only one etching. According to this method, since the conductive substance does not remain inside the cutting hole, it is possible to reliably prevent a short circuit at this portion. Further, if wet etching is used to form the cutting holes, the amount of dry etching for forming the cutting holes can be reduced, so that excessive plasma irradiation is not received. Therefore, electrostatic failure is unlikely to occur.

After the steps shown in FIG. 12B are completed, a new step is added, and in this step a cutting hole is formed by dry etching and wet etching, and then another mask is used. The short circuit wiring 3b may be cut by dry etching. Also in this method, since the conductive substance does not remain inside the cutting hole, it is possible to reliably prevent a short circuit at this portion. Further, since wet etching is used to form the cutting holes, light dry etching is sufficient to form the cutting holes, and therefore excessive plasma irradiation is not received. Therefore, electrostatic failure is unlikely to occur.

In any of these cases, the short-circuit wiring 3b is cut in the final step of the manufacturing process, which is effective against static electricity generated in many previous steps.

[Structure of Liquid Crystal Display Panel] The active matrix substrate AM of each mode thus formed is shown in FIG.
As shown in FIG. 7, the counter substrate OP and the counter substrate OP are bonded to each other in a state where a predetermined cell gap is secured by the seal layer 110 to form the liquid crystal display panel LP. Here, since the seal layer 110 is partially interrupted, the liquid crystal 120 is sealed inside the seal layer 110, and then the seal layer 130 is closed. In this state, since the counter substrate OP is smaller than the active matrix substrate AM, various terminals 80, 81, 82 ...
.., scan line drive circuit 60 and data line drive circuit 70
Are located outside the counter substrate OP.

(Example of Use of Liquid Crystal Display Panel) An example of use of the liquid crystal display panel LP according to the above-described embodiment in an electronic device when the liquid crystal display panel LP is of a transmissive type will be described with reference to FIGS. 24 and 25.

As shown in the block diagram of FIG. 24, an electronic apparatus constructed by using the liquid crystal display panel of the above-described form has a display information output source 1000, a display information processing circuit 1002, a display driving device 1004, a liquid crystal display panel 1006. , A clock generation circuit 1008, and a power supply circuit 1010. The display information output source 1000 includes ROM, RA
The clock generator circuit 100 is configured to include a memory such as M and a tuning circuit that tunes and outputs a television signal and the like.
The display information is processed and output based on the clock from 8. This display information output circuit 1002 is, for example, an amplifier
Polarity inversion circuit, phase expansion circuit. The liquid crystal display panel 1006 is configured to include a rotation circuit, a gamma correction circuit, a clamp circuit, and the like. Power supply circuit 10
10 supplies electric power to each circuit described above.

FIG. 2 shows an electronic device having such a configuration.
5, a liquid crystal projector, a personal computer (PC) compatible with multimedia, an engineering workstation (EWS), a pager, or a mobile phone, a word processor, a television, a viewfinder type or monitor direct-viewing video tape recorder, an electronic notebook, Electronic desk calculator, car navigation system, PO
Examples thereof include an S terminal and a device including a touch panel.

The projection type display device shown in FIG. 25 is a projection type projector using a liquid crystal display panel as a light valve, and uses, for example, a three-prism type optical system. In FIG. 25, in the liquid crystal projector 1100,
The projection light emitted from the lamp unit 1102 of the white light source is provided inside the light guide 1104, and the plurality of mirrors 11
The three liquid crystal display panels 11 that separate the three primary colors of R, G, and B (light separation means) by the 06 and two dichroic mirrors 1108 to display images of the respective colors.
10R, 1110G, 1110B. And
Each liquid crystal display panel 1110R, 1110G, 1
The light modulated by 110B is incident on the dichroic prism 1112 (light combining means) from three directions.
In the dichroic prism 1112, the lights of red R and blue B are bent by 90 ° and the lights of green G go straight, so that lights of respective colors are combined and a color image is projected on a screen or the like through a projection lens 1114.

The present invention is not limited to the above embodiments, but can be implemented in various modified forms within the scope of the gist of the present invention. For example, the present invention is not limited to being applied to the driving of the above-mentioned various liquid crystal display panels, but can also be applied to electroluminescence and plasm display devices.

[0070]

As described above, in the method of manufacturing an active matrix substrate according to the present invention, a plurality of terminals are provided for supplying a plurality of signals necessary for driving the data line driving circuit and the scanning line driving circuit. The respective steps are performed in a state in which the signal wirings respectively routed from the above are electrically connected by the first short circuit wiring. Therefore, even if static electricity is generated or electric charges are accumulated on the surface of the insulating substrate, the electric charges are diffused to the outer peripheral side of the substrate through the first short-circuit wiring, so that an excessive current causes an excess current. It does not suddenly flow into the drive circuit. Therefore, the data line driving circuit and the scanning line driving circuit can be protected. Moreover, contact holes are formed, patterned, and etched in the steps of forming TFTs, forming various wirings, and forming terminals. Therefore, the steps of forming cutting holes and the cutting are performed by using these steps also. A step of cutting the short circuit wiring through the use hole can be performed.

When the step of cutting the short-circuit wiring is performed in a step close to the final step of removing the second interlayer insulating film formed on the surface of the terminal, it occurs in the step performed before that. The drive circuit and the pixel portion can be effectively protected from static electricity.

Further, at least when wet etching is performed in the step of cutting the short circuit wiring, no conductive material remains in the cutting hole, so that no short circuit occurs in the connection hole.

[Brief description of drawings]

FIG. 1 is a block diagram of an active matrix substrate of a liquid crystal display panel according to Embodiment 1 of the present invention.

FIG. 2 is an enlarged plan view showing a corner portion of a pixel portion of the active matrix substrate shown in FIG.

FIG. 3 is an equivalent circuit diagram of a pixel on the active matrix substrate shown in FIG.

FIG. 4 is a plan view of terminals of the active matrix substrate shown in FIG.

5 is a plan view showing a connection structure of signal wirings and short-circuiting wirings in the active matrix substrate shown in FIG.

FIG. 6 is a plan view showing a state in which the active matrix substrates shown in FIG. 1 are formed in an array on a mother substrate.

FIG. 7 is an enlarged plan view showing a region A in the mother substrate shown in FIG.

8 is a circuit diagram of an electrostatic protection circuit configured on the active matrix substrate shown in FIG.

9A to 9D are process cross-sectional views showing a method of manufacturing the active matrix substrate shown in FIG.

FIG. 10 is a process cross-sectional view of each process performed after the process shown in FIG.

FIG. 11 is a process cross-sectional view of each process performed after the process shown in FIG.

FIG. 12 is a process cross-sectional view of each process performed after the process shown in FIG.

FIG. 13 is an explanatory diagram of a cutting hole forming step among the steps shown in FIGS. 9 to 12.

FIG. 14 is an explanatory diagram of a step of cutting the short circuit wiring among the steps shown in FIGS. 9 to 12;

FIG. 15 is an explanatory diagram for forming a cutting hole.

FIG. 16 is a block diagram of an active matrix substrate of a liquid crystal display panel according to Embodiment 2 of the present invention.

17 is an enlarged plan view showing a corner portion of a pixel portion of the active matrix substrate shown in FIG.

FIG. 18 is a block diagram of an active matrix substrate of a liquid crystal display panel according to Embodiment 3 of the present invention.

19 is an enlarged plan view showing a corner portion of a pixel portion of the active matrix substrate shown in FIG.

FIG. 20 is a block diagram of an active matrix substrate of a liquid crystal display panel according to a modification of the third embodiment of the present invention.

FIG. 21 is an explanatory diagram of another cutting hole forming step.

FIG. 22 is an explanatory diagram of another step of cutting the short circuit wiring.

FIG. 23 is an explanatory diagram showing a structure in which a counter substrate is attached to an active matrix substrate.

FIG. 24 is a block diagram of an electronic device using a liquid crystal display panel to which the present invention is applied.

FIG. 25 is an explanatory diagram showing an optical system of a projection display device using a liquid crystal display panel to which the present invention has been applied.

FIG. 26 is a block diagram of an active matrix substrate of a conventional liquid crystal display panel.

[Explanation of symbols]

4 First interlayer insulating film 5b, 8b Cutting hole 6c, 80, 81, 82 terminals 7 Second interlayer insulating film 11 pixels (screen display area) 19 cutting part 20 scan lines 30 data lines 50 TFT 60 data line drive circuit 65, 75 Electrostatic protection circuit 66 Protection resistance 70 Scan line drive circuit 72, 73 signal wiring 91A, 91B First wiring for short circuit 92 Second short-circuit wiring 93 Third short-circuit wiring 99 Antistatic wiring AM active matrix substrate (TFT substrate) MM mother board

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-1-233425 (JP, A) JP-A-2-242229 (JP, A) JP-A-2-267527 (JP, A) JP-A-5- 289102 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) G02F 1/1368 G09F 9/00 309 H01L 29/786

Claims (11)

(57) [Claims] 1. A pixel portion including a plurality of scanning lines, a plurality of data lines, a pixel switching thin film transistor connected to the data lines and the scanning lines, and a data side connected to the data lines and the scanning lines, respectively. A driver circuit and a scan line driver circuit, a plurality of signal wirings for supplying a plurality of signals necessary for driving the scan line driver circuit and the data line driver circuit, and a plurality of signal wirings connected to the signal wirings. The thin film transistor has a terminal on a substrate, and the thin film transistor electrically connects to the data line through a gate electrode formed at the same time as the scanning line and a first contact hole formed in a first interlayer insulating film. The pixel electrode is electrically connected through the source region to be connected, the second interlayer insulating film and the second contact hole formed in the second interlayer insulating film on the upper side of the first interlayer insulating film. A method of manufacturing an active matrix substrate including a drain region electrically connected, and a step of forming a first short-circuit line electrically connected to each of the signal lines together with the scanning line and the gate electrode, Active comprising: a step of forming a first cutting hole on the first short-circuit wiring; and a step of cutting the first short-circuit wiring through the first cutting hole. Matrix substrate manufacturing method. 2. The second short-circuit wiring according to claim 1, wherein after forming the second short-circuit wiring electrically connected to each of the scanning lines in the step of forming the first short-circuit wiring. A method of manufacturing an active matrix substrate, comprising: forming a second cutting hole on a wiring; and cutting the second short circuit wiring through the second cutting hole. . 3. The first short circuit wiring according to claim 1, wherein in the step of forming the first short circuit wiring, a third short circuit wiring intersecting with each of the data lines is formed. Electrically connecting the third short-circuit wiring and the data line through a third contact hole formed in the interlayer insulating film, and then cutting the third short-circuit wiring on the third short-circuit wiring. A method of manufacturing an active matrix substrate, comprising: forming a hole; and cutting the third short circuit wiring through the third cutting hole. 4. The method according to any one of claims 1 to 3,
A method of manufacturing an active matrix substrate, wherein the step of forming the cutting hole is also performed as the step of forming the contact hole. 5. The method according to any one of claims 1 to 4,
A method for manufacturing an active matrix substrate, wherein the step of cutting the short circuit wiring is performed also as an etching step of removing the second interlayer insulating film formed on the surface of the terminal. 6. The method according to any one of claims 1 to 5,
In the step of forming the cutting hole, wet etching is performed when the surface of the short circuit wiring is finally exposed. 7. The method according to any one of claims 1 to 5,
A method of manufacturing an active matrix substrate, wherein at least wet etching is performed in the step of cutting the short circuit wiring. 8. The method according to any one of claims 1 to 5,
In the step of forming the short-circuit wiring, the short-circuit wiring is electrically connected to the signal wiring located on the terminal side of the electrostatic protection circuit among the signal wirings. Production method. 9. The method according to claim 1, wherein
On the outer peripheral side of the active matrix substrate, a static electricity countermeasure wiring that is electrically connected to the short circuit wiring is formed, and the static electricity countermeasure wiring is adjacent on a mother substrate on which a large number of the active matrix substrates are formed. The static electricity countermeasure wirings of the active matrix substrate are electrically connected to each other, and when the respective active matrix substrates are cut out from the mother substrate, the static electricity countermeasure wirings of the adjacent active matrix substrates are electrically connected to each other. A method for manufacturing an active matrix substrate, which is characterized by being cut off. 10. An active matrix substrate manufactured by the manufacturing method according to any one of claims 1 to 9. 11. A liquid crystal display panel using the active matrix substrate defined in claim 10.