JP2008177457A - Method of manufacturing semiconductor device, method of manufacturing electro-optic device, and half-tone mask - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device with which a low-concentration impurity region and a high-concentration impurity region can be formed with a single impurity-introducing step, a method of manufacturing an electro-optic device, and a half-tone mask used in the methods of manufacturing thereof. <P>SOLUTION: In manufacturing a TFT, a resist mask 20 is formed using a half-tone mask 30 and a positive-type resist material 200, and subsequently a high-concentration impurity is introduced into a semiconductor film 1a, forming a source-side high-concentration impurity region 1c and a drain-side high-concentration impurity region 1f. In the half-tone mask 30, semi-transparent films 32 are so formed as to cover the both side ends of a light-shielding film 31. Therefore, in the resist mask 20, medium thick portions 20d are formed between a thick portion 20b and thin portions 20c. A source-side low-concentration impurity region 1e and a drain-side low-concentration impurity region 1f are respectively formed in regions that overlap the medium thick portions 20d. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a TFT semiconductor device, a method for manufacturing an electro-optical device, and a halftone mask.

  As an electro-optical device such as a liquid crystal device, an organic electroluminescence (EL) device, or a plasma display, a thin film transistor (TFT (Thin Film Transistor)) is used for each dot in order to drive a large number of dots arranged in a matrix. An active matrix electro-optical device provided with a) is widely used. The TFT generally uses amorphous silicon or polycrystalline silicon as a channel region. In particular, a polycrystalline silicon TFT manufactured only by a low-temperature process is widely used in electro-optical devices such as the above-described liquid crystal devices and organic EL devices because electrons or holes have a large electric field mobility.

  As the TFT, a TFT having an LDD (Lightly Doped Drain) structure and a TFT having a GOLD (Gate-drain Overlapped LDD) structure are widely known. A TFT having an LDD structure has a structure in which a low concentration impurity region is formed in a polycrystalline silicon film corresponding to an outer region immediately below a gate electrode, and a high concentration impurity region serving as a source region and a drain region is formed in the outer region. And has an effect of suppressing the off-current value. On the other hand, a TFT having a GOLD structure has a structure in which the low-concentration impurity region of the LDD structure is formed so as to overlap to a region immediately below the end of the gate electrode, and has an effect of suppressing the hot carrier phenomenon.

  Among the LDD and GOLD structures, as a method of forming a TFT having an LDD structure, for example, as shown in FIGS. 7B and 7C, a TFT channel region and a low concentration are formed on the upper layer of the semiconductor film 1. A resist mask 20 'having a thick portion overlapping the region and a thin portion overlapping the high-concentration impurity region is formed, and in this state or after patterning into the island-shaped semiconductor film 1a as shown in FIG. High-concentration impurities are introduced into the semiconductor film 1a through the thin portion 20c 'of the resist mask 20' to form high-concentration impurity regions 1c and 1d, and then low-concentration impurities are introduced into the semiconductor film using the gate electrode as a mask. A method of forming a low concentration impurity region has been proposed (see Patent Document 1).

In addition, as a method of forming a TFT having a GOLD structure, a resist mask is formed on the upper layer of the semiconductor film by forming a resist mask having a thick portion overlapping the channel region and a thin portion overlapping the low-concentration impurity region. On the other hand, a method has been proposed in which a low concentration impurity region is formed by introducing a low concentration impurity through a thin portion of a resist mask and then a high concentration impurity region is formed by introducing a high concentration impurity into a semiconductor film through a gate electrode. (See Patent Document 1).
JP 2006-54424 A

  In the semiconductor device described above, the manufacturing cost is greatly affected by the number of processes, and thus the number of manufacturing processes is required to be reduced. However, in the method disclosed in Patent Document 1, the number of steps is large, for example, the low concentration impurity region and the high concentration impurity introduction step are performed by two impurity introduction steps, and further reduction of the number of steps is required. .

  Further, when a TFT is manufactured by the method disclosed in Patent Document 1, as shown in FIG. 7A, a semi-transparent film 32 ′ is formed on the lower side of the light shielding film 31 ′ in the translucent substrate 35 ′. When the resist mask 20 'having a thick portion 20b' and a thin portion 20c 'is formed by exposure and development using the halftone mask 30' as shown in FIG. The light reflected from the interface between the semi-transparent film 32 'and the translucent substrate 35' may be exposed to the position where it overlaps with the outer peripheral edge of the light shielding film 31 '. As a result, as shown in FIG. 7D, the resist mask 30 'has a flat inclined surface 20x on the entire side surface of the thick portion 20b'. Therefore, as shown in FIG. 7D, when a high concentration impurity is introduced from the thin portion 20c ′ of the resist mask 20 ′, even in the region where the resist mask 20 ′ overlaps the thick portion 20b ′ in the semiconductor film 1a. In the portion overlapping the lower end side of the inclined surface 20x, high-concentration impurities are introduced. Therefore, as shown in FIG. 7E, the planar surface of the semiconductor film 1a is also formed at both ends in the channel width direction of the channel region 1b, and the high concentration regions 1x are formed at both ends in the channel width direction of the channel region 1b. The concentration region 1x forms an electron path that electrically connects the source side 1s and the drain side 1t. When such a situation occurs, in the TFT, electrons leak from the source side 1s to the drain side 1t regardless of on / off, and the TFT does not switch correctly.

  In view of such a situation, an object of the present invention is to form a low-concentration impurity region and a high-concentration impurity region by one impurity introduction step, and impurity regions are formed at both ends in the channel width direction of the channel region. It is an object of the present invention to provide a method for manufacturing a semiconductor device, a method for manufacturing an electro-optical device, and a halftone mask used in these methods.

  In order to solve the above problems, in the present invention, a semiconductor film in which a low concentration impurity region is formed between a channel region and a high concentration impurity region on the source side and the drain side, and at least gate insulation with respect to the channel region A method of manufacturing a semiconductor device having a thin film transistor provided with a gate electrode facing through a film, the semiconductor film forming step of forming a semiconductor film on a substrate, and a positive type coated on the upper side of the semiconductor film The resist material is exposed and developed using a halftone mask in which a light-shielding film and a semi-transparent film are each formed on a translucent substrate with a predetermined pattern, and a portion overlapping the channel region is thick, and the high concentration A resist mask forming step of forming a thin resist mask in a portion overlapping with the impurity region; and passing the thin portion of the resist mask through the semiconductor film. An impurity introduction step for introducing high-concentration impurities, and in the resist mask formation step, each of the semi-transparent films is provided as a half-tone mask in a region adjacent to both end portions of the light-shielding film. A mask that is formed and is formed so that the translucent film covers both end portions of the light shielding film is used.

  In the present invention, the mask means to include a reticle. In the present invention, the term “exposure” means so-called “light such as visible light and ultraviolet light”, and also includes electron beams and X-rays, and “semi-transparent film” means light. It is not meant to transmit only half, but to reduce light intensity.

  In the present invention, a resist mask having a thin resist mask with respect to the semiconductor film is formed using a halftone mask and a positive resist material, after forming a resist mask having a thick portion overlapping the channel region and a thin portion overlapping the high-concentration impurity region. High concentration impurities are introduced through the part. As a result, no impurity is introduced into a portion where the resist mask is thick and a channel region is formed, while a high concentration impurity is introduced into a portion where the resist mask is thin to form a high concentration impurity region. Here, in the halftone mask, a semi-transparent film is formed in a region adjacent to both end portions of the light shielding film, and the semi-transparent film is formed so as to cover both end portions of the light shielding film. Therefore, since the semi-transparent film is thickly formed near both ends of the light shielding film, a portion having an intermediate thickness is formed between the thick portion and the thin portion in the resist mask. Therefore, when high-concentration impurities are introduced through a thin portion of the resist mask, a low-concentration impurity region is formed in the semiconductor film in a region overlapping with a portion having an intermediate thickness of the resist mask. Therefore, the channel region, the low-concentration impurity region, and the high-concentration impurity region can be formed by one impurity introduction step, and it is not necessary to separately perform the step of introducing the low-concentration impurity. Therefore, since the number of impurity introduction steps can be reduced, the manufacturing cost of the semiconductor device can be reduced. In addition, since the halftone mask does not have a semitransparent film between the light shielding film and the translucent substrate, the exposure light is semitransparent when the resist mask is formed by exposure and development using the halftone mask. The exposure light does not enter the region that is reflected at the interface between the film and the translucent substrate and overlaps the outer peripheral edge of the light shielding film. Therefore, in the resist mask, since the side surface of the thick portion does not become a gently tapered inclined surface, when the impurity is introduced, the impurity is difficult to be introduced into a portion overlapping the thick portion of the resist mask. Therefore, impurity introduction regions are hardly formed at both ends in the channel width direction of the channel region, and even if formed, they can be easily removed.

  In the present invention, after the impurity introduction step, the resist mask is removed, and then the gate insulating film forming step for forming the gate insulating film so as to cover the semiconductor film, and the gate electrode for forming the gate electrode It is preferable to perform the forming step. That is, it is preferable to form a gate insulating film after the impurity introduction step. With such a configuration, since the impurity can be introduced without passing through the gate insulating film, it is possible to avoid damage to the gate insulating film when the impurity is introduced. Therefore, a gate insulating film having excellent insulating properties can be formed, and the reliability of the thin film transistor can be improved.

  In the present invention, it is preferable that a patterning step of patterning the semiconductor film using the resist mask is performed after the resist mask forming step and before the gate insulating film forming step. With this configuration, the resist mask can be used in two processes, ie, a semiconductor layer patterning process and an impurity introduction process, so that the resist mask forming process can be reduced once. In addition, a process associated with the resist mask forming process, for example, a process such as peeling of the resist mask can be simultaneously reduced. In addition, since the positions of the high concentration impurity region, the low concentration impurity region, and the channel region in the patterned semiconductor film are uniquely determined by the halftone mask (resist mask), the high concentration impurity region, the low concentration impurity region, and the low concentration impurity region are defined at predetermined positions on the semiconductor film. A concentration impurity region and a channel region can be formed.

  The semiconductor device manufacturing method to which the present invention is applied can be applied to an electro-optical device manufacturing method. In this case, the semiconductor device is used as an element substrate provided with a thin film transistor and a pixel electrode electrically connected to the thin film transistor in each of a plurality of pixels.

  In the present invention, in the halftone mask in which the light shielding film and the semi-transparent film are each formed on the translucent substrate with a predetermined pattern, the semi-transparent film is formed in a region adjacent to both end portions of the light shielding film. Each of the films is formed, and the translucent film is formed so as to cover both end portions of the light shielding film.

  In the halftone mask to which the present invention is applied, the semi-transparent film is formed on the translucent substrate so as to cover the end portion of the light-shielding film. A film will be formed. Therefore, after forming the semi-transparent film on the translucent substrate, the position of forming the semi-transparent film with respect to the light-shielding film is different from the case where the formation position of the light-shielding film is aligned with the semi-transparent film. Since it is sufficient to match, the alignment between the light shielding film and the semi-translucent film is easy.

  Embodiments of the present invention will be described below with reference to the drawings. In the following description, an element substrate used in an active matrix transmissive liquid crystal device, which is a typical electro-optical device, is illustrated as a semiconductor device. In the drawings used for the following description, the scales of the respective layers and members are different in order to make each layer and each member recognizable on the drawings.

[Embodiment 1]
(Structure of electro-optical device)
FIG. 1 is an equivalent circuit diagram of switching elements, signal lines, and the like in a plurality of dots arranged in a matrix constituting an image display region of the electro-optical device (liquid crystal device) of this embodiment. 2A and 2B are plan views showing enlarged one dot of the element substrate used in the electro-optical device according to the present embodiment, and the liquid crystal at a position corresponding to the line AA ′. It is sectional drawing when an apparatus is cut | disconnected. In FIG. 2B, the upper side in the drawing is shown as the light incident side, and the lower side in the drawing is shown as the viewing side (observer side).

  As shown in FIG. 1, in an electro-optical device 150 to which the present invention is applied, a plurality of dots are arranged in a matrix in an image display region, and a pixel electrode 9a and a pixel electrode 9a are controlled for each of the plurality of dots. A TFT 90 for this purpose is formed. The data line 6a to which the image signal is supplied is electrically connected to the source of the TFT 90, and the image signals S1, S2,..., Sn are supplied in this order to the plurality of data lines 6a. Alternatively, it is supplied for each group to a plurality of adjacent data lines 6a. The scanning line 3a is electrically connected to the gate of the TFT 90, and the scanning signals G1, G2,..., Gm are applied to the plurality of scanning lines 3a in a pulse-sequential manner at a predetermined timing. The pixel electrode 9a is electrically connected to the drain of the TFT 90. By turning on the TFT 90, which is a switching element, for a predetermined period, the image signals S1, S2,. Write in. Image signals S1, S2,..., Sn written at a predetermined level on the liquid crystal via the pixel electrode 9a are held for a certain period with a common electrode described later. The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gradation display. Here, in order to prevent the held image signal from leaking, a storage capacitor 98 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the common electrode.

  As shown in FIG. 2B, in the electro-optical device 150 of this embodiment, the element substrate 100 and the counter substrate 104 are bonded to each other with a sealing material (not shown) through a predetermined gap. A liquid crystal layer 102 is held in the enclosed region. The element substrate 100 is configured as a semiconductor device in which a plurality of TFTs 90 are formed, and a common electrode 108 is formed on the counter substrate 104.

  As shown in FIG. 2A, a plurality of rectangular pixel electrodes 9a are arranged in a matrix on the element substrate 100, and data lines 6a and scanning lines 3a are arranged along the vertical and horizontal boundaries of each pixel electrode 9a. And the capacitor line 3b is formed.

  In the TFT 90, an active layer is formed by the island-shaped semiconductor film 1a. In this embodiment, the semiconductor film 1a is formed of a polycrystalline silicon film. The data line 6a is electrically connected to the source side 1s of the semiconductor film 1a via the contact hole 92, and the pixel electrode 9a is connected to the drain side 1t of the semiconductor film 1a with the contact hole 96 and the drain electrode 6b. And electrically connected via a contact hole 94. The scanning line 3a protrudes so that a part thereof faces the channel region 1b of the semiconductor film 1a, and the protruding part of the scanning line 3a functions as the gate electrode 3g. The semiconductor film 1a extends to a portion facing the capacitor line 3b, and a storage capacitor 98 is formed with the extended portion 1g as a lower electrode and the capacitor line 3b as an upper electrode.

  2B, an element substrate 100 includes a light-transmitting substrate 10 made of a light-transmitting material such as glass, a pixel electrode 9a formed on the surface of the light-transmitting substrate 10 on the liquid crystal layer 102 side, a TFT 90, and The alignment film 11 is mainly used. The counter substrate 104 is mainly composed of a translucent substrate 105 made of a translucent material such as glass, a common electrode 108 formed on the surface of the translucent substrate 105 on the liquid crystal layer 102 side, and an alignment film 110. ing.

  In the element substrate 100, a base protective film 12 made of a silicon oxide film or the like is formed on the upper surface of the translucent substrate 10. Further, a pixel electrode 9a made of a transparent conductive material such as indium tin oxide (ITO) is formed on the surface of the translucent substrate 10 on the liquid crystal layer 102 side, and the pixel electrode 9a is adjacent to each pixel electrode 9a. A TFT 90 is formed.

  A semiconductor film 1a made of polycrystalline silicon is formed in a predetermined island pattern on the base protective film 12, and a gate insulating film 2 made of a silicon oxide film or the like is formed on the upper side of the semiconductor film 1a. ing. On the gate insulating film 2, a scanning line 3a (gate electrode 3g) is formed. In the semiconductor film 1a, a region facing the gate electrode 3g through the gate insulating film 2 is a channel region 1b in which a channel is formed by an electric field from the gate electrode 3g. In the semiconductor film 1a, one side (the left side in the figure) of the channel region 1b is the source side 1s, and the other side (the right side in the figure) is the drain side 1t.

  In this embodiment, the TFT 90 has an LDD structure, and a high-concentration impurity region (source-side high-concentration impurity region 1c, drain) is provided on the source side 1s and the drain side 1t of the semiconductor film 1a. Side high concentration impurity region 1d) and low concentration impurity regions (source side low concentration impurity region 1e, drain side low concentration impurity region 1f) having a relatively low impurity concentration are formed. The concentration impurity region 1e and the drain side low concentration impurity region 1f) are formed between the channel region 1b and the high concentration impurity region (source side high concentration impurity region 1c, drain side high concentration impurity region 1d).

  A first interlayer insulating film 4 made of a silicon oxide film or the like is formed on the upper side of the scanning line 3a (gate electrode 3g), and a data line 6a and a drain electrode 6b are formed on the first interlayer insulating film 4. Has been. The data line 6a is electrically connected to the source side high-concentration impurity region 1c as a source electrode of the TFT 90 through a contact hole 92 formed in the first interlayer insulating film 4, and the drain electrode 6b is connected to the first interlayer insulating film. The contact hole 94 formed in the film 4 is electrically connected to the drain side high concentration impurity region 1d. A second interlayer insulating film 5 made of a silicon nitride film or the like is formed on the upper side of the data line 6a and the drain electrode 6b, and a pixel electrode 9a is formed on the second interlayer insulating film 5. The pixel electrode 9 a is electrically connected to the drain electrode 6 b through a contact hole 96 formed in the second interlayer insulating film 5.

  The extending portion 1g (lower electrode) from the drain side high concentration impurity region 1d of the semiconductor film 1a is connected to the scanning line 3a via an insulating film (dielectric film) integrally formed with the gate insulating film 2. The capacitor line 3b in the same layer is disposed opposite to the upper electrode, and a storage capacitor 98 is formed. An alignment film 11 is formed on the outermost surface of the element substrate 100 on the liquid crystal layer 102 side.

  On the other hand, in the counter substrate 104, light incident on the electro-optical device 150 is incident on the surface of the translucent substrate 105 on the liquid crystal layer 102 side, at least in the channel region 1 b and the low-concentration impurity region (on the source side low). A light shielding film 106 is formed to prevent the light from entering the concentration impurity region 1e and the drain side low concentration impurity region 1f). On the light-transmitting substrate 105, a common electrode 108 made of ITO or the like is formed almost entirely on the upper layer side of the light shielding film 106, and an alignment film 110 is formed on the upper layer side of the common electrode 108. . Note that when the liquid crystal device 150 is configured for color display, a color filter is formed on the counter substrate 104, but the illustration thereof is omitted in FIG.

(Method for manufacturing element substrate)
FIGS. 3A to 3E and FIGS. 4A to 4C show the n-channel TFT 90 having the LDD structure on the element substrate 100 in the manufacturing process of the liquid crystal device according to this embodiment. It is process sectional drawing which shows a manufacturing method.

First, as shown in FIG. 3A, a glass substrate cleaned by ultrasonic cleaning or the like is prepared as the light transmissive substrate 10. Thereafter, under the condition that the surface temperature of the substrate is 150 to 450 ° C., a base protective film (buffer film) 12 made of a silicon oxide film or the like is formed on the entire surface of the translucent substrate 10 to a thickness of 100 to 500 nm by plasma CVD or the like. Then, a film is formed. As the source gas used in this step, a mixed gas of monosilane and dinitrogen monoxide, TEOS (tetraethoxysilane, Si (OC ₂ H ₅ ) ₄ ) and oxygen, disilane and ammonia, and the like are preferable.

  Next, in the semiconductor film formation step, the semiconductor film 1 made of amorphous silicon is formed on the entire surface of the base protective film 12 to a thickness of 30 to 100 nm by plasma CVD or the like. As the source gas used in this step, disilane or monosilane is suitable. Next, the semiconductor film 1 is polycrystallized by laser annealing or the like.

  Next, in the resist mask forming step, as shown in FIG. 3B, after applying a positive resist material 200 on the semiconductor film 1, the resist material 200 is exposed and developed using the halftone mask 30. To do.

  In the halftone mask 30, a light shielding film 31 that completely blocks exposure light and a semitransparent film 32 that partially transmits exposure light are formed on the light transmissive substrate 35 with a predetermined pattern, respectively. The region where neither the semi-transparent film 32 nor the translucent film 32 is formed is a total light-transmitting region 30a that completely transmits the exposure light. The light shielding film 31 is made of, for example, Cr or Cr oxide, and the semi-transparent film 32 is made of, for example, Cr oxide, Cr—Co alloy, silicon nitride, or the like.

  Here, the light shielding film 31 is formed in a region corresponding to the channel region 1b. The translucent film 32 is first formed in a region adjacent to both end portions in the longitudinal direction of the light shielding film 31. Further, in the present embodiment, the semi-transparent film 32 covers the entire surface of the light shielding film 31 including the surfaces of both end portions 31 a and 31 b in the longitudinal direction of the light shielding film 31. For this reason, the semi-transparent film 32 is thin in a region away from the light shielding film 31, but is considerably thicker in the vicinity of the light shielding film 31 because it rides on the light shielding film 31.

  For this reason, in the halftone mask 30 of this embodiment, the light shielding region 30b in which the light shielding film 31 is formed, the total light transmitting region 30a in which neither the light shielding film 31 nor the semitransparent film 32 is formed, and the light shielding film A semi-transparent region 30c in which the semi-transparent film 32 is thinly formed in a region away from 31 and an intermediate region 30d in which the semi-transparent film 32 is formed thick in the vicinity of the light shielding film 31 are formed. The light transmission degree of the exposure light in the intermediate region 30d is higher than that of the light-shielding region 30b and lower than that of the semi-light-transmitting region 30c.

  In the halftone mask 30 having such a configuration, for example, after a light-shielding film is formed on the light-transmitting substrate 35, the film is patterned by a photolithography technique to form a light-shielding film 31, and then The film is manufactured by forming a semi-transparent film on the upper layer side of the light shielding film 31 and then patterning the film by a photolithography technique to form the semi-transparent film 32.

  In this embodiment, the resist material 200 is exposed using the halftone mask 30 having such a configuration, and then developed to form the resist mask 20 shown in FIG. For this reason, in the resist mask 20, the thick portion 20b of the resist mask 20 is formed in the region overlapping with the light shielding region 30b, and the resist mask 20 is not formed in the region overlapping with the entire light transmitting region 30a. Further, a thin portion 20c of the resist mask 20 is formed in a region overlapping with the semi-transparent region 30c, and an intermediate thickness between the thick portion 20b and the thin portion 20c of the resist mask 20 is formed in a region overlapping with the intermediate region 30d. The intermediate thickness portion 20d is formed. In this embodiment, the thickness of the thin portion 20c of the resist mask 20 is, for example, about 50 nm to 200 nm, and the thickness of the thick portion 20b of the resist mask 20 is, for example, 200 nm or more.

  In the resist mask 20 thus formed, the formation region of the resist mask 20 (the total region of the thick portion 20b, the thin portion 20c, and the intermediate thickness portion 20d) overlaps with the formation region of the island-shaped semiconductor film 1a. The thick portion 20b of the resist mask 20 overlaps the channel region 1b, the thin portion 20c of the resist mask 20 overlaps the source side high concentration impurity region 1c and the drain side high concentration impurity region 1d, and the intermediate thickness portion 20d of the resist mask 20 It overlaps with the concentration impurity region 1e and the drain side low concentration impurity region 1f.

  Next, in the patterning step, using the resist mask 20 as a mask, the semiconductor film 1 formed under the resist mask 20 is etched into a predetermined shape, and as shown in FIG. Is formed by patterning. As the etching method, various methods such as dry etching or wet etching can be applied.

Subsequently, in the impurity introduction step, as shown in FIG. 3E, high-concentration impurity ions (phosphorus ions) are, for example, 0.1 × 10 ¹⁵ to the semiconductor film 1a using the resist mask 20 as a mask. Implantation is performed at a dose of about 10 × 10 ¹⁵ / cm ² . As a result, in the thin portion 20c of the resist mask 20, high-concentration impurity ions are implanted in the semiconductor film 1a through the resist mask 20 in a high concentration state, and the source-side high-concentration impurity region 1c and the drain-side high-concentration impurity. Region 1d is formed. Further, in the portion 20b where the resist mask 20 is thick, high concentration impurity ions are blocked in the resist mask 20, and the impurity ions do not reach the region of the semiconductor film 1a, so that the channel region 1b is formed. Further, in the intermediate thickness portion 20d of the resist mask 20, a part of the high concentration impurity ions are blocked in the resist mask 20, and the low concentration impurity ions are implanted into the semiconductor film 1a. Region 1e and drain-side low concentration impurity region 1f are formed.

  Next, after removing the resist mask 20, in the gate insulating film forming step, as shown in FIG. 4A, the gate insulating film 2 is formed on the upper layer side of the semiconductor film 1a by plasma CVD, sputtering, or the like. .

  Next, in the gate electrode formation process, after forming a conductive film on the upper layer of the gate insulating film 2, the conductive film is patterned using a photolithography technique, and as shown in FIG. Scan lines 3a and capacitor lines 3b are formed. Here, the gate electrode 3g is formed in a region overlapping with the channel region 1b in the channel length direction. As a result, both end portions of the gate electrode 3g are positioned so as to overlap the boundary portion between the channel region 1b and the source-side low concentration impurity region 1e and the boundary portion between the channel region 1b and the drain-side low concentration impurity region 1f. In this way, a TFT 90 having a so-called LDD structure is formed. Moreover, since a well-known method can be employ | adopted for subsequent processes, those description is abbreviate | omitted.

(Main effects of this form)
As described above, in this embodiment, the half-tone mask 30 and the positive resist material 200 are used so that the portion overlapping the channel region 1b is thick, and the source-side high-concentration impurity region 1c and the drain-side high-concentration impurity region 1f. After forming the resist mask 20 having a thin portion overlapping with the semiconductor layer 1a, a high concentration impurity is introduced into the semiconductor film 1a through the thin portion 20c of the resist mask 20. As a result, no impurity is introduced into the portion 20b where the resist mask 20 is thick, and the channel region 1b is formed. On the other hand, a high concentration impurity is introduced into the portion 20c where the resist mask 20 is thin, and the source side high concentration impurity region is formed. 1c and drain side high concentration impurity region 1f are formed.

  Here, in the halftone mask 30, a semi-transparent film 32 is formed in a region adjacent to both end portions 31 a and 31 b of the light-shielding film 31, and the semi-transparent film 32 is at least of the light-shielding film 31. Since it is formed so as to cover the surfaces of the side end portions 31 a and 31 b, the semi-transparent film 32 is formed thick in the vicinity of both ends of the light shielding film 31. Therefore, when the resist mask 20 is formed, an intermediate thickness portion 20d is formed between the thick portion 20b and the thin portion 20c. Therefore, when a high concentration impurity is introduced through the thin portion 20c of the resist mask 20, the semiconductor film In 1a, a source-side low-concentration impurity region 1e and a drain-side low-concentration impurity region 1f are formed in a region overlapping the intermediate thickness portion 20d of the resist mask 20. Therefore, the channel region 1b, the source side high concentration impurity region 1c, the drain side high concentration impurity region 1f, the source side low concentration impurity region 1e, and the drain side low concentration impurity region 1f are formed by one impurity introduction step. This eliminates the need for a separate step of introducing low-concentration impurities. Therefore, since the number of impurity introduction steps can be reduced, the manufacturing cost of the element substrate 100 can be reduced.

  Further, in this embodiment, after the impurity introduction step, the resist mask 20 is removed, and then a gate insulating film forming step for forming the gate insulating film 2 is performed, so that the impurity is introduced without the gate insulating film 2 being interposed. Can do. Therefore, it is possible to avoid damage to the gate insulating film 2 when introducing impurities, so that it is possible to form the gate insulating film 2 having excellent insulation and the like, and to improve the reliability of the TFT 90. it can.

  Further, in this embodiment, after the resist mask forming step, a patterning step for patterning and forming the semiconductor film 1a using the resist mask 20 is performed. For this reason, since the resist mask 20 can be used in two processes, ie, a patterning process for forming the semiconductor layer 1a and an impurity introducing process, the resist mask forming process can be reduced once. In addition, a process associated with the resist mask forming process, for example, a process such as peeling of the resist mask 20 can be simultaneously reduced.

  The positions of the channel region 1b, source-side high concentration impurity region 1c, drain-side high concentration impurity region 1f, source-side low concentration impurity region 1e, and drain-side low concentration impurity region 1f in the patterned semiconductor film 1a are halftone. Since it is uniquely determined by the mask 30 (resist mask 20), the channel region 1b, the source side high concentration impurity region 1c, the drain side high concentration impurity region 1f, the source side low concentration impurity region 1e, and the drain side low in the semiconductor film 1a The positional accuracy of the concentration impurity region 1f is high.

  Further, in the halftone mask 30 of this embodiment, since the semi-transparent film 32 is formed on the translucent substrate 35 so as to cover the end portion of the light-shielding film 31, after the light-shielding film 31 is formed, A semi-transparent film 32 is formed thereon. Therefore, unlike the case where the formation position of the light-shielding film is aligned with the semi-transparent film after the semi-transparent film is formed on the translucent substrate 35, the semi-transparent film 32 is formed with respect to the light-shielding film 31. Since the formation positions only need to be aligned, the alignment between the light shielding film 31 and the semi-transparent film 32 is easy.

  Furthermore, since the halftone mask 30 does not have the semi-transparent film 32 between the light shielding film 31 and the translucent substrate 35, the problem described with reference to FIG. 7 does not occur. That is, when the resist mask 20 is formed by exposure and development using the halftone mask 30, the exposure light is reflected at the interface between the semitransparent film 32 and the translucent substrate 35 and the outer peripheral edge of the light shielding film 31. Exposure light does not wrap around the overlapping area. Accordingly, in the resist mask 30, the side surface of the thick portion 30b does not become a gently tapered inclined surface. Therefore, when the impurity is introduced, the impurity overlaps the end portion of the thick portion 30b of the resist mask 30. It is difficult to introduce. Therefore, since the high concentration impurity regions are not formed at both ends in the channel width direction of the channel region 1b of the TFT 90, the switching characteristics can be improved, for example, the off-leak current of the TFT 90 can be reduced.

[Embodiment 2]
5A to 5E show an island-shaped semiconductor film including a channel region, a high concentration impurity region, and a low concentration impurity region in the manufacturing process of the liquid crystal device according to Embodiment 2 of the present invention. It is process sectional drawing which shows the process until it forms. Since the basic configuration of this embodiment is the same as that of Embodiment 1, common portions are denoted by the same reference numerals and description thereof is omitted.

  In the first embodiment, the semiconductor film 1 is patterned into an island shape and then the impurity introduction step is performed. In this embodiment, after the impurity introduction step is performed, the semiconductor film 1 is patterned into an island shape.

  That is, in this embodiment, first, as shown in FIG. 5A, in the semiconductor film forming step, after the base protective film 12 and the semiconductor film 1 made of polycrystalline silicon are formed on the translucent substrate 10, As shown in FIG. 5B, in the resist mask formation step, the positive resist material 200 is exposed and developed with the halftone mask 30, and then the resist mask 20 shown in FIG. 5C is formed.

Next, as shown in FIG. 5D, in the impurity introduction step, high-concentration impurity ions (phosphorus ions) are, for example, 0.1 × 10 ¹⁵ to the semiconductor film 1 using the resist mask 20 as a mask. Implantation is performed at a dose of about 10 × 10 ¹⁵ / cm ² . As a result, in the semiconductor film 1, the source-side high concentration impurity region 1c and the drain-side high concentration impurity region 1d are formed in a region overlapping the thin portion 20c of the resist mask 20, and the resist mask 20 is overlapped in the region overlapping the thick portion 20b. A channel region 1b is formed, and a source side low concentration impurity region 1e and a drain side low concentration impurity region 1f are formed in a region overlapping the intermediate thickness portion 20d of the resist mask 20.

  Subsequently, in the patterning step, the semiconductor film 1 is etched into a predetermined shape using the resist mask 20 as a mask, and an island-shaped semiconductor film 1a is formed by patterning as shown in FIG. As the etching method, various methods such as dry etching or wet etching can be applied.

  The subsequent steps are the same as those in the first embodiment, such as the gate insulating film forming step and the gate electrode forming step described with reference to FIGS. To do.

  Also in this embodiment, as in the first embodiment, the resist mask 20 has an intermediate thickness portion 20d between the thick portion 20b and the thin portion 20c. When the concentration impurity is introduced, in the semiconductor film 1a, a source side low concentration impurity region 1e and a drain side low concentration impurity region 1f are formed in a region overlapping the intermediate thickness portion 20d of the resist mask 20. Accordingly, the channel region 1b, the source side high concentration impurity region 1c, the drain side high concentration impurity region 1f, the source side low concentration impurity region 1e, and the drain side low concentration impurity region 1f are formed by one impurity introduction step. Thus, the same effects as those of the first embodiment can be obtained, for example, that it is not necessary to separately perform a step of introducing a low concentration impurity.

[Embodiment 3]
FIG. 4C is a process cross-sectional view showing a gate electrode forming process in the manufacturing process of the liquid crystal device according to the third embodiment of the present invention. Since the basic configuration of this embodiment is the same as that of Embodiment 1, common portions are denoted by the same reference numerals and description thereof is omitted.

  In the first and second embodiments, the gate electrode 3g is formed in a region that completely overlaps the channel region 1b in the channel length direction to form the TFT 90 having the LDD structure. In this embodiment, as shown in FIG. Then, a TFT 90 having a GOLD structure is formed. That is, both end portions of the gate electrode 3g are respectively a boundary portion between the source side high concentration impurity region 1c and the source side low concentration impurity region 1e, and a boundary portion between the drain side high concentration impurity region 1d and the drain side low concentration impurity region 1f. The gate electrode 3g is opposed to the source-side low concentration impurity region 1e, the channel region 1b, and the drain-side high concentration impurity region 1d with the gate insulating film 2 interposed therebetween at a position overlapping the portion.

  Also in this embodiment, as in the first embodiment, the resist mask 20 has an intermediate thickness portion 20d between the thick portion 20b and the thin portion 20c. When the concentration impurity is introduced, in the semiconductor film 1a, a source side low concentration impurity region 1e and a drain side low concentration impurity region 1f are formed in a region overlapping the intermediate thickness portion 20d of the resist mask 20. Accordingly, the channel region 1b, the source side high concentration impurity region 1c, the drain side high concentration impurity region 1f, the source side low concentration impurity region 1e, and the drain side low concentration impurity region 1f are formed by one impurity introduction step. Thus, the same effects as those of the first embodiment can be obtained, for example, that it is not necessary to separately perform a step of introducing a low concentration impurity.

[Other embodiments]
It should be noted that the technical scope of the present invention is not limited to the above-described embodiments, and includes those in which various modifications are made to the above-described embodiments without departing from the spirit of the present invention. For example, in the above embodiment, a single gate structure TFT has been described as an example. However, the present invention may be applied to the manufacture of a TFT having a twin gate structure. In the above embodiment, the element substrate used in the active matrix electro-optical device is described as an example of the semiconductor device. However, the electro-optical device using an electro-optical material other than liquid crystal, for example, an element used in an organic electroluminescence display device. The present invention may be applied to the manufacture of a semiconductor device other than a substrate or an electro-optical device.

[Example of mounting on electronic devices]
With reference to FIG. 6, an electronic apparatus in which the above-described electro-optical device 150 is mounted will be described. FIG. 6A illustrates a configuration of a mobile personal computer including the electro-optical device 150. The personal computer 2000 includes an electro-optical device 150 as a display unit and a main body 2010. The main body 2010 is provided with a power switch 2001 and a keyboard 2002. FIG. 6B shows a configuration of a mobile phone provided with the electro-optical device 150. A cellular phone 3000 includes a plurality of operation buttons 3001, scroll buttons 3002, and an electro-optical device 150 as a display unit. By operating the scroll button 3002, the screen displayed on the electro-optical device 150 is scrolled. FIG. 6C shows the configuration of a personal digital assistant (PDA) to which the electro-optical device 150 is applied. The information portable terminal 4000 includes a plurality of operation buttons 4001, a power switch 4002, and the electro-optical device 150 as a display unit. When the power switch 4002 is operated, various types of information such as an address book and a schedule book are displayed on the electro-optical device 150.

  In addition to the electronic apparatus shown in FIG. 6, the electronic apparatus on which the electro-optical device 150 is mounted is a digital still camera, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, an electronic notebook, Examples include calculators, word processors, workstations, videophones, POS terminals, devices with touch panels, and the like. The electro-optical device 150 described above can be applied as a display unit of these various electronic devices.

It is an equivalent circuit diagram of the liquid crystal device to which the present invention is applied. (A), (b) is an enlarged plan view showing one dot of the element substrate used in the liquid crystal device to which the present invention is applied, and the liquid crystal device is cut at a position corresponding to the line AA ′. It is sectional drawing when doing. It is process sectional drawing which shows the manufacturing method of the liquid crystal device which concerns on Embodiment 1 of this invention. FIG. 4 is a process cross-sectional view of a process performed subsequent to the process shown in FIG. 3. It is process sectional drawing which shows the manufacturing method of the liquid crystal device which concerns on Embodiment 2 of this invention. It is explanatory drawing of the electronic device using the liquid crystal device which concerns on this invention. It is explanatory drawing which shows the impurity introduction method using the conventional halftone mask.

Explanation of symbols

1 ··· Semiconductor film before patterning, 1a ·· Island-like semiconductor film, 1b ·· Channel region, 1c ·· High concentration impurity region on source side, 1d ·· High concentration impurity region on drain side, 1e ·· Low on source side Concentration impurity region, 1 f... Drain side low concentration impurity region, 1 s .. source side,
1t... Drain side, 2 .. gate insulating film, 3 g .. gate electrode 3 g, 9 a .. pixel electrode, 20 .. resist mask, 20 b .. thick part of resist mask, 20 c .. thin part of resist mask, 20d..Intermediate thickness portion of resist mask, 30..Halftone mask, 30b..Light-shielding region, 30a..Totally light-transmitting region, 30c..Semi-transparent region, 30d..Intermediate region, 31..Light-shielding Film, 32 .. translucent film, 35 .. translucent substrate, 90 .. TFT, 100 .. element substrate (semiconductor device), 102 .. liquid crystal layer, 150 .. electro-optical device

Claims (5)

A semiconductor film in which a low concentration impurity region is formed between a channel region and a high concentration impurity region on the source side and the drain side, and a gate electrode facing at least the channel region via a gate insulating film A method of manufacturing a semiconductor device having a thin film transistor,
A semiconductor film forming step of forming a semiconductor film on the substrate;
The positive resist material applied on the upper layer side of the semiconductor film is exposed and developed using a halftone mask in which a light-shielding film and a semi-transparent film are each formed on a translucent substrate with a predetermined pattern, A resist mask forming step of forming a resist mask in which a portion overlapping the channel region is thick and a portion overlapping the high concentration impurity region is thin;
An impurity introduction step of introducing high-concentration impurities into the semiconductor film through a thin portion of the resist mask,
In the resist mask forming step, as the halftone mask, the semi-transparent films are respectively formed in regions adjacent to both end portions of the light-shielding film, and the semi-transparent film is at least the light-shielding film A method of manufacturing a semiconductor device, comprising using a mask formed so as to cover the surfaces of both end portions of the semiconductor device. After the impurity introduction step, the resist mask is removed,
2. The semiconductor device according to claim 1, wherein a gate insulating film forming step for forming the gate insulating film so as to cover the semiconductor film and a gate electrode forming step for forming the gate electrode are performed. Production method. After the resist mask forming step,
The method for manufacturing a semiconductor device according to claim 1, wherein a patterning step of patterning the semiconductor film using the resist mask is performed. An electro-optical device manufacturing method using the semiconductor device manufacturing method according to claim 1,
The method of manufacturing an electro-optical device, wherein the semiconductor device is an element substrate including each of a plurality of pixels including the thin film transistor and a pixel electrode electrically connected to the thin film transistor. In the halftone mask in which the light shielding film and the semi-transparent film are each formed on the translucent substrate with a predetermined pattern,
The semi-transparent films are respectively formed in regions adjacent to both end portions of the light shielding film,
The half-tone mask is characterized in that the semi-transparent film is formed so as to cover at least the surfaces of both end portions of the light-shielding film.

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