JPH0448654A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To enable lowering of gate leak current and electric resistance of a gate electrode by forming a polycrystalline silicon layer through a gate oxide film on a semiconductor substrate, by forming a high melting point metal silicide layer on the polycrystalline silicon layer, by forming a silicon oxide film directly thereon and by forming a layer insulating film on the silicon oxide film. CONSTITUTION:A polycrystalline silicon film 3 formed through a gate oxide film 2, a WSi film 4 formed on the polycrystalline silicon film 3, an oxide silicon film 12 formed on the WSi film 4, a thermal oxide film 10 formed on an N<+>-diffusion layer 8, a sidewall 7a formed at a sidewall part of the polycrystalline silicon film 3 and the WSi film 4, and a layer insulating film 13 formed to cover the heat oxide film 10, the sidewall 7a and the oxide silicon film 12 are formed on a silicon substrate. Oxidation of the WSi film 4 is prevented in a manufacture process by interposing the oxide silicon film 12 between the WSi film 4 and the layer insulating film 13. As a result, it is possible to effectively prevent a rise of electric resistance of a gate electrode and an increase of gate lead current.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a semiconductor device using a composite film consisting of a polycrystalline silicon layer and a high melting point metal silicide layer as a gate electrode. and its manufacturing method.

[Prior Art] Conventionally, a MOS type semiconductor device having an LDD structure using a composite film made of a high melting point metal film and a polycrystalline silicon film as a gate electrode is known. FIG. 3 is a sectional view showing a conventional MOS transistor using a gate electrode made of a high melting point metal film and a polycrystalline silicon film. Referring to FIG. 3, the MOS transistor includes a silicon substrate 1, an N+ diffusion layer 8 formed at a predetermined interval on the main surface of the silicon substrate 1, a portion that will become the channel region of the transistor, and an N+ diffusion layer 8 formed on the main surface of the silicon substrate 1 at a predetermined interval. The polycrystalline silicon film 3 is formed between the N- diffusion layer 6 formed at the boundary with the layer 8 and the adjacent N+ diffusion layer with a gate oxide film interposed therebetween, and the polycrystalline silicon film 3 formed on the polycrystalline silicon film 3. Thermal oxide film 10 formed on WSiSiB6N+ diffusion layer 8, polycrystalline silicon film 3 and WS
A side wall 7a formed on the iSiB6 wall portion,
W is provided in the interlayer insulating film 13 formed to cover the entire surface and in the contact hole formed in the interlayer insulating film 13.
It includes an aluminum wiring 14 for making SiSiB6 gaseous contact.

4A to 4E are cross-sectional structural views for explaining the manufacturing process of the MOS transistor shown in FIG. 3. FIG. The manufacturing process will now be described with reference to FIGS. 3 to 4E. First, as shown in Figure j@4A, a gate oxide film 2 of about 200 Å is formed on the main surface of a silicon substrate 1, and then a polycrystalline silicon film 3 of about 200 OA is formed by the CVD method and doped with phosphorus. do. Then, using the sputtering method, WSiSi of about 3000A was
B6 is completed. Next, as shown in FIG. 4B, after forming a photoresist 5 in a desired shape using photolithography, using the photoresist 5 as a mask, the WSiSiB 6 and polycrystalline silicon film 3 are etched by a dry etching method using plasma. Etch sequentially. As a result, a polycrystalline silicon film 3 and a gate electrode made of WSiSiB6 are formed.

Then, as a photoresist 5 or WSiSiB6 mask, 1 to 5 x 1013 (c
m-2) to form an N- diffusion layer 6 having an LDD structure. Next, as shown in FIG. 4C, a CVD oxide film 7 of 2000 to 3000 Å is formed over the entire surface by CVD method 1. Here, when forming the CVD oxide film 7, the temperature is 850°C ~
Because heat treatment is performed at 900°C, WSiSiB6, which was in an amorphous state before forming the CVD oxide film 7,
The growth of W crystals (hereinafter referred to as grains) progresses. As a result, a collection of W grains of about 500 to 1500 A is formed, and surplus Si is collected therebetween. Next, as shown in FIG. 4D, by etching the CVD oxide film 7 using an anisotropic oxide film dry etching method, a side wall 7a is formed on the side wall of the gate electrode made of WSiSiB6 and polycrystalline silicon film 3. do.

Here, when the CVD oxide film 7 is etched, C
Etching is performed by an amount equivalent to the film thickness of the VD oxide 117 and an overetch amount of 10 to 20%. And WStSiB4
Using the side wall 7a as a mask, approximately 3 to 5×101O (am−2) of As was implanted by ion implantation.
An N+ diffusion layer 8 is formed.

Next, as shown in FIG. 4E, in order to make the N+ diffusion layer 8 an electrically active layer, the temperature was increased to 850°C to 95°C in an N2 atmosphere.
Heat treatment is performed at 0°C. Thereafter, heat treatment is performed at 850 DEG C. to 950 DEG C. in an 02 atmosphere to form a thermal oxide film 10 in order to cover the gate electrode with a thermal oxide film. Thereafter, as shown in FIG. 3, an interlayer insulating film 13 is formed by the CVD method, contact holes are formed in the interlayer insulating film 13, and A (wiring is performed).Thus, an N-channel MOS transistor is completed. .

[Problem to be solved by the invention] As mentioned above, WSiSiB, which is a conventional high melting point metal film,
MOS using a composite film consisting of 6 and polycrystalline silicon films 3
) In the transistor, as explained in FIG. 4D, when forming the sidewall 7a, the CVD oxide film 7 (the fourth C
(see figure) was etched by an anisotropic oxide film dry etching method to cover an amount equivalent to the thickness of the CVD oxide film 7 and an overetch amount of 10 to 20%. However, during this overetching, the surface of the WS i film 4 is struck by the plasma and the Si that had filled in between the grains is removed.
Since the natural oxide film is etched, the W grains are exposed. In this state, when heat treatment is performed in the 02 atmosphere as explained in Fig. 4E,
Oxygen is supplied along the grain boundaries of the grains exposed on the WSiSiB6 surface, and excess Si and W existing between the grains is oxidized. As a result, a WSi abnormal oxide film 9 consisting of 5i02 is formed or WO is sublimated.

Further, since Si is supplied as an oxidizing agent from the polycrystalline silicon film 3 based on WSiSiB6, the thickness of the polycrystalline silicon film 3 is locally reduced, and WSiSiC2 intrudes into the region. As a result, stress is applied to the gate oxide film 2, resulting in an increase in gate leakage current.

In other words, the conventional gate electrode is made of a high melting point metal film (WSiSi).
L using a composite film consisting of C2 and polycrystalline silicon film 3
In a MOS transistor with a DD structure, there is a problem that oxidation of the WSiSiC2 surface progresses during the manufacturing process, increasing the resistance value of WSiSiC2 constituting the gate electrode. The Si inside the WSiSiC2 is raised as an oxidizing agent, and the polycrystalline silicon film 3 is locally reduced in thickness, and it bites into the WSiSiC2 crystalline silicon film 4, which puts stress on the gate oxide film 2 and increases gate leakage current. There was a problem with the increase.

The present invention was made in order to solve the above-mentioned problems, and provides a semiconductor device and a method for manufacturing the same that can reduce the electric pulse resistance of a gate electrode and reduce gate leakage current. The purpose is to

[Means for Solving the Problems] The semiconductor device according to the first claim includes a polycrystalline silicon layer formed on a semiconductor substrate via a gate oxide film, and a high melting point metal silicide formed on the polycrystalline silicon layer. a silicon oxide film formed directly on the refractory metal silicide, and an interlayer insulating layer formed on the silicon oxide film.

A method for manufacturing a semiconductor device according to a second aspect includes the steps of: forming a gate oxide film and a polycrystalline silicon layer on a semiconductor substrate, and then introducing impurities into the polycrystalline silicon layer;
A high melting point metal silicide layer is formed on the polycrystalline silicon layer by sputtering, and immediately after that, the entire high melting point metal silicide layer is etched into a silicon oxide layer by a subsequent thermal oxidation process to form a contact hole. forming an amorphous silicon layer having a thickness varying in thickness by sputtering.

[Function] In the semiconductor device according to the first aspect, a polycrystalline silicon layer is formed on the semiconductor substrate via a gate oxide film, a high melting point metal silicide layer is formed on the polycrystalline silicon layer,
A silicon oxide film is formed directly on the high melting point metal silicide layer, and an interlayer insulating film is formed on the silicon oxide film. In addition to preventing oxidation of the high melting point metal silicide layer that constitutes the
Silicon in the polycrystalline silicon layer is also not sucked up.

In the method for manufacturing a semiconductor device according to the second aspect, after a gate oxide film and a polycrystalline silicon layer are formed on a semiconductor substrate, an impurity is introduced into the polycrystalline silicon layer, and a sputtering method is applied to the polycrystalline silicon layer. A high melting point metal silicide layer is formed, and immediately after that, a thermal oxidation process is performed on the high melting point metal silicide layer to form a contact hole. Since the silicon layer is formed by sputtering, the amorphous silicon layer prevents oxidation of the high melting point metal silicide layer, and the manufacturing process for forming contact holes does not become complicated.

[Embodiments of the invention] Embodiments of the present invention will be described below based on the drawings.

FIG. 1 shows an M using a gate electrode according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing an OS transistor.

Referring to FIG. 1, a MOS transistor includes a silicon substrate 1, an N+ diffusion layer 8 formed on the silicon substrate 1 at a predetermined interval, and two adjacent N+ diffusion layers 8 forming a channel region. A gate oxide film 2 is formed between the N- diffusion layer 6 formed in the boundary region with the part and the adjacent N1 diffusion layer 8.
A polycrystalline silicon film 3 formed through the polycrystalline silicon film 3, a silicon oxide film 12 formed on WSiSiC2WSiSi formed on the polycrystalline silicon film 3, and a thermal oxide film 10 formed on the N+ diffusion layer 8. Polycrystalline silicon film 3 and W
A sidewall 7a formed on the wall portion of the SiSi 20, an interlayer insulating film 13 formed to cover the thermal oxide film 10, the sidewall 7a, and the silicon oxide film 12.
and an aluminum wiring 14 provided in a contact hole formed in an interlayer insulating film 13.

In this example, the WS forming the gate electrode as described above is
By interposing the silicon oxide film 12 between the iSi 20 insulating film 13, WSiSi2
As a result, it is possible to effectively prevent an increase in the electric resistance of the gate electrode and an increase in gate leakage current, which have conventionally caused problems due to oxidation of the WSi film 4.

28 to 2E are cross-sectional structural views for explaining the manufacturing process of the MOS transistor shown in FIG. 1. The manufacturing process will be described with reference to FIGS. 1 to 2E. First, as shown in FIG. 2A, a gate oxide film 2 with a thickness of about 200 A is formed on the main surface of a silicon substrate 1, and then a polycrystalline silicon film 3 of about 2000 A is formed by the CVD method, and phosphorus is removed. Dope. Then, using sputtering method etc., 3000 WSiSi20
After that, an amorphous silicon film 11 having a thickness of about 100 to 300 octane is formed by sputtering.

Next, as shown in FIG. 2B, the amorphous silicon film 11, WSiSi 20, and polycrystalline silicon film 3 are sequentially etched using the photoresist 5 formed into a desired shape using photolithography as a mask. This results in
A gate electrode made of polycrystalline silicon film 3 and WSiSi 20 is formed. Then, using the photoresist 5 or the gate electrode as a mask, 1 phosphorus P is added by ion implantation.
About 5×10” [cm −2 ] is implanted to form an N − diffusion layer 6 having an LDD structure.Next, as shown in FIG. 2C, a CVD oxide film 7 is formed on the entire surface by the CVD method.

The heat treatment during the formation of the CVD oxide film 7 causes the grains of the WSi film to grow as in the conventional case. Next, the second
As shown in Figure D, the CVD oxide film 7 is etched by an anisotropic dry etching method to a portion corresponding to the thickness of the CVD oxide film 7 and an overetch amount of 10 to 20% of the thickness of the CVD oxide film 7, thereby forming a WSiSi20 crystal. Sidewalls 7a are formed on the sidewalls of the gate electrode made of silicon film 3. Here, in this example, since the WSiSi 20 surface is protected by the amorphous silicon film 11,
Since the WSiSi 20 surface is not directly struck during over-etching of the CVD oxide film 7 (see FIG. 2C) as in the prior art, the W grains are not exposed. After that, using the gate electrode and the sidewall 7a as a mask, As is deposited in the amount of 3 to 5 x 10'' Cam- by ion implantation.
2] to form an N+ diffusion layer 8. Next, the second
As shown in Fig. E, in order to make the N+ diffusion layer 8 an electrically active layer, heat treatment is performed at 850 to 950° C. in an N2 atmosphere. After that, to cover the gate electrode with a thermal oxide film,
Heat treatment at 850°C to 950°C in 02 atmosphere,
A thermal oxide film 10 is formed. At this time, the amorphous silicon film 11 is also oxidized and becomes a silicon oxide film 12. The thickness of the silicon oxide film 12 is determined by the amount of oxidation during the formation of the thermal oxide film, but if the thickness of the amorphous silicon film 11 is set in advance to be equal to or greater than the amount of oxidation, WSi
Si20 is not oxidized.

As a result, WSi! The electrical resistance of the gate electrode of which 14 is a constituent part does not become high, and the electrical resistance of the gate electrode can be lowered compared to the conventional one. In addition, when forming a thermal oxide film, 5i75<WS i film 4 is used as an oxidized agent.
Since it exists as an amorphous silicon film on the surface of the electrode, the 81 is not sucked up from the underlying polycrystalline silicon film 3 (unlike in the conventional case, the gate oxide film is stressed and the gate leakage current increases). do not have. Therefore, gate leakage current can be reduced compared to the conventional method. After the manufacturing process explained in FIG. 2E, the interlayer insulating film 13 is finally formed by the CVD method as shown in FIG.
Heat treatment is performed at 900°C to 950°C in a 102 atmosphere. At this time, the amorphous silicon film 11 is completely oxidized and becomes a silicon oxide film 12. Thereafter, a contact hole is formed in the interlayer insulating film 13 using photolithography, but in the oxide film etching process for forming this contact hole, the silicon oxide film 12 on WSiSi is also used in the same way as the interlayer insulating film 13. etched into WSi
The SiO2 surface is exposed. That is, in this embodiment, WS
The amorphous silicon film 11 provided to prevent oxidation on the iSiO2 surface has completely changed to a silicon oxide film 12 when the contact hole is formed, and if the contact hole is formed in this state, the etching process is divided into two steps. It is not necessary and the manufacturing process will not be complicated.

Finally, All interconnection 14 is provided in the contact hole formed in interlayer insulating film 13 to complete the MOS transistor.

Note that in this example, WSiSi is used as the high melting point metal film.
Although O2 was used, the present invention is not limited to this, and similar effects can be obtained when other high melting point metal films such as MoSi are used. Further, in this embodiment, an example in which the present invention is applied to the gate electrode of a MOS transistor is shown, but the present invention is not limited to this, and the effect of lowering the electrical resistance value can be obtained when applied to wiring or the like.

[Effects of the Invention] According to the invention described in the first claim, a polycrystalline silicon layer is formed on a semiconductor substrate via a gate oxide film, and a high melting point metal silicide layer is formed on the polycrystalline silicon layer. , a silicon oxide film is formed directly on the high melting point metal silicide layer, and an interlayer insulating layer is formed on the silicon oxide film. In this process, the high melting point metal silicide layer constituting the gate electrode is prevented from being oxidized, and the silicon in the polycrystalline silicon layer is not sucked up, so the electrical resistance of the gate electrode can be lowered and the gate leakage current can be reduced. We have now been able to provide a semiconductor device that can reduce the power consumption.

According to the second aspect of the invention, after forming a gate oxide film and a polycrystalline silicon layer on a semiconductor substrate, impurities are introduced into the polycrystalline silicon layer, and the polycrystalline silicon layer is heated by sputtering. forming a melting point metal silicide layer,
Immediately thereafter, an amorphous silicon layer is formed on the high melting point metal silicide layer by a sputtering method, and has a thickness such that the entire layer changes into a silicon oxide layer during etching of the oxide film for forming contact holes in a subsequent thermal oxidation process. As a result, oxidation of the high melting point metal silicide layer is prevented by the amorphous silicon layer, making it possible to lower the electrical resistance of the gate electrode and gate leakage current. It doesn't get complicated either.

[Brief explanation of drawings]

FIG. 1 shows an M using a gate electrode according to an embodiment of the present invention.
Cross-sectional views showing OS transistors, Figures 2A to 2
Figure E is a cross-sectional structural diagram for explaining the manufacturing process of the MOS transistor shown in Figure 1, and Figure 3 shows a MOS transistor using a conventional gate electrode made of a high melting point metal film and a polycrystalline silicon film. The cross-sectional views, FIGS. 4A to 4E, are cross-sectional structural views for explaining the manufacturing process of the MOS transistor shown in FIG. 3. In the figure, 1 is a silicon substrate, 2 is a gate oxide film, and 3 is a silicon substrate.
4 is a polycrystalline silicon film, 4 is a WSi film, 5 is a photoresist, 6 is an N- diffusion layer, 7 is a CVD oxide film, 7a is a sidewall, 8 is an N+ diffusion layer, 9 is a WSi abnormal oxide film, 10
11 is a thermal oxide film, 11 is an amorphous silicon film, 12 is a silicon oxide film, 13 is an interlayer insulating film, and 14 is an aluminum wiring. Note that in each figure, the same reference numerals indicate the same or corresponding parts. 13... Interlayer insulating film 14... Aluminum wiring Figure 2B Figure 4A Figure 4B Figure 2C Figure 2D Figure 2E δ Figure 4C Figure 4D Figure 4E Display of the incident Invention Person amending the name Relationship with the case Address Name Representative 4, Agent address Procedure amendment (voluntary) 1990 Patent Application No. 156200 Semiconductor device and its manufacturing method

Claims (2)

[Claims] (1) A polycrystalline silicon layer formed on a semiconductor substrate via a gate oxide film, a high melting point metal silicide layer formed on the polycrystalline silicon layer, and a high melting point metal silicide layer formed directly on the high melting point metal silicide layer. A semiconductor device comprising: a silicon oxide film; and an interlayer insulating layer formed on the silicon oxide film. (2) After forming a gate oxide film and a polycrystalline silicon layer on a semiconductor substrate, introducing impurities into the polycrystalline silicon layer, and forming a high melting point metal silicide layer on the polycrystalline silicon layer by sputtering. Immediately thereafter, an amorphous silicon layer is formed on the high-melting point metal silicide layer by sputtering, and the amorphous silicon layer has such a thickness that the entire layer changes into a silicon oxide layer when the oxide film is etched to form a contact hole in a subsequent thermal oxidation process. A method of manufacturing a semiconductor device, the method comprising: