JPH08181218A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE: To avoid lowering of the punch-through breakdown strength of a parasitic transistor in a semiconductor device, in which an intermediate breakdown strength transistor and a low-voltage transistor are formed on a common semiconductor substrate. CONSTITUTION: In a semiconductor device, in which a low-voltage transistor and an open drain type intermediate breakdown strength transistor 22 are formed on a semiconductor substrate 21, each gate insulating film of the intermediate breakdown strength transistor 22 and the low-voltage transistor 47 is composed of gate insulating films 23 having the same constitution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a low voltage transistor and a medium voltage transistor having a so-called open drain structure on a common semiconductor substrate, and a manufacturing method thereof.

[0002]

2. Description of the Related Art Microcontrollers are so-called I /
An external device such as a liquid crystal display device, a fluorescent display tube or a servomotor is controlled through an O (input / output) port. This I / O port is
A high breakdown voltage transistor is used so as not to be destroyed even if an external high voltage is directly applied.

By the way, in order to control an external device such as a liquid crystal display device or a servomotor, for example, an n-channel type medium breakdown voltage insulated gate (MOS) transistor (hereinafter referred to as a medium breakdown voltage transistor) of about 12 V is required. These medium voltage transistors are called open drain type because the drain terminals are not connected on the semiconductor chip. By forming these medium-voltage transistors on the same semiconductor chip as the CPU (Central Processing Unit) and the logic, the added value of the microcontroller is increased.

FIG. 8 is a schematic sectional view of an NOD (n-channel offset drain) type open drain type medium breakdown voltage transistor. In this transistor,
In addition to the transistor formation portion on the surface of the silicon semiconductor substrate 1, local thermal oxidation, so-called LOCOS (Local Oxidation of S
The element isolation insulating layer 2 is formed by the silicon, and the SiO ₂ gate insulating film 3 is formed by surface thermal oxidation in the formation portion of the medium breakdown voltage transistor. In addition, a p-type well region 4 is formed by ion implantation in the formation portion of the medium breakdown voltage transistor of the silicon semiconductor substrate 1, and, for example, a channel stop region 5 ion-implanted by the same mask as the ion implantation of the well region 4 is formed. It is formed.

A gate electrode 6 is formed on the gate insulating film 3. This gate electrode 6 is formed by forming a refractory metal layer 6B on an impurity-doped polycrystalline silicon layer 6A, for example. By using this gate electrode 6 as a mask, low concentration regions 7s and 7d of the source and drain are formed by ion implantation so as to face the substrate surface on the well region 4. Further, a source region and a drain region in which high concentration regions 8s and 8d are formed on both sides of the formation portion of the gate electrode 6 via low concentration regions 7s and 7d are formed.

Below the gate electrode 6, a threshold voltage V _th adjusting region (hereinafter referred to as V / A region) 9 is formed which is doped with impurities by ion implantation.

FIG. 9 is a schematic sectional view of an LOD (LOCOS offset drain) type medium withstand voltage transistor. In FIG. 9, parts corresponding to those in FIG.

By the way, conventionally, the manufacturing of the medium withstand voltage transistor portion is carried out by an original process. Therefore, the microcontroller including the medium withstand voltage transistor has a large number of manufacturing steps, and the cost is low. There is a problem that is high. That is, in this medium breakdown voltage transistor, it is necessary to increase the thickness of the gate insulating film so that the gate insulating film is not destroyed even if a high voltage is directly applied to the gate insulating film. Therefore, it is necessary to take a unique and complicated additional process for forming the gate insulating film of the medium voltage transistor.

An additional process for forming this medium breakdown voltage transistor will be described with reference to FIGS. 10A to 11B. In this case, as shown in FIG. 10A, for example, a thick element is formed between the formation portions of the respective transistors of the silicon semiconductor substrate 1 to be formed separately from each other, such as the low voltage transistor to which the low voltage V _cc is applied and the medium withstand voltage transistor. The isolation insulation layer 2 is locally thermally oxidized so-called LOCOS (Local Oxidation of Sil
icon)). Then, the surface of the silicon semiconductor substrate 1 of the transistor formation portion separated by the element isolation insulating layer 2 in which the element isolation insulating layer 2 is not formed is thermally oxidized to form the first oxide film 11.

As shown in FIG. 10B, a photoresist 10 covers the formation portion of the medium breakdown voltage transistor.

As shown in FIG. 11A, photoresist 1
Using 0 as an etching mask, the first oxide film 11 on the formation portion of the low voltage transistor is removed by etching.

As shown in FIG. 11B, photoresist 1
0 is removed, and the surface of the silicon semiconductor substrate 1 is again thermally oxidized to form the second oxide film 12. This way,
The second oxide film 12 is formed on the surface of the low voltage transistor formation portion.
The thin gate insulating film of the low voltage transistor is formed only by the
And a thick gate insulating film is formed by superimposing the second oxide films 11 and 12.

As described above, when the low voltage transistor and the medium breakdown voltage transistor are formed on the common semiconductor substrate 1, the second oxide film 12 is selected to form each gate insulating film of each transistor. A step of forming a photoresist 10 having a predetermined pattern to be formed at a position, a step of etching the first oxide film 11 using the photoresist 10 as a mask, and a step of forming a second oxide film 12 are added. However, the increase of the etching process and the second oxide film process remarkably complicates the work and hinders mass productivity.

Further, in the case of this method, part of the element isolation insulating layer 2 is etched in the etching step of FIG. 11A, so that the part 2 of the element isolation insulating layer 2 is etched.
Since a becomes thin, the threshold voltage V _th of the parasitic transistor in the low-voltage transistor finally formed
And the punch-through breakdown voltage is lowered.

[0015]

SUMMARY OF THE INVENTION The present invention is intended to solve the above-mentioned problem of reduction in punch-through breakdown voltage of a parasitic transistor in a semiconductor device in which a medium breakdown voltage transistor and a low voltage transistor are formed on a common semiconductor substrate.

[0016]

According to the first aspect of the present invention, as shown in a schematic sectional view of an example thereof in FIG. 1, a low voltage transistor (a p-channel low voltage transistor in the example shown in FIG. 1 is provided on a semiconductor substrate 21. 47) and the open drain type medium-voltage transistor 22 are formed,
The gate insulating films of the medium breakdown voltage transistor 22 and the low voltage transistor 47 are formed by the gate insulating film 23 having the same structure.

The second aspect of the present invention is, for example, in a method of manufacturing a semiconductor device in which a low voltage transistor such as a p-channel low voltage transistor 47 and an open drain type medium withstand voltage transistor 22 are formed on a semiconductor substrate 21 shown in FIG.
The medium voltage transistor and each gate insulating film 23 of the low voltage transistor are simultaneously formed.

The third aspect of the present invention employs, in the above-described production method of the present invention, an ion implantation step of setting the impurity concentration on the gate side of the drain region of the medium breakdown voltage transistor 22 to a predetermined concentration.

[0019]

According to the above-mentioned device of the present invention, since the medium breakdown voltage transistor 22 and each gate insulating film 23 of the low-voltage transistor have the same structure, that is, the same material and thickness, the above-mentioned manufacturing method of the present invention. Since each of the gate insulating films 23 can be formed in the same step as described above, two times for forming the gate insulating film of the low voltage transistor and the gate insulating film of the medium withstand voltage transistor as in the above-described conventional method. It is possible to avoid the necessity of the oxidation step for forming the gate insulating film, and to avoid the step of etching away a part of the gate insulating film in the formation portion of the low voltage transistor.

Further, it is possible to prevent a part of the element isolation insulating layer from becoming thin due to this etching.

In the above-mentioned third invention,
The concentration of the drain side of the medium breakdown voltage transistor on the gate side is set by adding an ion implantation step.
That is, the concentration adjusting region 33 is formed on the gate side of the drain region in this manner, and by doing so, as will be described later, the gate insulating film 23 of the medium breakdown voltage transistor 22 is formed at a low voltage. It is possible to sufficiently maintain the withstand voltage of the medium withstand voltage transistor 22 in spite of the same configuration and the same forming process as the gate insulating film of the transistor.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the manufacturing method of the present invention for obtaining an embodiment of a semiconductor device according to the present invention will be described with reference to the process diagrams of FIGS.

In this example, the common semiconductor substrate 21 has n
This is a case where the present invention is applied to a semiconductor device in which a channel low-voltage transistor, a p-channel low-voltage transistor, and an open drain type n-channel medium withstand voltage transistor are formed.

First, as shown in FIG. 2A, for example, a silicon semiconductor substrate 21 having a p-type specific resistance of 8 to 12 Ωcm is prepared, and on one main surface thereof, between the formation parts of the respective circuit elements (in this example, the above-mentioned parts are formed). Of the transistor) and, in this example, the element isolation insulating layer 26 is formed in a portion other than the wiring contact portion of the drain formation portion in the formation portion of the open drain type n-channel medium withstand voltage transistor. . This element isolation insulating layer 26 is formed by, for example, C on the main surface of the semiconductor substrate 21 by a normal LOCOS.
SiN serving as a mask for thermal oxidation is entirely formed by a VD (Chemical Vapor Deposition) method, and the portion for forming the element isolation insulating layer 26 is removed by selective etching by photolithography to remove the SiN layer. The oxidation-resistant mask is formed of, for example, SiO ₂ having a thickness of 400 to 500 nm formed by thermally oxidizing the semiconductor substrate 21. That is, the element isolation insulating layer 26 has a pattern in which an opening is formed in the formation portion of each transistor and an opening 26C is formed in the contact portion. After that, the oxidation-resistant mask is removed, and the surface of the semiconductor substrate 21 exposed to the outside by this removal is further thermally oxidized, for example, a so-called sacrificial oxide film having a thickness of 40 nm for protecting the surface from damage at the time of ion implantation performed later. 28 is formed.

As shown in FIG. 2B, an n-channel low voltage transistor
The formation area of the transistor and the source area of the medium voltage transistor
P-type well region in each of the region and the channel formation portion
29 and 30 selectively, for example boron B⁺From 300
5 × 10 at 400 keV¹²~ 1 × 10¹³cm^-2The dose of
Simultaneously formed by ion implantation in a quantity. In addition,
Well region using the same mask as the mask for forming the region 30
A channel stop region 31 is formed on the region 30, for example,
B⁺5 to 10 at 100 to 120 keV¹¹~ 2 x 1
0¹²cm^-2Is formed by ion implantation with a dose amount of. Again
In the channel forming part of the withstand voltage transistor,
Threshold voltage V_thAdjusting V / A area 32
Byron B⁺At 20 to 30 keV and 1 × 10¹²~ 4x
10¹²cm ^-2Formed by ion implantation at a dose of
It

On the other hand, the n-type well region 34 and the drain region 24 are selectively formed under the element isolation insulating layer 26 in the p-channel low-voltage transistor forming portion and the drain region forming portion of the medium breakdown voltage transistor, respectively. , Phosphorus P ⁺ at 300 to 500 keV, 8 × 10 ¹² to 1 ×
It is formed by ion implantation with a dose amount of 10 ¹³ cm ^-2 .

After that, sufficient annealing is performed in a nitrogen atmosphere at 800 to 900 ° C. to activate each ion-implanted impurity.

As shown in FIG. 3A, the sacrificial oxide film 28 is removed so that the removed portions, that is, the n-channel and p-channel low-voltage transistor forming portions and the medium-voltage transistor forming portions are simultaneously formed with the same material. , The gate insulating film 23 having the same structure depending on the thickness is formed. The gate insulating film 23 can be formed by a silicon oxide SiO ₂ film formed by thermally oxidizing the surface of the substrate 21 by thermal oxidation in a wet atmosphere.

As shown in FIG. 3B, n channel and p
Gate electrodes 35, 36, and 37 of the respective transistors are formed on the gate insulating film 23 in the low voltage transistor forming portions of the channels and the intermediate breakdown voltage transistor forming portions, respectively. The gate electrodes 35, 36 and 37 are formed by sequentially forming a polycrystalline semiconductor layer 38 made of polycrystalline silicon and a refractory metal layer 39 made of WSi or the like, and patterning them by photolithography to form a so-called polycide structure. As a result, it is possible to reduce the specific resistance.

Next, although not shown, first, for example, a p-channel transistor forming portion is covered with photoresist or the like, and the gate electrodes 35 and 3 are formed in the n-channel low-voltage transistor forming portion and the medium-voltage transistor forming portion.
7 and the element isolation insulating layer 26 as a mask, ion implantation of impurities is carried out to lower the source and drain regions (hereinafter referred to as S / D regions) of the n-channel low-voltage transistor finally obtained as shown in FIG. The low concentration region 2 of the source region of the medium breakdown voltage transistor is formed while the concentration region 40a is formed.
7a is formed. Next, for example, the formation portion of the n-channel low-voltage transistor and the formation portion of the medium breakdown voltage transistor are covered with, for example, photoresist, and the gate electrode 36 and the element isolation insulating layer 26 are formed in the formation portion of the p-channel low-voltage transistor. S / D of p-channel low-voltage transistor finally obtained by performing impurity ion implantation using
The low concentration region 41a of the region is formed.

After that, on the gate side of the drain region 24 of the medium breakdown voltage transistor, this drain region 24 is used in this example.
Selectively, for example, phosphorus P through the upper element isolation insulating layer 26.
⁺ Is 100 to 150 keV and 5 × 10 ^{12 to} 810 ¹² cm
Ion implantation is performed with a dose amount of ^-2 to form a drain concentration adjustment region 33.

Similarly, as shown in FIG. 4, sidewalls 42 are formed on both side surfaces of the gate electrodes 35, 36 and 37, respectively. The sidewalls 42 are formed by a well-known method, for example, SiO ₂ is formed by a CVD method, and each gate electrode 35, 3 is formed by dry etching showing anisotropic etching in a direction orthogonal to the substrate surface.
It can be formed by leaving a portion where the substantial thickness of both side surfaces of 6 and 37 is substantially large and removing the other portions.

Next, although not shown, for example, the p-channel transistor forming portion is covered with photoresist or the like, and the gate electrodes 35 and 37 are formed in the n-channel low-voltage transistor forming portion and the medium-voltage transistor forming portion, respectively.
By using the sidewall 42 and the element isolation insulating layer 26 as a mask, ion implantation of impurities is performed to form a high-concentration S / D region 40 of the n-channel low-voltage transistor finally obtained as shown in FIG. At the same time, the high-concentration source region 27 of the medium breakdown voltage transistor is formed. Then, for example, n
The formation portion of the channel low-voltage transistor and the formation portion of the medium breakdown voltage transistor are covered with, for example, photoresist, and the gate electrode 36 thereof, the sidewall 42 thereof, and the element isolation insulating layer 26 are formed in the formation portion of the p-channel low-voltage transistor. Ion implantation of impurities with and as a mask,
As shown in FIG. 4, a wiring contact portion 25 of a high impurity concentration region is formed below the source region 27 of high concentration of the n-channel medium withstand voltage transistor finally obtained and the opening 26C outside the drain region 24 thereof.

After that, as shown in FIG.
An interlayer insulating layer 43 made of, for example, SiO ₂ is formed by the D method or the like, and a contact window is formed in this interlayer insulating layer 43 at the lead-out portion of the wiring (electrode) of each transistor by etching by photolithography. 44 is ohmic-contacted with a predetermined portion of each transistor. The wiring 44 is formed, for example, by depositing a metal layer of Al on the entire surface by vapor deposition, sputtering, etc., and simultaneously forming a predetermined pattern by pattern etching by photolithography.

As shown in FIG. 6, the protective insulating layer 4 is entirely covered.
Coat 5. In this way, the common semiconductor substrate 21
Then, a semiconductor device in which the n-channel low-voltage transistor 46, the p-channel low-voltage transistor 47, and the n-channel open-drain medium withstand voltage transistor 22 are formed is obtained.

The open drain type medium withstand voltage transistor 22 according to the present invention has the same structure in which the gate insulating film 23 is simultaneously formed by the same gate insulating film 23 as the other low voltage transistors 46 and 47.

As described above, in the present invention, the gate insulating film 23 of the medium breakdown voltage transistor 22 is formed by the same thin gate insulating film as in the low voltage transistor. The required breakdown voltage can be sufficiently ensured.

That is, in the open drain type medium withstand voltage transistor, the electric field strength of 5 MV / cm or less is maintained in order to maintain the withstand voltage on the drain side of the gate portion. For this reason, the concentration on the drain side, that is, the final impurity concentration on the gate side of the drain region, that is, the substrate concentration over this portion, for example, the V / A region 32 in which ions are implanted, the channel stop region 31, the well region 30, the drain region Ion implantation conditions for forming the concentration adjustment region 33 are selected so that the substantial n-type concentration including the superposition of 24 is 1 × 10 ^{17 to} 5 × 10 ¹⁷ atoms / cm ³ .

Table 1 below shows the potential in the vicinity of the gate insulating film on the drain side of the gate insulating film (oxide film) when the gate voltage Vg is changed with the drain voltage Vd = 15V in the above-mentioned medium withstand voltage transistor according to the present invention. , Shows the position where the maximum electric field in the same gate insulating film (oxide film) and the same electric field in the oxide film have a peak. As is clear from this, the electric field applied to the gate insulating film is V
0.54MV / cm at maximum when d = 15V and Vg = 0V
Which is 2.9 at the maximum when Vd = 15V and Vg = 5V.
MV / cm, which is sufficiently lower than the electric field of 5 MV / cm at which breakdown occurs.

[0040]

[Table 1]

As described above, according to the device of the present invention and the manufacturing method thereof, the gate insulating films of the low-voltage transistor and the medium-voltage transistor can be simultaneously formed to have the same structure, that is, the same film thickness. In addition, it is possible to avoid the complicated work when the gate insulating film of the medium breakdown voltage transistor is specially formed, and particularly to avoid the thin portion 2a of the element isolation insulating layer 2 in the low voltage transistor forming portion as shown in FIG. 11B. .

In the above-mentioned example, the medium breakdown voltage transistor has an n-channel LOD type structure.
A channel structure can also be used. In this case, the conductivity type of each part of this transistor is selected to be the conductivity type opposite to the above-mentioned example, and in this case, the well region 3 of the well region 3 is selected.
0 is the well region 34 of the p-channel low voltage transistor
And the low concentration region 27a of the source region are formed at the same time as the source region of the p-channel low voltage transistor.

The medium breakdown voltage transistor has the above-mentioned L
The configuration is not limited to the OD type configuration, and as shown in FIG. 7, a configuration corresponding to FIG. 1 can be employed. Also in this case, the concentration adjustment region 33 of the drain region 24 may have a low concentration S /
After the D region 22 is formed, it can be formed by performing ion implantation. In this example, since this ion implantation is not performed through the element isolation insulating layer 26, the ion implantation may be performed by, for example, P ⁺ at 50 keV to 70 keV and 5 × 10 ¹² / cm ² to.
The dose is 8 × 10 ¹² / cm ² .

In FIG. 7, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and duplicate description will be omitted.

In the above-described embodiment, the ion implantation of the concentration adjusting region 33 is performed after the gate electrode is formed. This ion implantation is performed, for example, prior to the formation of the element isolation insulating layer 26. The present invention is not limited to the above-described example, and the drain region 24 and the concentration adjusting region 33 can be the same region as a result, without departing from the spirit of the present invention. , Various changes can be made.

[0046]

As described above, according to the present invention, in the semiconductor device in which the low voltage transistor and the open drain type medium withstand voltage transistor are formed on the semiconductor substrate,
Since the gate insulating films of the medium-voltage transistor and the low-voltage transistor have the same structure, the conventional case in which the gate insulating films of the low-voltage transistor and the medium-voltage transistor are individually formed as in the manufacturing method of the present invention In contrast to this, since the number of ion implantation steps for forming the concentration adjusting region 33 is increased by one step, the gate insulating films of the medium withstand voltage transistor and the low voltage transistor are formed to have different thicknesses as in the conventional case. In this case, since the complicated etching work and the oxidation process for forming the gate insulating film twice can be performed only once, the manufacturing process is simplified and the element isolation insulating layer shown in FIG. 11B is formed. The inconvenience of thinning can be avoided, and the low punch-through withstand voltage due to the parasitic transistor of the low-voltage transistor can be avoided. The can be avoided.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of an embodiment of a semiconductor device according to the present invention.

FIG. 2A is a process drawing of an example of a method for manufacturing a semiconductor device according to the present invention. FIG. 3B is a process drawing of an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 3A is a process drawing of an example of a method for manufacturing a semiconductor device according to the present invention. FIG. 3B is a process drawing of an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a process drawing of an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 5 is a process drawing of an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 6 is a process drawing of an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 7 is a cross-sectional view of another example of a semiconductor device according to the present invention.

FIG. 8 is a cross-sectional view of an example of a conventional open drain type medium withstand voltage transistor.

FIG. 9 is a cross-sectional view of another example of a conventional offset open drain type medium withstand voltage transistor.

FIG. 10A is a process diagram of a method for manufacturing a conventional open drain type medium withstand voltage transistor. 9B is a process diagram of a conventional method for manufacturing an open drain type medium withstand voltage transistor.

FIG. 11A is a process diagram of a manufacturing method of a conventional open-drain type medium withstand voltage transistor. 9B is a process diagram of a conventional method for manufacturing an open drain type medium withstand voltage transistor.

[Explanation of symbols]

 21 semiconductor substrate 22 medium voltage transistor 23 gate insulating film 24 drain region 24a region of drain region on channel formation region side 25 wiring contact part 26 element isolation insulating layer 27 source region 27a region of source formation channel formation region side

Claims (3)

[Claims] 1. A semiconductor device in which a low-voltage transistor and an open-drain medium-voltage transistor are formed on a semiconductor substrate, wherein the gate insulating films of the medium-voltage transistor and the low-voltage transistor have the same structure. Characteristic semiconductor device. 2. A method of manufacturing a semiconductor device in which a low-voltage transistor and an open-drain medium-voltage transistor are formed on a semiconductor substrate, wherein the medium-voltage transistor and each gate insulating film of the low-voltage transistor are simultaneously formed. A method of manufacturing a characteristic semiconductor device. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising an ion implantation step of setting an impurity concentration on a gate side of a drain region of the medium breakdown voltage transistor to a predetermined concentration.