JPH04366924A - Manufacture of active matrix substrate - Google Patents

Abstract

PURPOSE:To realize the high-definition active matrix display device which is improved in aperture rate and superior in picture quality as to the manufacture of the active matrix substrate which is equipped with a TFT as switching elements and also equipped with an additional capacitor for the improvement of display characteristics. CONSTITUTION:The TFT 21 is formed first on an insulating substrate 1 in the process of a channel area 2a, a source area 5a, a drain area 5b, and a gate electrode 6. Then the additional capacity 22 consisting of a 1st capacity electrode 10, an additional capacity insulating film 11, and a 2nd capacity electrode 12 is formed almost right above an area including the formation area of the TFT 21.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a method for manufacturing an active matrix substrate used in an active matrix display device such as a liquid crystal display, and more specifically, the present invention relates to a method for manufacturing an active matrix substrate used in an active matrix display device such as a liquid crystal display. The present invention relates to a method of manufacturing an active matrix substrate provided with additional capacitance in order to improve characteristics.

0002

2. Description of the Related Art FIG. 4 shows an equivalent circuit diagram of a general active matrix display device equipped with additional capacitance. This display device includes a plurality of horizontally parallel gate bus lines 24, 2.
A plurality of source bus wirings 25, 25... intersect with 4...
are arranged vertically. One rectangular picture element area surrounded by the gate bus wiring 24 and the source bus wiring 25 includes a picture element capacitor (CLC) 23 and a supplementary capacitor (CS) 2.
2 are provided in parallel. In addition, gate bus wiring 2
4 and the source bus wiring 25 are connected to the gate electrode and source electrode of the TFT 21, respectively. Also, T.F.
A pixel capacitor 23 and an additional capacitor 2 are connected to the drain electrode of T21.
2 are connected.

An active matrix substrate used in such a display device has conventionally been manufactured by a manufacturing process shown in FIG. As shown in FIG. 5A, first, a silicon layer that will later become the semiconductor layer 2 is deposited to a thickness of 100 nm on an insulating substrate 1 made of transparent glass or the like by low pressure CVD. Next, this silicon layer is patterned by photolithography and dry etching, thereby forming the semiconductor layer 2.

Next, as shown in FIG. 5(b), for example, C
A 100% insulating film 3 made of silicon oxide is deposited on the entire surface of the insulating substrate 1 by the VD method so as to cover the semiconductor layer 2.
Deposited to a thickness of nm. Thereafter, a resist film 4 is formed on the entire surface of the insulating film 3, and then a portion of the resist film 4 on the first capacitor electrode 2b, which is a part of the semiconductor layer 2, is removed. Then, using this resist film 4 as a mask, the portion that will become the first capacitor electrode 2b is doped with, for example, phosphorus P as an impurity by ion implantation at 100 KeV and 5×10 15 c.
Doping is carried out under conditions of m-2. Note that the phosphorus P doping step may be performed before forming the insulating film 3.

Next, as shown in FIG. 5C, the resist film 4 is removed, and a gate electrode 6 and a second capacitor electrode 6a are patterned on the semiconductor layer 2 with the insulating film 3 interposed therebetween. The gate electrode 6 is connected to the aforementioned gate bus wiring 24. Further, the above-mentioned additional capacitor 22 is formed by the first capacitor electrode 2b, the insulating film 3, and the second capacitor electrode 6b. Therefore, in this active matrix substrate, the insulating film 3 is used as an additional capacitance insulating film for additional capacitance.

Next, the gate electrode 6 and the second capacitor electrode 6a
was used as a mask, and by ion implantation method, for example, with phosphorus as an impurity, 100 KeV, 5 x 1015 cm-
Doping is carried out under the following conditions. By this ion implantation of impurities, the gate electrode 6 and the second capacitor electrode 6 of the semiconductor layer 2 are
A source region 5a and a drain region 5b are formed in a portion other than below a, and a channel region 2a is formed in a portion of the semiconductor layer 2 below the gate electrode 6. The insulating film 3 functions as a gate insulating film. The TFT 21 is manufactured through the above steps.

Next, as shown in FIG. 5(d), an interlayer insulating film 7 made of silicon oxide is formed on the entire surface of the insulating substrate 1 by CVD. Then, in order to activate the doped impurities, the insulating substrate 1 is heat-treated at 950° C. for 30 minutes in nitrogen, for example. Thereafter, contact holes 9a and 9b are formed in the portions of interlayer insulating film 7 above source region 5a and drain region 5b, and source bus wiring 25 is formed above contact hole 9a above source region 5a. On the other hand, a picture element electrode 8 is formed over the contact hole 9b above the drain region 5b and on the interlayer insulating film 7, thereby producing an active matrix substrate.

[0008] Thereafter, the active matrix substrate is bonded to a counter substrate on which a counter electrode is formed, and a display medium such as a liquid crystal is sealed between the two, thereby producing a liquid crystal display as an example of an active matrix display device. .

[0009]

[Problems to be Solved by the Invention] Incidentally, in order to improve the definition and image quality of a liquid crystal display, that is, to reduce the pixel size and improve the aperture ratio, it is necessary to improve the TFT and additional capacitance, which are the constituent elements of the liquid crystal display. It is necessary to reduce the area of

However, it is difficult to reduce the size of the TFT for the following reasons.

[0011] In other words, if the TFT is not made smaller by reducing the gate length, a short channel effect will occur with a decrease in the threshold voltage Vth and an increase in leakage current, and as a result, the TFT will become smaller. This is because there is a limit to how much it can be reduced.

Furthermore, it is difficult to reduce the additional capacitance for the following reasons.

That is, even if the picture element size is reduced, the charge to be stored in the additional capacitance cannot be reduced, so there is a limit to the reduction of the additional capacitance.

[0014] The present invention solves the problems of the prior art, and it is possible to increase the aperture ratio without reducing the area of the TFT and additional capacitance, and when it is incorporated into an active matrix substrate, it is possible to increase the aperture ratio. An object of the present invention is to provide a method for manufacturing an active matrix substrate that can improve image quality and high definition.

[0015]

[Means for Solving the Problems] The method for manufacturing an active matrix substrate of the present invention includes the steps of forming a thin film transistor on an insulating substrate, and adding an insulating film almost directly above a region including a region where the thin film transistor is formed. The method includes a step of forming a capacitor, thereby achieving the above object.

[0016]

[Function] When an additional capacitor is formed through an insulating film almost directly above the region including the thin film transistor formation region as described above, the aperture ratio, which is the ratio of the effective display area to the unit area of the picture element, is reduced. A predetermined additional capacity can be secured without having to do so. In other words, the aperture ratio can be increased without reducing the area of the TFT and additional capacitance.

[0017]

[Examples] Examples of the present invention will be described below.

FIG. 1 shows a cross-sectional structure of an active matrix substrate manufactured by the method of the present invention, and the active matrix substrate is manufactured by the steps shown in FIG. The details will be explained below.

As shown in FIG. 2A, first, a silicon layer that will later become the semiconductor layer 2 is deposited to a thickness of 100 nm on an insulating substrate 1 made of quartz, sapphire, or the like by low pressure CVD. Next, the silicon layer is patterned by photolithography and dry etching to form semiconductor layer 2. Next, using, for example, the CVD method, a gate insulating film 3 made of SiO2 is deposited to a thickness of 100 nm over the entire surface of the insulating substrate 1 so as to cover the semiconductor layer 2.

Thereafter, Si doped with phosphorus P is deposited to a thickness of 300 nm on the gate insulating film 3, and the Si
A gate electrode 6 is formed by patterning. Then,
Using the gate electrode as a mask, phosphorus was added as an impurity by ion implantation at 100 KeV, 5 x 1015 cm.
- Doping under the condition of 2. By this doping, a channel region 2a is formed in a portion of the semiconductor layer 2 corresponding to the lower part of the gate electrode 6, and a source region 5a and a drain region 5b are formed on the sides of the channel region 2a. The TFT 21 is manufactured as described above.

Next, as shown in FIG. 2(b), CVD
A SiO2 film having a thickness of 600 nm is deposited on the entire surface of the insulating substrate 1 by a method to cover the TFT 21 to form a first interlayer insulating film 7a. Thereafter, in order to activate the doped impurity P, the insulating substrate 1 is heat-treated at 950° C. for 30 minutes in nitrogen, for example. When the heat treatment is completed, a contact hole 9 is opened in a portion of the first interlayer insulating film 7a corresponding to the drain region 5b of the TFT 21.

Next, as shown in FIG. 2C, a first capacitor electrode 10 having a thickness of 150 nm is formed on the first interlayer insulating film 7a to serve as the lower electrode of the additional capacitor 22. The material of the first capacitor electrode 10 is made of polysilicon doped with phosphorus P. Specifically, the first capacitor electrode 10 is formed from the upper part of the gate electrode 6 to the opposite side of the contact hole 9, and a part of the first capacitor electrode 10 is formed through the contact hole 9 to extend from the upper part of the gate electrode 6 to the opposite side of the contact hole 9.
Connected to the drain region of FT21. Next, so as to cover the first capacitor electrode 10 formed in this way,
An additional capacitance insulating film 11 is deposited on the entire surface of the insulating substrate 1. Specifically, SiO with a thickness of 100 nm was formed using the CVD method.
It is formed by depositing two films.

Next, as shown in FIG. 2(d), a second capacitor electrode 12, which becomes the upper electrode of the additional capacitor 22, is formed on the additional capacitor insulating film 11. Specifically, it is formed by depositing a 150 nm thick polysilicon film doped with phosphorus P. As shown in the figure, the additional capacitance 22 formed as described above is formed almost directly above (directly above) the region on the insulating substrate 1 that includes the TFT 21 formation region. Therefore,
According to such a structure, the aperture ratio can be significantly improved compared to the active matrix substrate of the conventional structure shown in FIG. 5, in which the TFT 21 and the additional capacitor 22 are installed in a separated state. Therefore, when the active matrix substrate is incorporated into a display device, the image quality of the display device can be improved and high definition can be achieved.

As shown in FIG. 1, a second interlayer insulating film 7b is formed on the second capacitor electrode 12 formed as described above.
is formed. Specifically, the film thickness was 400 nm using the CVD method.
It is formed by depositing a SiO2 film of. Next, contact holes 13a and 13b are opened in a portion of the second interlayer insulating film 7b corresponding to above the source region 5a and a portion corresponding to above the gate electrode 6, respectively. after that,
A source bus line 25 is connected to the opening of the contact hole 13a.
Also, a picture element electrode 8 is formed at the opening of the contact hole 13b. A portion of source bus line 25 is connected to source region 5a through contact hole 13a. Further, a part of the picture element electrode 8 is connected to the second capacitor electrode 12 through the contact hole 13b. Through the above steps, an active matrix substrate is manufactured.

[0025] Thereafter, a counter substrate having a counter electrode formed on the opposite surface side is bonded to the active matrix substrate, and a liquid crystal serving as a display medium is sealed between both substrates, thereby producing an active matrix display device. Ru.

[0026] The active matrix substrate has TFT2
Although the active matrix substrate to which the present invention is directed is not limited to such a structure,
The present invention can be similarly applied to an active matrix substrate having a structure in which the gate electrode 6 of the TFT 21 is provided below the channel layer 2a as shown in FIG. The manufacturing of this active matrix substrate is the same as that of the above embodiment except that the manufacturing procedure of the portion including the gate electrode 6 and the channel region 2a is different. will be omitted.

[0027]

Effects of the Invention Since the method for manufacturing an active matrix substrate of the present invention described above takes the step of forming an additional capacitance almost directly above the region including the TFT formation region on the insulating substrate, the active matrix manufactured by this step According to the substrate, the aperture ratio can be significantly improved compared to the above-mentioned conventional active matrix substrate. Moreover, this can be realized without reducing the area of the TFT and additional capacitance. Therefore, by incorporating it into an active matrix display device such as a liquid crystal display, a high-definition active matrix display device with excellent image quality can be realized.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an active matrix substrate manufactured by the method of the present invention.

FIG. 2 is a cross-sectional view showing the manufacturing process of the method of the present invention.

FIG. 3 is a sectional view showing a modified example of an active matrix substrate manufactured by the method of the present invention.

FIG. 4 is a drawing showing an equivalent circuit of a conventional active matrix display device.

FIG. 5 is a cross-sectional view showing the manufacturing process of a conventional active matrix substrate.

[Explanation of symbols]

1 Insulating substrate 2 Semiconductor layer 2a Channel layer 3 Gate insulating film 5a Source region 5b Drain region 6 Gate electrode 7a First interlayer insulating film 7b Second interlayer insulating film 8 Pixel electrodes 9, 13a, 13b Contact hole 10 First
Capacitor electrode 11 Additional capacitor insulating film 12 Second capacitor electrode 21 TFT 22 Additional capacitor 25 Source bus line

Claims (1)

[Claims] 1. A method for manufacturing an active matrix substrate, comprising the steps of forming a thin film transistor on an insulating substrate, and forming an additional capacitor via an insulating film almost directly above a region including the region where the thin film transistor is formed. .