JPS5821868A - Manufacture of thin polycrystalline silicon film transistor - Google Patents
Manufacture of thin polycrystalline silicon film transistorInfo
- Publication number
- JPS5821868A JPS5821868A JP12076381A JP12076381A JPS5821868A JP S5821868 A JPS5821868 A JP S5821868A JP 12076381 A JP12076381 A JP 12076381A JP 12076381 A JP12076381 A JP 12076381A JP S5821868 A JPS5821868 A JP S5821868A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- source
- hydrofluoric acid
- film transistor
- solution containing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 4
- 230000003647 oxidation Effects 0.000 claims abstract 2
- 238000007254 oxidation reaction Methods 0.000 claims abstract 2
- 230000001590 oxidative effect Effects 0.000 claims abstract 2
- 239000010409 thin film Substances 0.000 claims description 16
- 239000010408 film Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 10
- 238000001259 photo etching Methods 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 13
- 239000000243 solution Substances 0.000 abstract description 6
- 239000002344 surface layer Substances 0.000 abstract description 3
- 230000002411 adverse Effects 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 abstract description 2
- 239000006104 solid solution Substances 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 abstract 1
- 230000009545 invasion Effects 0.000 abstract 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- -1 CdS and CdSe Chemical class 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
Abstract
Description
【発明の詳細な説明】
本発明は多結晶シリコンを用いた薄膜トランジスタの製
造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a thin film transistor using polycrystalline silicon.
薄膜トランジスタは、絶縁体基板上に蒸着等によシ半導
体薄膜を被着形成して能動素子を作ったもので、通常は
電界効果形であり構造及び動作ともにMOS−FETに
類似している。しかし、MOS−FETが通常単結晶基
板を用いて形成されるのに対し、この薄膜トランジスタ
は絶縁体基板上に形成した半導体薄膜によって構成され
るために、大面積トランジスタアレイを製作できるとい
う利点を有している。このため、例えば液晶マトリクス
ディスプレイのクロストーク防止用のスイッチング素子
として極めて好適である。即ち、液晶マトリクスディス
プレイは近年ポケットテレビやコンピュータ一端末用機
器として開発が進められ、画像の一層の精細化が求めら
れているが、画素子数の増加に伴なうクロストークを防
止するためには各画素にスイッチング素子を付設する手
段が有効である。この場合、薄膜トランジスタを用いれ
ばディスプレイパネルの一方の基板に作り付けることが
できるから有利である。薄膜を構成する半導体としては
、CdS、CdSe等の化合物やアモルファスシリコン
等も用いられるが、特性の安定性や無公害の観点から多
結晶シリコンが最もすぐれている。A thin film transistor is an active element formed by depositing a semiconductor thin film on an insulating substrate by vapor deposition or the like, and is usually a field effect type, and is similar in structure and operation to a MOS-FET. However, while MOS-FETs are usually formed using a single crystal substrate, thin film transistors are constructed from a semiconductor thin film formed on an insulating substrate, and therefore have the advantage of being able to fabricate large-area transistor arrays. are doing. Therefore, it is extremely suitable as a switching element for preventing crosstalk in, for example, a liquid crystal matrix display. In other words, in recent years, liquid crystal matrix displays have been developed as devices for pocket TVs and computer terminals, and there is a demand for even higher definition images, but in order to prevent crosstalk due to the increase in the number of pixels. An effective method is to attach a switching element to each pixel. In this case, it is advantageous to use thin film transistors because they can be fabricated on one substrate of the display panel. Compounds such as CdS and CdSe, amorphous silicon, and the like are also used as semiconductors constituting the thin film, but polycrystalline silicon is the best in terms of stability of properties and non-polluting properties.
第1図および第2図は、通常用いられているこの種の薄
膜トランジスタの一例を示す断面図である。同図におい
て、1はガラス等の絶縁体基板、2は半導体膜、3は絶
縁膜、4,5はソースおよびドレイン電極、6はゲート
電極である。FIGS. 1 and 2 are cross-sectional views showing an example of this type of thin film transistor commonly used. In the figure, 1 is an insulating substrate such as glass, 2 is a semiconductor film, 3 is an insulating film, 4 and 5 are source and drain electrodes, and 6 is a gate electrode.
しかしながら、上記構成を有する薄膜トランジスタにお
いて、半導体が多結晶シリコンの場合、膜厚が薄いと結
晶性が不十分で良好な動作特性が得られず、良好な動作
特性を得るためには膜厚は2000X以上、望ましくは
5000AJJ上必要である。ところが半導体膜の膜厚
をこのように厚くすると、第1,2図の構造の場合、ゲ
ートに電圧を印加してもソースおよびドレイン電極近傍
の半導体にキャリアが十分励起されず、動作しにくくな
るという欠点がある。そξで半導体膜として多結晶シリ
コンを用いる場合には、キャリア励起上有利な第3,4
図の構造が望ましいと考えられる。However, in a thin film transistor having the above structure, when the semiconductor is polycrystalline silicon, if the film thickness is too small, the crystallinity is insufficient and good operating characteristics cannot be obtained. The above is preferably 5000 AJJ or more. However, if the thickness of the semiconductor film is increased in this way, in the case of the structure shown in Figures 1 and 2, even if voltage is applied to the gate, carriers will not be sufficiently excited in the semiconductor near the source and drain electrodes, making it difficult to operate. There is a drawback. Therefore, when polycrystalline silicon is used as the semiconductor film, the third and fourth layers are advantageous for carrier excitation.
The structure shown in the figure is considered desirable.
なお、第3,4図において第1,2図と同一部分には同
一符号を付しである。しかしながら、第3図の構造では
ソースおよびドレイン電極4,5を形成後、多結晶シリ
コンの半導体膜2を形成することになるが、多結晶シリ
コン膜を形成するためには基板温度を500℃、あるい
はそれ以上に上げる必要があり、シリコン膜を形成する
時点で電極材料がシリコン中に拡散、あるいはシリコン
と反応してし1い実際上採用できないという欠点がある
。結局半導体膜として多結晶シリコンを用いる場合には
第4図の構造をとらざるを得なくなる。In addition, in FIGS. 3 and 4, the same parts as in FIGS. 1 and 2 are given the same reference numerals. However, in the structure shown in FIG. 3, the polycrystalline silicon semiconductor film 2 is formed after forming the source and drain electrodes 4 and 5, but in order to form the polycrystalline silicon film, the substrate temperature must be set at 500°C. However, there is a drawback that the electrode material may diffuse into the silicon or react with the silicon at the time of forming the silicon film, so that it cannot be used in practice. In the end, if polycrystalline silicon is used as the semiconductor film, the structure shown in FIG. 4 has to be adopted.
第4図の構造の場合、ソース、ドレイン電梧4゜5の形
成はマスク蒸着でも可能であるが、電極パターンの精度
が不十分でありソース・ドレイン間のリークが起9やす
いなどの欠点がある。これに対してフォトエツチングで
は容易に所定の電極パターンを形成することができて望
ましい結果を得ることができる。1だ、電極材料として
は多結晶シリコンと反応しにぐいこと、良好な’tri
、気的コンタクトがとれることなどの条件を考慮すると
ほぼAd に限定きれる。結局、多結晶シリコン薄膜ト
ランジスタのソース、ドレイン’th<としては、フォ
トエツチングでAl のパターンを形成したものが望
ましいことになる。In the case of the structure shown in Figure 4, it is possible to form the source and drain electrodes by mask evaporation, but there are drawbacks such as insufficient precision of the electrode pattern and leakage between the source and drain. be. On the other hand, photoetching can easily form a predetermined electrode pattern and produce desirable results. 1. As an electrode material, it does not easily react with polycrystalline silicon, and has good 'tri' properties.
Considering conditions such as the ability to make physical contact, it can be almost limited to Ad. In the end, it is desirable that the source and drain 'th< of the polycrystalline silicon thin film transistor be formed with an Al pattern formed by photo-etching.
しかしながら、このような多結晶シリコン薄膜トランジ
スタを製作したところ、以下の問題があることか分った
。すなわち多結晶シリコン膜上にAlを蒸着する場合、
密着性をよくするために基板温度を上げると、A/が多
結晶シリコン中に拡散して表面層がP型になる傾向があ
シ、これが基板温度にきわめて敏感であるために動作特
性が一定のものが得に<<、またA1層をフォトエツチ
ングすることによってソース・ドレイン電極を形成した
あとの多結晶シリコン表面が清浄でないために良好な動
作特性を得にくい。However, when such a polycrystalline silicon thin film transistor was manufactured, it was found that the following problems occurred. That is, when depositing Al on a polycrystalline silicon film,
When the substrate temperature is raised to improve adhesion, A/ tends to diffuse into the polycrystalline silicon and the surface layer becomes P-type. This is extremely sensitive to the substrate temperature, so the operating characteristics remain constant. Moreover, it is difficult to obtain good operating characteristics because the polycrystalline silicon surface is not clean after the source/drain electrodes are formed by photoetching the A1 layer.
これらは、表面を適当な液でエツチングすることによっ
て清浄化できるが、シリコン表面を清浄化しようとする
とAl も溶解してしまうという問題が生じる。These can be cleaned by etching the surface with a suitable solution, but when attempting to clean the silicon surface, the problem arises that Al also dissolves.
本発明けこのような点に鑑みて考えられたもので、その
目的とするところは、特性の良好な多結晶シリコン薄膜
トランジスタを得るだめの製造方法を提供することにあ
る。以下、本発明の詳細な説明する。The present invention has been conceived in view of these points, and its purpose is to provide a manufacturing method for obtaining polycrystalline silicon thin film transistors with good characteristics. The present invention will be explained in detail below.
まず、第4図において、ソース、ドレイン電極4.5を
形成後、その表面をプラズマ酸化する。First, in FIG. 4, after forming source and drain electrodes 4.5, their surfaces are plasma oxidized.
次に、表面を7ツ酸を含んだ液でエツチングする。Next, the surface is etched with a solution containing 7-acid.
この方法によれば、多結晶シリコンの半導体膜2の表面
を低温で酸化できるために望ましくない不純物の侵入を
防止でき、しかもそのとき生成されたシリコンの酸化物
はフッ酸を含んだ液で容易に除去されるため、多結晶シ
リコン表面層に固溶したAlを含めて表面が清浄化され
る。また、ソース、ドレイン電極パターンも同時に酸化
されるが、生成されたAl酸化物はフッ酸にきわめて溶
解しにくいために、多結晶シリコン膜の表面のみを選択
的にエツチングできることになる。According to this method, since the surface of the polycrystalline silicon semiconductor film 2 can be oxidized at low temperature, it is possible to prevent the intrusion of undesirable impurities, and furthermore, the silicon oxide produced at that time can be easily removed with a solution containing hydrofluoric acid. Since Al is removed as a solid solution in the polycrystalline silicon surface layer, the surface is cleaned. Further, the source and drain electrode patterns are also oxidized at the same time, but since the generated Al oxide is extremely difficult to dissolve in hydrofluoric acid, only the surface of the polycrystalline silicon film can be selectively etched.
以上のべたように、本発明の製造方法によれば、多結晶
シリコン表面を他に悲影響を及ばずことなく清浄化でき
るために、再現性よく、シかも良好な特性のトランジス
タを製作することができるという優れた効果がある。As described above, according to the manufacturing method of the present invention, it is possible to clean the polycrystalline silicon surface without adversely affecting others, so that it is possible to manufacture transistors with good reproducibility and good characteristics. It has the excellent effect of being able to
第1図ないし第3図は従来の多結晶シリコン薄膜トラン
ジスタの断面図、第4図は本発明の製造方法を実施する
多結晶シリコン薄膜トランジスタの断面図である。
1・・・・絶縁体基板、2・・・・半導体膜、3・・・
・絶縁膜、4・・・拳ソース電極、5・・・・ドレイン
電極、6・・拳・ゲート電極。
7−1 to 3 are cross-sectional views of conventional polycrystalline silicon thin film transistors, and FIG. 4 is a cross-sectional view of a polycrystalline silicon thin film transistor in which the manufacturing method of the present invention is implemented. 1... Insulator substrate, 2... Semiconductor film, 3...
- Insulating film, 4... fist source electrode, 5... drain electrode, 6... fist/gate electrode. 7-
Claims (1)
成し、フォトエツチングによってソース。 ドレイン電極を形成した多結晶シリコン薄膜トランジス
タの製造方法において、前記ソース、ドレイン電極を形
成した後表面をプラズマ酸化し、プラズマ酸化によって
形成されたシリコン酸化物をフッ酸を含んだ液で除去す
ることを特徴とする多結晶シリコン薄膜トランジスタの
製造方法。[Claims] A source is formed by forming an Ag layer on a polycrystalline silicon film formed on an insulating substrate and photoetching it. A method of manufacturing a polycrystalline silicon thin film transistor with a drain electrode formed therein includes plasma oxidizing the surface after forming the source and drain electrodes, and removing silicon oxide formed by the plasma oxidation with a solution containing hydrofluoric acid. A method for manufacturing a characteristic polycrystalline silicon thin film transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12076381A JPS5821868A (en) | 1981-08-03 | 1981-08-03 | Manufacture of thin polycrystalline silicon film transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12076381A JPS5821868A (en) | 1981-08-03 | 1981-08-03 | Manufacture of thin polycrystalline silicon film transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5821868A true JPS5821868A (en) | 1983-02-08 |
Family
ID=14794385
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12076381A Pending JPS5821868A (en) | 1981-08-03 | 1981-08-03 | Manufacture of thin polycrystalline silicon film transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5821868A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59193062A (en) * | 1983-04-15 | 1984-11-01 | Hitachi Ltd | Polycrystalline silicon thin film transistor |
JPH01128572A (en) * | 1987-11-13 | 1989-05-22 | Nippon Telegr & Teleph Corp <Ntt> | Thin film transistor and manufacture thereof |
US6566174B1 (en) * | 1997-04-23 | 2003-05-20 | Nec Corporation | Thin-film transistor elements and methods of making same |
-
1981
- 1981-08-03 JP JP12076381A patent/JPS5821868A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59193062A (en) * | 1983-04-15 | 1984-11-01 | Hitachi Ltd | Polycrystalline silicon thin film transistor |
JPH0554271B2 (en) * | 1983-04-15 | 1993-08-12 | Hitachi Ltd | |
JPH01128572A (en) * | 1987-11-13 | 1989-05-22 | Nippon Telegr & Teleph Corp <Ntt> | Thin film transistor and manufacture thereof |
US6566174B1 (en) * | 1997-04-23 | 2003-05-20 | Nec Corporation | Thin-film transistor elements and methods of making same |
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