JPH0284775A - Manufacture of vertical thin film transistor - Google Patents

Abstract

PURPOSE:To have only to use a high-cost plasma CVD only one time for the formation of an insulating film for gate electrode parts and to make it possible to obtain a TFT, which is improved in both the film thickness and the film quality of its gate insulating film and has a superior efficiency, by a method wherein the surfaces of the gate electrodes are oxidized by an anodization method to form the insulating film and the like. CONSTITUTION:A first main electrode 12 is formed on an insulative substrate 11, a first insulating film 14 is formed on the main electrode 12 and gate electrodes 15 of a prescribed pattern are formed on the film 14. Then, the surfaces of the electrodes 15 are anodized to cover with a second insulating film 16 and the film 14 is etched away using the above electrodes 15 as masks after or before that process. After that, a semiconductor film 17 which is used as an operating layer is deposited on the whole surface and second main electrodes 19 are formed on the film 17. For example, the above film 17 is formed as an amorphous semiconductor film or a poly semiconductor film containing silicon, carbon and germanium or their mixtures as its main component. Moreover, second main electrodes 19 are formed on the semiconductor layer 17 through a high-impurity concentration a Si film 18.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to a method for manufacturing a vertical thin film transistor that is useful when applied to a drive circuit section of a two-dimensional image sensor, a liquid crystal display, and the like.

(Prior Art) In recent years, applications of thin film transistors (TPT) using amorphous silicon (a-8t) have become active. Currently, a-
The mainstream type of 8i TPT is the planar type, which achieves an on/off ratio in the range of 4 to 6 digits. However, amorphous semiconductors have low mobility, and in the case of silicon, u-0, icM
It is about 2/v*sec. For this reason, the current a-S
The response speed of the t-planar TPT is as slow as about 10 .mu.sec at most, making it difficult to use in high-speed drive applications.

Therefore, vertical thin film transistors have recently been viewed as promising as thin film transistors capable of high-speed operation. A conventional example thereof will be explained next.

Figure 4 shows the MS type vertical TPT (Japanesc
Journal of Applied Phys.
slcs Vol, 24 (1985) pp4
87-471). A drain electrode 22 is formed on an insulating substrate 21 such as glass. A high resistance a-3i film 24 is deposited via the n-type a-8i film 23, and this a-Si film 24
A gate electrode 25 having a predetermined pattern is embedded therein. A source electrode 27 is formed on the a-8i film 24 via an n◆ type layer 26 having a predetermined pattern.

In this vertical TPT structure, the electrode metal (M) and semiconductor (S) are in direct contact with each other in the gate part to form a Schottky junction, so the gate leakage current is large and a sufficient 0N1
The problem is that the 0FF ratio cannot be obtained.

Figure 5 shows a vertical TPT whose gate part has an MIS structure.
This is a conventional example. The difference from FIG. 4 is that the gate electrode 25 is covered with insulating films 28 and 29. With such a gate structure, leakage current becomes small and it becomes possible to obtain a large 0N10FF ratio.

To obtain the structure shown in FIG. 5, first the electrode film 2 is placed on the substrate 21.
2. After depositing the n+ type A-8T film 23, a first insulating film 28 and a metal film of the gate electrode 25 are laminated, and the laminated film of these metal films and the first insulating film 28 is etched into a predetermined pattern. Next, a second insulating film 29 is deposited over the entire surface and patterned, leaving it around the gate electrode 25. After this, a high-resistance a-8i film 24 is deposited, and a source electrode 27 is formed thereon via an n+ type layer 26. In this conventional example, there is a big problem in the process of forming the gate part of the MIS structure. was there. First, two insulating film formation steps are required, and an expensive process such as plasma CVD is used, resulting in high costs. Second, vertical TP
At T, the gate electrode spacing determines the channel width, so the high 0
In order to obtain the N10FF ratio, a high-definition gate electrode is required, and specifically microfabrication with a gate spacing of 2 μm or less is required. It is technically difficult to form a pattern with high precision, and even if it were possible, it would be expensive. Thirdly, the side wall portion of the gate electrode 25 in the insulating film 29 becomes the main gate insulating film that directly affects the TPT operation, but it is difficult to form this side wall insulating film with a similar thickness and densely. , which is difficult with the CVD method.

(Problems to be solved by the invention) As mentioned above, the vertical TPT with the conventional MIS structure has
Problems include the high cost of forming the insulating film by plasma CVD twice when forming the gate part, and the technical difficulty of microfabrication of the insulating film of the gate part and the technical difficulty of forming a uniform and high-quality film. was there.

The present invention solves these problems by providing a TPT with an MIS structure.
The purpose is to provide a manufacturing method for.

[Structure of the Invention] (Means for Solving the Problems) In the present invention, after forming a first main electrode on an insulating substrate, a gate electrode is formed on the first main electrode in a predetermined manner via a first insulating film. Using this gate electrode as a mask, the first insulating film is removed by etching, and the surface of the gate electrode is subjected to anodic oxidation (
(including plasma anodic oxidation) to form a second insulating film. A high-resistance semiconductor film serving as an active layer is then deposited, and a second main electrode is formed thereon.

(Function) According to such a method, expensive plasma CVD only needs to be used once to form the insulating film of the gate electrode portion. In addition, since the second insulating film is formed by modifying the surface after patterning the gate electrode, the process of forming a highly accurate insulating film pattern using PEP in accordance with the gate electrode pattern as in the conventional method is no longer required. do not have. Furthermore, in the anodic oxidation method, oxidation grows isotropically from the metal surface, so that the insulating film formed on the side walls of the gate electrode also has excellent composition, film thickness, and tightness.

(Example) FIG. 1 shows the structure of a vertical TPT according to an example of the present invention, and FIGS. 2(a) to (j) show its manufacturing process. The manufacturing process will be specifically explained below.

After cleaning the surface of an insulating substrate 11 such as glass, a metal film is deposited and turned into a predetermined shape to form a drain electrode (first main electrode) 12 ((a)
). On top of this, by plasma CVD method, n medium size a-8i
Deposit film 13 ((b)). Next, this n÷ type a-
For example, a −
A first insulating film 14 made of 3iNx or the like is formed (
C)) Then, a gate electrode metal film is deposited on this insulating film 14 (d)) This is patterned into a predetermined shape to form a gate electrode 15 ((e)). Then, using this gate electrode 15 as a mask, the first insulating film 14 is
is removed by machining and soching to expose the n÷ type layer 13 (
(f)). Next, the surface (upper surface and side surfaces) of this gate electrode 15 is oxidized by an anodic oxidation method to form a second insulating film 16 ((g)). Next, an undoped high-resistance a-St film 17 and then an n-medium type a-9L film 18 are sequentially deposited over the entire surface by plasma CVD ((h)).

Then, a metal film is deposited, and this metal film and the n medium a
The -9i film 18 is patterned into a predetermined shape to form a source electrode (second main electrode) 19 ((j)).

Thus, according to this embodiment, compared to conventional processes, a MIS type vertical TPT can be manufactured by reducing the high cost process such as plasma CVD for depositing an insulating film. Moreover, there is no need for a PEP process for forming an insulating film in accordance with a fine gate electrode pattern. As a result of the above, M
IS type vertical TPT can be manufactured. In addition, since an anodic oxide film is used for the gate insulating film, plasma C
When compared with the case using VD, a homogeneous oxide film with a similar thickness can be obtained particularly on the side wall of the gate electrode in contact with the channel region, and excellent TPT characteristics can be obtained.

In the above embodiment, as shown in FIGS. 2(f) and 2(g), first the first insulating film 14 is etched using the patterned gate electrode 15 as a mask, and then the gate electrode 15 is etched.
The surface of the substrate was covered with a second insulating film 16 formed by anodic oxidation.

This part of the process can be reversed as shown in FIGS. 3(a) and 3(b). That is, as shown in FIG. 3(a),
After the surface of the patterned gate electrode 15 is covered with the second insulating film 16 by anodic oxidation, the first insulating film 14 is etched using the gate electrode 15 as a mask, as shown in FIG. 3(b). A vertical TPT with excellent characteristics can be obtained by performing the other steps in the same manner as in the previous embodiment.

The present invention is not limited to the above embodiments.

For example, in the examples, an a-3T film was used, but other materials may also be used, such as amorphous semiconductors (a-S i C, a-S i G e, etc.) whose main components are carbon, germanium, or a mixture thereof.
Furthermore, a polycrystalline semiconductor film can be used.

The pond water invention can be implemented with various modifications without departing from the spirit thereof.

[Effects of the Invention] As described above, according to the present invention, the vertical T
By introducing the anodic oxidation method to the manufacturing of PT, it is possible to reduce the high-cost process that requires high precision, and also improve the thickness and quality of the gate insulating film, resulting in a T with excellent performance.
PT can be obtained.

[Brief explanation of the drawing]

FIG. 1 shows a vertical TP with an MIS structure according to an embodiment of the present invention.
Figures 2 (a) to (j) are diagrams showing the manufacturing process thereof, Figures 3 (a) and (b) are diagrams for explaining the manufacturing process of other examples, and Figure 4 The figure shows a vertical TP with a conventional MS structure.
FIG. 5 is a diagram showing a vertical TPT with a conventional MIS structure. 11... Insulating substrate, 12... Drain electrode (first
main electrode), 13...n medium-sized a-Si film, 14...
first insulating film, 15... gate electrode, 16... first
Insulating film (anodized film), 17...and-pro-3
t film, 18...n medium-sized a-3i film, 19... source electrode (second main electrode). Applicant's agent Patent attorney Takehiko Suzue Figure (2) Figure (3) Figure (4) Figure 3

Claims (2)

[Claims] (1) forming a first main electrode on an insulating substrate;
forming a first insulating film on the first main electrode;
A step of forming a gate electrode in a predetermined pattern on the first insulating film, a step of anodizing the surface of the gate electrode and covering it with a second insulating film, and masking the gate electrode after or before this step. The method is characterized by comprising the steps of etching away the first insulating film, depositing a semiconductor film to serve as an active layer over the entire surface, and forming a second main electrode on the semiconductor film. A method for manufacturing vertical thin film transistors. (2) The method for manufacturing a vertical thin film transistor according to claim 1, wherein the semiconductor film is an amorphous semiconductor or a polycrystalline semiconductor whose main component is silicon, carbon, germanium, or a mixture thereof.