JP3411408B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an insulating substrate such as glass,
Alternatively, a semiconductor device having a non-single-crystal silicon film provided on an insulating film formed on various substrates, such as a thin film transistor (TFT) or a thin film diode (TFD),
Further, the present invention relates to a method for manufacturing a thin film integrated circuit to which they are applied, particularly a thin film integrated circuit for an active liquid crystal display device (liquid crystal display).

[0002]

2. Description of the Related Art In recent years, semiconductor devices having TFTs on an insulating substrate such as glass, for example, active type liquid crystal display devices using TFTs for driving pixels, image sensors, three-dimensional integrated circuits, etc. have been developed.

A thin film non-single crystal silicon semiconductor is generally used for a TFT used in these devices.
The thin-film non-single-crystal silicon semiconductor is roughly classified into two types, that is, an amorphous silicon semiconductor (a-Si) and a crystalline silicon semiconductor. Amorphous silicon semiconductors are the most commonly used because they have a low manufacturing temperature, can be relatively easily manufactured by the vapor phase method, and have high mass productivity. Since it is inferior to the silicon semiconductor that it has, in order to obtain higher speed characteristics in the future, there has been a strong demand for establishment of a method for manufacturing a TFT made of a crystalline silicon semiconductor. As a silicon semiconductor having crystallinity suitable for such a purpose, polycrystalline silicon, microcrystalline silicon,
Amorphous silicon containing a crystalline component, semi-amorphous silicon having an intermediate state between crystalline and amorphous are known.

As a method for obtaining a thin film silicon semiconductor having these crystallinity, an amorphous semiconductor film is subjected to plasma CV.
A method is known in which a film is formed by a method such as the D method or a low pressure CVD method, and thermal energy is applied to this for a long time (thermal annealing) to crystallize. However, it is usually necessary to set the heating temperature to 600 ° C. or higher, and to raise the crystal growth to a high temperature of 640 ° C. or higher, which is a problem that the substrate is thermally affected.
Moreover, since the heating time required for crystallization reaches several tens of hours or more, mass productivity is low. Therefore, it has been required to lower the heating temperature and shorten the heating time.

[0005]

On the other hand, by irradiating strong light of infrared rays or visible light for about 10 to 1000 seconds, the temperature of the film surface is raised to a high temperature of substantially 800 ° C. or higher to crystallize. The method of letting was developed. This method is called a lamp anneal or a rapid thermal anneal (RTA) method and is expected as a process that can reduce the influence on the substrate because the heating time is short.

However, the plasma CVD method and the reduced pressure C
A large amount of hydrogen is contained in the film formed by the VD method in combination with silicon, and in a short time actually used in the RTA method, crystallization does not proceed sufficiently at the center of hydrogen decomposition reaction. I understood it. Further, hydrogen contained in the film is decomposed and released to the outside, which causes another problem that the morphology of the film surface is significantly deteriorated. The present invention is
The present invention has been made in view of such circumstances, and an object thereof is to obtain a silicon film having sufficient crystallinity and suitable for forming a semiconductor device while using the RTA method.

[0007]

According to the present invention, an amorphous silicon film is formed on a glass substrate, and the amorphous silicon film is crystallized by means such as thermal annealing. It has a first step of desorbing hydrogen and a second step (RTA step) of heating the silicon film by intense light. An insulating film that does not absorb 10% or more of the light used in the third step may be formed on the silicon film between the second step and the third step.

In the present invention, the silicon film obtained in the first step preferably has a low degree of crystallinity, and the crystallinity thereof is 1 to 50%, preferably 1 to 10%. In the first step, thermal anneal or other crystallization method can be used. In addition, before the second step, the silicon film is patterned and etched to be separated into islands.
A step of dividing may be provided.

In the present invention, the substrate has a strain point of 55.
A glass substrate of 0 to 680 ° C. is preferable. Specifically, Corning No. 7059 (strain point 593 ° C), 1733
No. (strain point 640 ° C.), HOYA LE30 (strain point 62
5 ° C), NA35 from NH Techno Glass (strain point 650
℃), NA45 (strain point 610 ℃), OHARA E-
8 (strain point 643 ° C.), Nippon Electric Glass Co., Ltd.'s OA-2 (strain point 625 ° C.), Asahi Glass's AN 1 (strain point 625 ° C.), AN
2 (strain point 625 ° C.) and the like. It goes without saying that glass substrates other than the above may be used.

An insulating film of silicon oxide, silicon nitride, aluminum nitride or the like may be formed on the surface of the glass substrate, and an amorphous silicon film may be formed thereon. The second step may be omitted when a coating of a material having high thermal conductivity such as aluminum nitride is formed on the glass substrate. In the first step, when crystallization is performed by thermal annealing, the temperature and time thereof vary depending on the film thickness, composition, etc. of the semiconductor thin film, but in the case of a substantially intrinsic silicon semiconductor, 520 to 620 ° C. , For example, 55
0 to 600 ° C. and 1 to 4 hours are suitable. Further, the thermal annealing temperature is preferably lower than the strain point of the glass substrate.

Before the thermal annealing step, the silicon film is ion-implanted to 1 × 10 ¹⁴ to 1 × 10 ¹⁶ cm.
^Implanting silicon ions at a dose of ^-2 is particularly preferable because crystal growth due to thermal annealing is suppressed. The silicon film obtained in the first step of the present invention may contain a metal element such as nickel that promotes crystallization. Other metal elements that promote such crystallization include Fe, Co, Ni, Ru, Rh, Pd, and O.
s, Ir, Pt, Sc, Ti, V, Cr, Mn, Cu,
Zn, Au, and Ag are known, but an amorphous silicon film to which these elements are added can be sufficiently crystallized even by thermal annealing at a low temperature of 520 to 620 ° C. for 1 to 4 hours and a short time. proceed.

However, if the crystallization progresses excessively, the effect of the subsequent crystal growth by RTA is lost. Therefore, when these metal elements are added, it is desired that the thermal annealing time be shorter or the thermal annealing temperature be lower than in the case of a substantially intrinsic silicon film. By including these metal elements, it is possible to crystallize at a lower temperature even in the subsequent RTA step. In addition, these metal elements also have the effect of promoting hydrogen desorption from the amorphous silicon film during thermal annealing. When such a metal element is added, it is preferable to implant silicon ions as described above before the thermal annealing step because crystal growth in the thermal annealing step can be suppressed.

It should be noted that these metal elements have a great influence on semiconductor characteristics and reliability, and a silicon film containing a large amount of these metal elements and crystallized has a particularly long-term reliability and durability. Lack. In order to solve such a problem, the concentration of the metal element present in these silicon films is effective in performing crystallization at a required temperature, and
It is preferable that the semiconductor characteristics are not adversely affected. Specifically, when the concentration of these metal elements contained in the silicon film is analyzed in the depth direction by secondary ion mass spectrometry (SIMS), the minimum detected concentration is 1 × 10 ¹⁵ to
It is preferably 1 × 10 ¹⁹ cm ⁻³ .

As the light used for the RTA in the above-mentioned second step, the wavelength of the light used is preferably absorbed by the silicon film and not substantially absorbed by the glass substrate, and the central wavelength is near infrared or visible. It is suitable to use light rays. For example, light having a wavelength of 4 μm to 0.6 μm (for example, infrared light having a peak at a wavelength of 1.3 μm) is preferable, and by irradiating such intense light for a relatively short time of about 10 to 1000 seconds, silicon can be obtained. The film can be heated to improve its crystallinity. At this time, the silicon film is 8
It is desirable to heat to 00 to 1300 ° C.

Further, if the material is rapidly heated from room temperature to such a high temperature or, conversely, is rapidly cooled from such a high temperature to room temperature, the influence of stress or the like on the silicon film is great. Therefore, before reaching such a high temperature, a preheating step of heating at a temperature lower than that for a while,
In the process of lowering the temperature from the high temperature state, a post-heating step of heating for a while at an intermediate temperature between the high temperature and room temperature may be provided. In order to prevent thermal damage to the substrate, the temperature of the preheating process and the postheating process is preferably 50 to 200 ° C. lower than the strain point of the glass substrate.

[0016]

The thermal annealing of the first step causes at least nucleation of crystal growth. Even when the crystallization was suppressed, the crystallization was low (the crystallization area was 1 to 50).
%, Preferably 1 to 10% of the crystallized state (the rest is in the amorphous state) of the silicon film can be obtained. However, it is not preferable to form a semiconductor device as it is from the crystalline silicon film obtained in the first step. This is because a large amount of amorphous components and the like remain mainly at grain boundaries and the like, and the bulk and surface characteristics of the silicon film are unfavorable.

Therefore, in the present invention, this silicon film is converted into a silicon film having good crystallinity by RTA in the second step. By RTA, the silicon film can be heated to further improve the crystallinity of the crystallized silicon film, and at the same time, the film quality can be densified. At this time, in the case of a silicon film having a low degree of crystallinity, it is possible to spread the crystal from the crystal nucleus generated in the first step to the surrounding amorphous region. In such a case, crystallization proceeds over a relatively long distance, which is effective in reducing grain boundaries and the like. By increasing the crystallinity in this way, it is possible to obtain a high-quality silicon film having a crystallized area of 90% or more as used in a thin film transistor (TFT).

However, in such RTA, since a rapid temperature change is locally caused, a difference in the coefficient of thermal expansion between the silicon film and the substrate and a difference in the temperature between the surface of the silicon film and the interface between the substrate and the silicon film. Therefore, the silicon film is often peeled off. In particular, this is remarkable when the area of the film is large so as to cover the entire surface of the substrate. Therefore, as described above, in the second step, the film is divided into small enough areas, and the distance between the films is wide enough so as not to absorb the excessive heat, so that the films are peeled off. Can be prevented.
Further, in this case, since the entire surface of the substrate is not heated through the silicon film, thermal contraction of the substrate can be suppressed to the minimum.

In the present invention, it is preferable to irradiate a silicon film formed on a glass substrate with light having a wavelength of 0.6 to 4 μm in the second step (RTA step). Light of this wavelength is effectively absorbed by the low-crystallized intrinsic or substantially intrinsic (phosphorus or boron is 10 ¹⁷ cm ⁻³ or less) silicon film and is converted into heat. Also,
Far infrared light having a wavelength of 10 μm or more is absorbed by the glass substrate and heats the glass substrate. However, when the wavelength of 4 μm or less is most, the absorption by the glass is 0.01 to 10%, so heating is extremely difficult. Few. That is, in order to crystallize the silicon film having a low degree of crystallinity and not significantly affect the substrate, the wavelength of 0.6 to 4 μm is advantageous.

[0020]

[Embodiment] [Embodiment 1] This embodiment is shown in FIGS.
This is an example of forming a circuit in which a P-channel type TFT (referred to as PTFT) and a N-channel type TFT (referred to as NTFT) using a crystalline silicon film formed on the glass substrate shown in FIG. The configuration of this embodiment can be applied to a switching element of a pixel electrode of an active liquid crystal display device, a peripheral driver circuit, an image sensor, and a three-dimensional integrated circuit.

FIG. 1 shows a sectional view of the manufacturing process of this embodiment. First, a 2000-Å-thick silicon oxide base film 102 was formed on a substrate (Corning 7059) 101 by a sputtering method. The substrate is annealed at a temperature higher than the strain point before or after the formation of the base film, and then gradually cooled to the strain point or less at 0.1 to 1.0 ° C./min.
Subsequent shrinkage of the substrate in the subsequent steps (including the infrared light irradiation of the present invention) accompanied by a temperature rise facilitates mask alignment. For the Corning 7059 substrate, after annealing at 620 to 660 ° C. for 1 to 4 hours, it is gradually cooled at 0.1 to 1.0 ° C./min, preferably 0.03 to 0.3 ° C./min, and 400 to
It is recommended to take out when the temperature has dropped to 500 ° C.

Then, an intrinsic (I-type) amorphous silicon film 103 having a thickness of 300 to 1500 Å, for example 800 Å, was formed by the plasma CVD method. Furthermore, a thickness of 100 to 800 Å, for example, 2 by plasma CVD method.
A silicon oxide film 104 of 00Å was deposited. This becomes a protective film in the following thermal annealing process and prevents the film surface from being roughened.

Next, under a nitrogen atmosphere (atmospheric pressure), 600 ° C.
Thermally annealed for 4 hours. By this thermal annealing,
The surplus hydrogen in the silicon film was released, and the film exhibited a low degree of crystallinity. However, even when the silicon film was analyzed by Raman scattering spectroscopy, a peak due to the silicon crystal could not be clearly recognized like a polycrystalline silicon film in which 90% or more was crystallized. The crystallinity of the film at this time is such that at least nucleation for crystal growth occurs and the crystallized area is 50% or less, typically only 1 to 10%. Observation with a TEM (transmission electron microscope) is 1000 Å or less, typically 2
Fine crystals of 0 to 100Å were observed. In order to nucleate the crystallization about 3 to 30 times, the silicon film is preliminarily ion-implanted with 1 × 10 ¹⁴ to 1 × 10 ¹⁶ cm ^-2.
It was effective to implant silicon ions at a dose of. (Fig. 1 (A))

After this step, the silicon film is patterned.
By etching, an island-shaped active layer 105 of the TFT was formed. The size of the active layer 105 is determined in consideration of the channel length and channel width of the TFT. 50μ for small ones
m × 20μm, large size 100μm × 1000μ
It was m. Many such active layers were formed on the substrate.

Then, 0.6 to 4 μm, here 0.8
The active layer was crystallized by irradiating infrared light having a peak at ˜1.4 μm for 30 to 180 seconds (RTA step). Temperature is 800 to 1300 ° C, typically 900 to 1200
C., for example, 1100.degree. Irradiation was carried out in an H ₂ atmosphere in order to improve the surface condition of the active layer. In this step, since the active layer is selectively heated, the heating of the glass substrate can be minimized. And, it is very effective in reducing defects and dangling bonds in the active layer. (Fig. 1 (B))

A halogen lamp was used as the infrared light source. The intensity of visible / near infrared light was adjusted so that the temperature on the single crystal silicon wafer of the monitor was 800 to 1300 ° C, typically 900 to 1200 ° C. Specifically, the temperature of the thermocouple embedded in the silicon wafer was monitored and fed back to the infrared light source. The temperature of the silicon surface on the glass substrate is about 2/3 of that.
It is estimated to have decreased to some extent. In this embodiment,
The temperature rise / fall was performed as shown in FIG. 4 (A) or (B). The temperature rise was constant, the speed was 50 to 200 ° C./sec, and the temperature decrease was 20 to 100 ° C. by natural cooling.

FIG. 4A shows a general temperature cycle, which is composed of three processes of a temperature raising time a, a holding time b, and a temperature lowering time c. However, in this case, since the sample is rapidly heated and cooled from room temperature to a temperature as high as 1000 ° C., and further from a high temperature state to room temperature, it has a great influence on the silicon film and the substrate, and the silicon film may be peeled off. high.

In order to solve this problem, FIG.
As described above, a preheat time d or a postheat time f is provided before reaching the holding time, and a temperature lower than the strain point of the glass substrate by 50 to 200 ° C. before reaching the holding time, for example, 400.
It is desirable to maintain a temperature of up to 700 ° C. that does not significantly affect the substrate or film. As the preheating time d and the postheating time f, 30 seconds to 30 minutes was preferable. Especially, 300 × 400mm ² , 400 × 600mm
It is desirable that the large-area substrate of ^{2 has} a uniform temperature so as not to locally expand and contract thermally.

During irradiation of visible / infrared light, a silicon oxide or silicon nitride film may be formed on the surface as a protective film. This is to improve the surface condition of the silicon film 105. In this embodiment, in order to improve the condition of the surface of the silicon film 105, it was performed in an H ₂ atmosphere.
0.1 to 10% by volume of HCl, other hydrogen halides, or compounds of fluorine, chlorine, and bromine may be mixed in the H ₂ atmosphere.

Since the visible / near-infrared light irradiation selectively heats the crystallized silicon film, the heating of the glass substrate can be minimized. And, it is very effective in reducing defects and intangible bonds in the silicon film.
In addition, after the RTA process is completed, 200 to 50
Performing hydrogen annealing at 0 ° C., typically 350 ° C. is also effective in reducing defects. This is 1 × 1
The same effect can be obtained by ion-doping hydrogen with an amount of 0 ¹³ to 1 × 10 ¹⁵ cm ⁻² and further performing a heat treatment at 200 to 300 ° C.

After the RTA process, a silicon oxide film 106 having a thickness of 1000 Å was formed as a gate insulating film by the plasma CVD method. TEOS (tetra-ethoxy-silane, Si (OC ₂ H ₅ ) ₄ ) and oxygen were used as the source gas for CVD, and the substrate temperature during film formation was 300 to 550 ° C., for example 400 ° C.

A silicon oxide film 106 to be the gate insulating film
After the film formation, the visible / near infrared irradiation was performed again under the same conditions as in the RTA step. This irradiation of visible / near-infrared rays was able to eliminate the levels mainly at the interface between the silicon oxide film 106 and the silicon film 105 and in the vicinity thereof.
This is extremely useful for an insulating gate type field effect semiconductor device in which the interface characteristics between the gate insulating film and the channel formation region are extremely important.

Subsequently, by the sputtering method,
A film having a thickness of 6000 to 8000 Å, for example, 6000 Å (containing 0.01 to 0.25% of the rare earth element of the periodic table IIIa) was formed. Then, the aluminum film was etched to form the gate electrodes 107 and 109.
Further, the surface of the aluminum electrode was anodized to form oxide layers 108 and 110 on the surface. This anodic oxidation was performed in an ethylene glycol solution containing 1-5% tartaric acid. The thickness of the obtained oxide layers 108 and 110 was 2000Å. Since the oxides 108 and 110 have a thickness to form the offset gate region in the subsequent ion doping process, the length of the offset gate region can be determined in the anodizing process.

Next, an ion doping method (also called a plasma doping method) is used to mask the gate electrode portion (that is, the gate electrode 107 and the oxide layer 108 around the gate electrode 109, the gate electrode 109 and the oxide layer 110 around it).
Impurities that impart P or N conductivity type in a self-aligned manner were added to the silicon film 105. Phosphine (PH ₃ ) and diborane (B ₂ H ₆ ) are used as the doping gas,
In the former case, the acceleration voltage is 60 to 90 kV, for example 80
kV, in the latter case 40-80 kV, for example 65 kV
And The dose amount was 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, phosphorus was 2 × 10 ¹⁵ cm ⁻² and boron was 5 × 10 ¹⁵ . Upon doping, one region was covered with a photoresist to selectively dope each element. As a result, N-type impurity regions 114 and 11
6. P-type impurity regions 111 and 113 are formed, and a P-channel type TFT (PTFT) region and an N-channel type TF are formed.
A region with T (NTFT) could be formed.

After that, annealing was performed by irradiation with laser light. As the laser light, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was used, but another laser may be used. The laser light irradiation condition is that the energy density is 200 to 400 mJ / c.
m ² , for example, 250 mJ / cm ^2, and 2 per place
Irradiation was performed for 10 shots, for example, 2 shots. The effect may be increased by heating the substrate to about 200 to 450 ° C. during the irradiation of the laser light. (Fig. 1
(C))

Further, this step may be a method of irradiating visible / near infrared light (RTA method). In the visible / near infrared, crystallized silicon, phosphorus or boron is 10 ¹⁷
Amorphous silicon added to -10 ²¹ cm ^-3 is easily absorbed, and effective annealing comparable to thermal annealing at 1000 ° C or higher can be performed. When phosphorus or boron is added, the light is sufficiently absorbed even in the near infrared due to the impurity scattering. This can be fully inferred because it is black even when observed with the naked eye. On the other hand, since it is difficult to be absorbed by the glass substrate, it does not require heating the glass substrate to a high temperature and requires only a short treatment time, so it can be said that it is the optimal method in the process where shrinkage of the glass substrate is a problem. .

Then, a silicon oxide film 11 having a thickness of 6000Å is formed.
7 was formed as an interlayer insulator by the plasma CVD method. As this interlayer insulator, polyimide or a two-layer film of silicon oxide and polyimide may be used. Further, a contact hole is formed, and a TFT electrode / wiring 1 is formed of a metal material, for example, a multilayer film of titanium nitride and aluminum.
18, 120, 119 were formed. Finally, anneal at 350 ° C. for 30 minutes in a hydrogen atmosphere of 1 atm, and
We have completed a semiconductor circuit that has a complementary structure. (Fig. 1
(D))

Particularly, in the present invention, R by visible / near infrared light is used.
It is important to neutralize the dangling bonds generated in the TA step by adding hydrogen in a subsequent step by heating at 250 to 400 ° C. in a hydrogen atmosphere. As described above, according to the present invention, the mass productivity is improved, and the leakage current (off current) when the gate electrode is 0 V or the reverse bias voltage (negative in the case of NTFT) is applied to the gate electrode Compared with the method, it can be lowered by 1 to 2 digits. The circuit shown above is based on PTFT and NTF.
Although it is a CMOS structure in which T and T are provided in a complementary manner, it is also possible to fabricate two independent TFTs at the same time by fabricating two TFTs at the same time and cutting them at the center in the above process.

[Embodiment 2] In this embodiment, an N-channel TFT is used in an active matrix type liquid crystal display device.
Is an example in which each pixel is provided as a switching element. Although only one pixel will be described below, a large number (generally hundreds of thousands) of other pixels are simultaneously formed with the same structure. It goes without saying that a P-channel TFT may be used instead of the N-channel TFT. Further, instead of being provided in the pixel portion of the liquid crystal display device, it can be used in the peripheral circuit portion. It can also be used for image sensors and other devices. That is, if it is used as a thin film transistor, its use is not particularly limited.

An outline of the manufacturing process of this embodiment is shown in FIG.
In this embodiment, the substrate 200 is an NA45 glass substrate (thickness 1.1 mm, 300 × 400 mm, strain point 61).
0 ° C) was used. First, as a base film, plasma CV
An aluminum nitride film 201 having a thickness of 2000 Å is formed by the D method or the sputtering method, and a silicon oxide film 202 is further formed on the aluminum nitride film 201 by plasma CVD as another base film.
It was formed to a thickness of 00Å. Aluminum nitride has thermal conductivity 10 times or more higher than that of a glass substrate, and is preferable for maintaining temperature uniformity in a large-area substrate. Further, oxygen may be added to aluminum nitride in an amount of 0.01 to 20 atomic% with respect to nitrogen in order to make the coefficient of thermal expansion close to that of the glass substrate and improve the adhesion.

To form aluminum nitride by the plasma CVD method, trimethylaluminum (Al (CH ₃ ) ₃ ) and ammonia may be used as raw materials. Further, in order to form by sputtering, reactive sputtering may be performed by using an aluminum target with an atmosphere of nitrogen or ammonia. TEOS and oxygen were used as source gases for the CVD of the silicon oxide film 202. Furthermore, LPCVD method or plasma CVD
The amorphous silicon film 203 by 1000 Å, the silicon oxide film 20
4 was formed to a thickness of 200Å. And 55
Thermal annealing was performed at 0 ° C. for 1 hour. (Fig. 2 (A))

After this thermal annealing step, the silicon film was patterned and etched to leave only the island-like active layer 205 of the TFT and remove the others. And the island-shaped active layer 2
05 was irradiated with visible / near infrared light to improve the crystallinity of the silicon film. The temperature was 1100 ° C. and the time was 30 seconds. Since the heat conduction through the silicon film is uniform due to the aluminum nitride, the patterning / etching step may be performed after the visible / near infrared light irradiation. (Fig. 2
(B))

Further, tetra ethoxy silane (TEO
S) as a raw material, and a gate insulating film of silicon oxide (thickness 700 to 180) is formed by a plasma CVD method in an oxygen atmosphere.
0Å, typically 1200Å) 206 was formed. The substrate temperature was 350 ° C. Next, a known film containing polycrystalline silicon as a main component was formed by the LPCVD method, and this was etched to form a gate electrode 207. Phosphorus was introduced into polycrystalline silicon as an impurity in an amount of 0.1 to 5 atomic% in order to improve conductivity.

After that, phosphorus is implanted as an N-type impurity by an ion doping method to self-align with the source region 20.
8, the channel formation region 209, and the drain region 210 were formed. Then, by irradiating the KrF laser beam, the crystallinity of the silicon film whose crystallinity was deteriorated due to the ion implantation was improved. At this time, the energy density of the laser light was set to 250 to 300 mJ / cm ² . By this laser irradiation, the sheet resistance of the source / drain of this TFT became 300 to 800 Ω / cm ² . In addition,
When a low-concentration drain (LDD) structure in which the doping concentration is lower than usual is used, the sheet resistance is 10 to 2
It becomes 00 kΩ / □. The step of annealing by laser irradiation may be performed by lamp annealing of visible / near infrared light. (Fig. 2 (C))

After that, an interlayer insulator 211 is formed of silicon oxide or polyimide, and the pixel electrode 212 is further formed.
Was formed of ITO. Then, a contact hole is formed, and chromium /
The electrodes 213 and 214 were formed of an aluminum multilayer film, and one of the electrodes 214 was connected to the ITO 212. Finally, hydrogenation was performed by annealing in hydrogen at 200 to 400 ° C. for 2 hours. In this way
The TFT is completed. This step is simultaneously performed on many other pixel regions at the same time. In addition, in order to further improve the moisture resistance, a passivation film may be formed on the entire surface with silicon nitride or the like. (Fig. 2 (D))

The active matrix pixel transistor shown in this embodiment is not required to operate at such a high speed. Therefore, in this example, the time of the first thermal annealing was set to 1 hour, which was shorter than that in the case of Example 1, in order to shorten the process time. Therefore, the crystallinity of the silicon film obtained in this example was inferior to that in Example 1, but
Sufficient static and dynamic characteristics were obtained for the switching transistor of the active matrix circuit.

[Embodiment 3] This embodiment will be described with reference to FIG. As the substrate, a glass substrate having a strain point of 550 to 650 ° C., for example, AN2 (strain point of 616 ° C.) is used, and as in Example 1, in order to prevent shrinkage, it is annealed in advance at 670 ° C. for 4 hours, and then 0. After slowly cooling to 450 ° C. at 1 ° C./min, the one taken out was used. First, a base film 302 was formed on a substrate 301, and further an amorphous silicon film 303 having a thickness of 300 to 800 Å and a silicon oxide film 304 having a thickness of 200 Å were formed by a plasma CVD method.

Then, thermal annealing was carried out at 620 ° C. for 30 minutes. After the thermal annealing, the substrate was rapidly cooled to 450 ° C at a rate of 2 to 200 ° C / sec, preferably 10 ° C / sec or more. This is to prevent the substrate from shrinking due to this thermal annealing process. In such an annealing furnace in which rapid cooling is impossible, the same effect can be obtained by taking the substrate out of the furnace and leaving it at room temperature. Further, although AN2 is used as the substrate here, other glass substrates having a strain point of 550 to 680 ° C., for example, Corning 1733 (strain point 640 ° C.) or L
A substrate such as E30 (strain point 625 ° C.) may be used.

In this embodiment, the thermal annealing temperature is higher than in the first and second embodiments, and the strain point (616) of AN2 is set.
However, even if a heat treatment / slow cooling treatment is performed in advance, it is difficult to suppress the shrinkage of the substrate. In such a case, rapid cooling from the annealing temperature as described above is effective. (FIG. 3A) Next, the silicon film 303 is patterned and etched to
Island-shaped active layer regions 306 and 307 were formed. The etching of the active layer was performed by the RIE method having anisotropy in the vertical direction. (Fig. 3 (B))

Then, a silicon oxide or silicon nitride film 307 having a thickness of 200 to 3000 Å was formed by the plasma CVD method. Low pressure CVD or photo CVD may be used to form the silicon nitride film. Then, RTA processing of visible / near infrared light was performed in the same manner as in Example 1. The conditions were the same as in Example 1. In this embodiment, a protective film of silicon oxide or silicon nitride is formed on the surface of the active layer during visible / near-infrared light irradiation. Therefore, the surface is not roughened or contaminated during infrared light irradiation. I was able to prevent it. (Fig. 3 (C))

After irradiation with visible / near infrared light, the protective film 307 was removed. After that, the gate insulating film 30 is formed as in the first embodiment.
8. Gate electrodes 309 and 310 were formed, an impurity region was formed by the ion doping method, and this was activated by laser irradiation. (FIG. 3D) Further, an interlayer insulator 311 is formed, a contact hole is formed in this, and metal wirings 312, 313, 314 are formed.
Was formed. (Fig. 3 (E))

In this way, a complementary TFT circuit was formed. In this embodiment, a protective film is formed on the surface of the active layer upon irradiation with visible / near infrared light, so that the surface is prevented from being roughened or contaminated. Therefore, the characteristics (electric field mobility and threshold voltage) and reliability of the TFT of this example were extremely good. Further, as is apparent from this example, the present invention was particularly effective for a substrate material having a glass transition point of 550 to 680 ° C.

[0053]

EFFECTS OF THE INVENTION By simultaneously irradiating a silicon film crystallized by means such as thermal annealing with intense light of a wavelength such as visible / near infrared light, the crystallinity is improved and at the same time. The film quality could be densified and a silicon film having good crystallinity could be obtained. Especially when thermal annealing is adopted, the temperature and time are 520 to 520.
620 ° C. (preferably 550 to 600 ° C.) and 1 to 4 hours were preferable.

Further, in order to improve the characteristics of the gate insulating film, after forming an insulating film on the crystalline silicon film obtained by the present invention, visible / near red in nitrous oxide (N ₂ O) or ammonia. Annealing may be performed by irradiation with light having a wavelength such as external light. By this step, the interface state can be reduced. After these steps, hydrogenation annealing can be performed in a hydrogen atmosphere at 200 to 450 ° C. to add hydrogen to the silicon film to remove / neutralize dangling bonds.

In the present invention, when the thermal annealing is adopted, the time required for it can be set within 4 hours,
It can be greatly reduced from the conventional tens of hours. Further, since the annealing time is shorter and shorter than the conventional one, the influence on the substrate in the annealing process is sufficiently small. Also, in the subsequent RTA step, the wavelength of the light used is 0.6 to 4 μm, and even if a glass material is used for the substrate, it is rapidly cooled after that, so that it softens or contracts, which is an industrial factor. It does not deform enough to make it unusable. As described above, the present invention is industrially useful, and in particular, the present invention is extremely effective for forming an insulating gate type semiconductor device.

[Brief description of drawings]

1A to 1C show steps of manufacturing a TFT of Example 1. FIG.

FIG. 2 shows a process of manufacturing a TFT of Example 2.

FIG. 3 shows a manufacturing process of a TFT of Example 3.

FIG. 4 shows an example of temperature setting according to the first embodiment.

[Explanation of symbols]

101 glass substrate 102 Base film (silicon oxide film) 103 Silicon film 104 Silicon oxide film 105 Island-shaped silicon film (active layer) 106 Gate insulating film (silicon oxide film) 107, 109 Gate electrode (aluminum) 108, 110 Anodized layer (aluminum oxide) 111, 114 Source (drain) region 112,115 Channel forming region 113, 116 Drain (source) region 117 Interlayer insulator 118-120 electrodes

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-5-152325 (JP, A) JP-A-3-218640 (JP, A) JP-A-3-22540 (JP, A) JP-A-3- 24736 (JP, A) JP 3-227525 (JP, A) JP 3-293719 (JP, A) JP 5-67635 (JP, A) JP 3-265143 (JP, A) JP-A-3-181119 (JP, A) JP-A-3-34434 (JP, A) JP-A-4-80914 (JP, A) JP-A-3-289129 (JP, A) Sakai Tsuruo, high-purity silica Applied Technology, Japan, CMC Co., Ltd., March 1, 1991, 1st edition, p. 131-132 (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/336 H01L 29/786 H01L 21/20

Claims (4)

(57) [Claims] 1. A first step of forming a non-single crystal silicon film on a glass substrate which absorbs 0.1 to 10% of near infrared rays or visible light having a wavelength of 0.6 μm to 4 μm, and the non-single crystal. A second step of crystallizing the silicon film, and a third step of irradiating the near-infrared ray or the visible ray having the wavelength of 0.6 μm to 4 μm to promote the crystallization of the crystallized non-single-crystal silicon film. In the third step, the non-single-crystal silicon film is irradiated with the near-infrared ray or visible light at 400 to 700 ° C.
Of the crystallized non-single-crystal silicon film obtained by the second step is performed by preheating, then raising the temperature to 800 to 1300 ° C., and then performing post heating at 400 to 700 ° C. A method for manufacturing a semiconductor device, wherein the degree is 1 to 50%. 2. The method for manufacturing a semiconductor device according to claim 1 , wherein the non-single-crystal silicon film is formed on a glass substrate having a thin film formed on the surface thereof. 3. The method for manufacturing a semiconductor device according to claim 2 , wherein the second step is performed by thermal annealing. 4. The method for manufacturing a semiconductor device according to claim 3 , wherein the temperature of the thermal annealing is 520 to 620 ° C.