JPH07183536A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH07183536A
JPH07183536A JP34671293A JP34671293A JPH07183536A JP H07183536 A JPH07183536 A JP H07183536A JP 34671293 A JP34671293 A JP 34671293A JP 34671293 A JP34671293 A JP 34671293A JP H07183536 A JPH07183536 A JP H07183536A
Authority
JP
Japan
Prior art keywords
silicon film
tft
peripheral circuit
region
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP34671293A
Other languages
Japanese (ja)
Other versions
JP2762219B2 (en
Inventor
Shoji Miyanaga
昭治 宮永
Hisashi Otani
久 大谷
Yasuhiko Takemura
保彦 竹村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP34671293A priority Critical patent/JP2762219B2/en
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to KR1019940035849A priority patent/KR100319332B1/en
Publication of JPH07183536A publication Critical patent/JPH07183536A/en
Priority to US08/592,513 priority patent/US5705829A/en
Application granted granted Critical
Publication of JP2762219B2 publication Critical patent/JP2762219B2/en
Priority to KR1020000022831A priority patent/KR100315888B1/en
Priority to US10/135,773 priority patent/US6624445B2/en
Priority to US10/747,165 priority patent/US6955954B2/en
Priority to US11/250,635 priority patent/US7402471B2/en
Priority to US12/175,481 priority patent/US7700421B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To improve a crystalline silicon film of a TFT in crystallinity and to obtain TFTs used for a picture element region and other TFTs used for a peripheral circuit region through the same process by a method wherein the crystalline silicon film of a TFT arranged in a peripheral circuit region is irradiated with laser rays or string light rays. CONSTITUTION:A prime film 202 of silicon oxide and an amorphous silicon film 203 are formed on a substrate 201. A nickel-containing acetate solution 205 which promotes crystallization is applied onto the amorphous silicon film 203. Nickel contained in an acetate solution is 10ppm in concentration. Thereafter, the substrate 201 is annealed in a nitrogen atmosphere at a temperature of 550 deg.C for four hours to turn the silicon film 203 crystalline. A this point, the silicon film 203 starts crystallizing as nickel in contact with the silicon film starts diffusing. The crystallization of the silicon film tapes placed nearly along a direction vertical to the substrate 201. After a crystallization process, the silicon film 203 is improved in crystallinity by irradiation with laser rays 216. Only TFTs located in a peripheral circuit region are subjected to the irradiation process.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、アクティブマトリクス
型の液晶表示装置の構成に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of an active matrix type liquid crystal display device.

【0002】[0002]

【従来の技術】画素電極にTFT(薄膜トランジスタ)
を配置し、画素電極のスイッチングを行なうアクティブ
マトリクス型の液晶表示装置が知られている。またさら
に画素電極に配置されたTFTを駆動するための周辺回
路領域をも同一基板上に形成する一体化された構成も提
案されている。
2. Description of the Related Art TFT (thin film transistor) is used for a pixel electrode.
There is known an active matrix type liquid crystal display device in which the pixel electrodes are arranged and the pixel electrodes are switched. Further, an integrated structure has also been proposed in which a peripheral circuit region for driving a TFT arranged in a pixel electrode is also formed on the same substrate.

【0003】このような画素領域と周辺回路領域とが一
体化されたアクティブマトリクス型の液晶表示装置にお
いては、それぞれの領域において必要とするTFTの特
性は異ならせる必要がある。
In such an active matrix type liquid crystal display device in which the pixel region and the peripheral circuit region are integrated, it is necessary to make the characteristics of the TFT different in each region.

【0004】各画素に配置されるTFTは、画素電極に
電荷を保持させる機能が必要とされる。従って大きな移
動度は要求されないが、OFF電流が小さいことが必要
とされる。
The TFT arranged in each pixel is required to have a function of retaining charges in the pixel electrode. Therefore, a large mobility is not required, but a small OFF current is required.

【0005】一方、周辺回路領域に配置されるTFT
は、画素領域に配置されたTFTをドライブするための
ものとなるので、大きなON電流を流すことができ、高
移動度を有することが必要とされる。、
On the other hand, TFTs arranged in the peripheral circuit area
Since it is for driving the TFT arranged in the pixel region, it is necessary to allow a large ON current to flow and to have high mobility. ,

【0006】[0006]

【発明が解決しようとする課題】本発明は、アクティブ
マトリクス型の液晶表示装置において、同一基板上に形
成される画素領域用のTFTと周辺回路領域用のTFT
とをその必要とする特性を同一工程で得ることを課題と
する。
SUMMARY OF THE INVENTION In an active matrix type liquid crystal display device, the present invention provides a pixel area TFT and a peripheral circuit area TFT formed on the same substrate.
The object is to obtain the required characteristics in the same step.

【0007】[0007]

【課題を解決するための手段】本発明は、アクティブマ
トリクス型の液晶表示装置において、画素領域と周辺回
路領域とに配置されるTFTとを異なる結晶状態の結晶
性珪素膜で構成したことを特徴とする。そして本発明は
上記構成を実現するために、周辺回路領域を構成する結
晶性珪素膜にレーザー光または強光を照射したものを用
いることを特徴とする。
According to the present invention, in an active matrix type liquid crystal display device, TFTs arranged in a pixel region and a peripheral circuit region are formed of crystalline silicon films in different crystal states. And In order to realize the above structure, the present invention is characterized in that a crystalline silicon film forming a peripheral circuit region is irradiated with laser light or strong light.

【0008】結晶性珪素膜を得る方法としては、加熱に
よって非晶質珪素膜を結晶化させる方法が知られている
が、本発明においては、非晶質珪素の結晶化を助長する
元素を非晶質珪素膜に導入することによって、550
℃、4時間程度の加熱工程によって結晶化させる方法を
採用することを特徴とする。
As a method of obtaining a crystalline silicon film, a method of crystallizing an amorphous silicon film by heating is known. In the present invention, an element which promotes crystallization of amorphous silicon is not used. 550 by introducing into the crystalline silicon film
The method is characterized by adopting a method of crystallizing by a heating step at 4 ° C. for about 4 hours.

【0009】結晶化を助長する触媒元素としては、N
i、Pd、Pt、Cu、Ag、Au、In、Sn、Pd
P、As、Sbから選ばれた一種または複数種類の元素
を用いることができる。またVIII族、IIIb族、IVb族、
Vb族元素から選ばれた一種または複数種類の元素を用い
ることもできる。
As a catalyst element for promoting crystallization, N
i, Pd, Pt, Cu, Ag, Au, In, Sn, Pd
One or more kinds of elements selected from P, As and Sb can be used. Group VIII, IIIb, IVb,
It is also possible to use one or more kinds of elements selected from the Vb group elements.

【0010】[0010]

【実施例】 〔実施例1〕本実施例は、アクティブマトリクス型の液
晶表示装置において、周辺回路領域と画素領域に結晶性
珪素膜を用いたTFTを配置した構成に関する。上記周
辺回路領域および画素領域に形成されるTFTは、結晶
化を助長する触媒元素を添加することによって基板垂直
な方向に結晶成長が行われた結晶性珪素膜を用いた構成
を有する。また、周辺回路領域に形成された結晶性珪素
膜はレーザー光または強光の照射によって結晶化がさら
に助長されており、より大きなON電流を探すことがで
き、またより大きな移動度を有する構成となっている。
[Embodiment 1] This embodiment relates to a configuration in which a TFT using a crystalline silicon film is arranged in a peripheral circuit region and a pixel region in an active matrix type liquid crystal display device. The TFT formed in the peripheral circuit region and the pixel region has a structure using a crystalline silicon film in which crystal growth is performed in a direction perpendicular to the substrate by adding a catalytic element that promotes crystallization. In addition, the crystalline silicon film formed in the peripheral circuit region is further promoted to be crystallized by irradiation with laser light or strong light, so that a larger ON current can be searched for and a larger mobility can be obtained. Has become.

【0011】図2および図3に本実施例の作製工程を示
す。図2に示すのは周辺回路用にTFTの作製工程図で
あり、図3に示すのは画素領域に形成されるTFTの作
製工程図である。それぞれの図において符号の同一なも
のは同一の箇所を示す。またそれぞれの作製工程は互い
に対応する。図1は本実施例で作製されるアクティブ型
の液晶表示装置を上面から見た概要図である。本実施例
で示す周辺領域用のTFTと画素領域用のTFTとは、
図1に示すような状態で同一基板上に形成される。図1
には、周辺回路領域A、Bとその冗長回路であるA’、
B’が示されている。この冗長回路A’、B’は、周辺
回路領域A、Bに欠陥が存在する場合に利用される。
2 and 3 show the manufacturing process of this embodiment. FIG. 2 is a manufacturing process diagram of a TFT for a peripheral circuit, and FIG. 3 is a manufacturing process diagram of a TFT formed in a pixel region. In each figure, the same reference numerals indicate the same parts. Further, each manufacturing process corresponds to each other. FIG. 1 is a schematic view of an active type liquid crystal display device manufactured in this example, as viewed from above. The peripheral area TFT and the pixel area TFT shown in this embodiment are
They are formed on the same substrate in the state shown in FIG. Figure 1
In the peripheral circuit areas A and B and their redundant circuits A ′,
B'is shown. The redundant circuits A ′ and B ′ are used when there are defects in the peripheral circuit areas A and B.

【0012】まず、基板201を洗浄し、TEOS(テ
トラ・エトキシ・シラン)と酸素を原料ガスとしてプラ
ズマCVD法によって厚さ2000Åの酸化珪素の下地
膜202を形成する。
First, the substrate 201 is cleaned, and a base film 202 of silicon oxide having a thickness of 2000 Å is formed by a plasma CVD method using TEOS (tetra-ethoxy-silane) and oxygen as source gases.

【0013】そして、プラズマCVD法によって、厚さ
500〜1500Å、例えば1000Åの真性(I型)
の非晶質珪素膜203を成膜する。そして結晶化を助長
する触媒元素であるニッケル元素を含んだ溶液(ここで
は酢酸塩溶液)205塗布する。酢酸溶液中におけるニ
ッケルの濃度は10ppmである。なお、酢酸溶液の塗
布前に極薄い酸化膜(数十Å以下)を形成し、酢酸溶液
の濡れ性を改善することは効果的である。
Then, by plasma CVD method, an intrinsic (I type) having a thickness of 500 to 1500Å, for example, 1000Å
The amorphous silicon film 203 is formed. Then, a solution (here, an acetate solution) 205 containing nickel element which is a catalytic element for promoting crystallization is applied. The concentration of nickel in the acetic acid solution is 10 ppm. It is effective to improve the wettability of the acetic acid solution by forming an extremely thin oxide film (several tens of liters or less) before applying the acetic acid solution.

【0014】ここでは触媒元素を含有した溶液を塗布す
ることにより、非晶質珪素膜にその結晶化を助長する触
媒元素であるニッケルを導入したが、プラズマ処理や蒸
着法やスパッタ法やCVD法によってニッケル膜または
ニッケルを含有する膜を形成するこによって、ニッケル
を導入するのでもよい。
Here, nickel, which is a catalytic element that promotes crystallization of the amorphous silicon film, was introduced into the amorphous silicon film by applying a solution containing the catalytic element. However, plasma treatment, vapor deposition method, sputtering method or CVD method was used. Nickel may be introduced by forming a nickel film or a film containing nickel by.

【0015】この後、窒素雰囲気下で500〜620
℃、例えば550℃、4時間の加熱アニールを行い、珪
素膜203の結晶化を行う。この際、ニッケルと珪素膜
が接触した部分ニッケルが拡散していき、結晶化が起こ
る。そして結晶化は、基板に対して概略垂直な方向に行
われることになる。(図2(A)、図3(A))
Then, in a nitrogen atmosphere, 500 to 620
The silicon film 203 is crystallized by performing heat annealing at 4 ° C., for example, 550 ° C. for 4 hours. At this time, the nickel that is in contact with the nickel film and the silicon film diffuses, and crystallization occurs. Then, crystallization is performed in a direction substantially perpendicular to the substrate. (Fig. 2 (A), Fig. 3 (A))

【0016】上記加熱処理による結晶化工程の後にさら
にレーザー光216の照射により珪素膜203の結晶性
を高める。この工程は、図2(B)に示すように周辺回
路領域のTFTを構成する珪素膜のみに対して行なう。
レーザー光は、KrFエキシマレーザー(波長248n
m、パルス幅20nsec)を用い、250mJ/cm
2 のエネルギー密度で2ショト行なう。またレーザー光
としては他のレーザー光を用いてもよい。このレーザー
光の照射は基板を400℃に加熱して行う。これは、レ
ーザー光の照射によるアニール効果をさらに高めるため
である。
After the crystallization step by the heat treatment, the crystallinity of the silicon film 203 is further enhanced by irradiation with the laser beam 216. This step is performed only on the silicon film forming the TFT in the peripheral circuit region as shown in FIG.
The laser light is a KrF excimer laser (wavelength 248n
m, pulse width 20 nsec), and 250 mJ / cm
It performed 2 Shoto in second energy density. Other laser light may be used as the laser light. This irradiation with laser light is performed by heating the substrate to 400 ° C. This is to further enhance the annealing effect due to laser light irradiation.

【0017】この工程は、強光の照射によるものでもよ
い。例えば波長1.2μmの赤外光を照射することによ
って行なうことができる。赤外光の照射は、数分間で高
温加熱処理したものと同等の効果を得ることができる。
This step may be performed by irradiation with strong light. For example, it can be performed by irradiating infrared light having a wavelength of 1.2 μm. Irradiation with infrared light can achieve the same effect as that obtained by heat treatment at high temperature for several minutes.

【0018】結晶化が終了した状態において、珪素膜中
にニッケル濃度は約1018/cm3であった。そして、
珪素膜203をパターニング後、ドライエッチングし
て、島状の活性層領域208を形成する。
When crystallization was completed, the nickel concentration in the silicon film was about 10 18 / cm 3 . And
After patterning the silicon film 203, dry etching is performed to form an island-shaped active layer region 208.

【0019】その後、100体積%の水蒸気を含む10
気圧、500〜600℃の、代表的には550℃の雰囲
気中において、1時間放置することによって、活性層
(珪素膜)208の表面を酸化させ、酸化珪素膜209
を形成する。酸化珪素膜の厚さは1000Åとする。熱
酸化によって酸化珪素膜209を形成したのち、基板
を、アンモニア雰囲気(1気圧、100%)、400℃
に保持させる。そして、この状態で基板に対して、波長
0.6〜4μm、例えば、0.8〜1.4μmにピーク
をもつ赤外光を30〜180秒照射し、酸化珪素膜20
9に対して窒化処理を施す。なおこの際、雰囲気に0.
1〜10%のHClを混入してもよい。
Thereafter, 10 containing 100% by volume of water vapor
The surface of the active layer (silicon film) 208 is oxidized by leaving it in the atmosphere of 500 to 600 ° C., typically 550 ° C. for 1 hour to oxidize the surface of the silicon oxide film 209.
To form. The thickness of the silicon oxide film is 1000Å. After forming the silicon oxide film 209 by thermal oxidation, the substrate is placed in an ammonia atmosphere (1 atm, 100%) at 400 ° C.
To hold. Then, in this state, the substrate is irradiated with infrared light having a peak at a wavelength of 0.6 to 4 μm, for example, 0.8 to 1.4 μm for 30 to 180 seconds, and the silicon oxide film 20 is irradiated.
A nitriding process is performed on 9. At this time, the atmosphere was 0.
1-10% HCl may be mixed.

【0020】引き続いて、スパッタリング法によって、
厚さ3000〜8000Å、例えば6000Åのアルミ
ニウム(0.01〜0.2%のスカンジウムを含む)を
成膜する。そして、アルミニウム膜をパターニングし
て、ゲイト電極210を形成する。(図2(C)、図3
(C))
Subsequently, by the sputtering method,
A film of aluminum (containing 0.01 to 0.2% scandium) having a thickness of 3000 to 8000Å, for example, 6000Å is formed. Then, the aluminum film is patterned to form the gate electrode 210. (Fig. 2 (C), Fig. 3
(C))

【0021】さらに、このアルミニウムの電極の表面を
陽極酸化して、表面に酸化物層211を形成する。この
陽極酸化は、酒石酸が1〜5%含まれたエチレングリコ
ール溶液中で行う。得られる酸化物層211の厚さは2
000Åである。なお、この酸化物211は、後のイオ
ンドーピング工程において、オフセットゲイト領域を形
成する厚さとなるので、オフセットゲイト領域の長さを
上記陽極酸化工程で決めることができる。(図2
(D)、図3(D))
Further, the surface of the aluminum electrode is anodized to form an oxide layer 211 on the surface. This anodic oxidation is performed in an ethylene glycol solution containing 1-5% tartaric acid. The resulting oxide layer 211 has a thickness of 2
It is 000Å. Since the oxide 211 has a thickness to form the offset gate region in the subsequent ion doping process, the length of the offset gate region can be determined by the anodic oxidation process. (Fig. 2
(D), FIG. 3 (D))

【0022】次に、イオンドーピング法(プラズマドー
ピング法とも言う)によって、活性層領域(ソース/ド
レイン、チャネルを構成する)にゲイト電極部、すなわ
ちゲイト電極210とその周囲の酸化層211をマスク
として、自己整合的にN導電型を付与する不純物(ここ
では燐)を添加する。ドーピングガスとして、フォスフ
ィン(PH3 )を用い、加速電圧を60〜90kV、例
えば80kVとする。ドーズ量は1×1015〜8×10
15cm-2、例えば、4×1015cm-2とする。この結
果、N型の不純物領域212と213を形成することが
できる。図からも明らかなように不純物領域とゲイト電
極とは距離xだけ放れたオフセット状態となる。このよ
うなオフセット状態は、特にゲイト電極に逆電圧(Nチ
ャネルTFTの場合はマイナス)を印加した際のリーク
電流(オフ電流ともいう)を低減する上で有効である。
特に、本実施例のようにアクティブマトリクスの画素を
制御するTFTにおいては良好な画像を得るために画素
電極に蓄積された電荷が逃げないようにリーク電流が低
いことが望まれるので、オフセットを設けることは有効
である。
Next, the gate electrode portion, that is, the gate electrode 210 and the oxide layer 211 around it is used as a mask in the active layer region (which constitutes a source / drain and a channel) by an ion doping method (also called a plasma doping method). An impurity (here, phosphorus) that imparts the N conductivity type is added in a self-aligning manner. Phosphine (PH 3 ) is used as the doping gas, and the acceleration voltage is set to 60 to 90 kV, for example, 80 kV. Dose amount is 1 × 10 15 to 8 × 10
It is set to 15 cm -2 , for example, 4 × 10 15 cm -2 . As a result, N-type impurity regions 212 and 213 can be formed. As is clear from the figure, the impurity region and the gate electrode are in an offset state separated by a distance x. Such an offset state is particularly effective in reducing a leak current (also referred to as an off current) when a reverse voltage (negative in the case of an N-channel TFT) is applied to the gate electrode.
In particular, in the TFT for controlling the pixels of the active matrix as in the present embodiment, it is desired that the leak current is low so that the charges accumulated in the pixel electrode do not escape in order to obtain a good image, and therefore an offset is provided. That is valid.

【0023】その後、レーザー光の照射によってアニー
ルを行う。レーザー光としては、KrFエキシマレーザ
ー(波長248nm、パルス幅20nsec)を用いる
が、他のレーザーであってもよい。レーザー光の照射条
件は、エネルギー密度が200〜400mJ/cm2
例えば250mJ/cm2 とし、一か所につき2〜10
ショット、例えば2ショット照射した。このレーザー光
の照射時に基板を200〜450℃程度に加熱すること
によって、効果を増大せしめてもよい。(図2(E)、
図3(E))
After that, annealing is performed by irradiation with laser light. As the laser light, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) is used, but other laser may be used. The laser light irradiation conditions are energy density of 200 to 400 mJ / cm 2 ,
For example, 250 mJ / cm 2 and 2 to 10 per place
Shot, for example, 2 shots were irradiated. The effect may be increased by heating the substrate to about 200 to 450 ° C. during the irradiation of the laser light. (Fig. 2 (E),
(Fig. 3 (E))

【0024】続いて、厚さ6000Åの酸化珪素膜21
4を層間絶縁物としてプラズマCVD法によって形成す
る。さらに、スピンコーティング法によって透明なポリ
イミド膜215を形成し、表面を平坦化する。
Then, a silicon oxide film 21 having a thickness of 6000Å is formed.
4 as an interlayer insulator is formed by the plasma CVD method. Further, a transparent polyimide film 215 is formed by spin coating to flatten the surface.

【0025】そして、図3(F)に示すように画素領域
に形成されるTFTの出力の一端に連結されるITO電
極300を形成する。このITO電極300は画素電極
として機能する。
Then, as shown in FIG. 3F, an ITO electrode 300 connected to one end of the output of the TFT formed in the pixel region is formed. This ITO electrode 300 functions as a pixel electrode.

【0026】次に層間絶縁物214、215にコンタク
トホールを形成して、金属材料、例えば、窒化チタンと
アルミニウムの多層膜によってTFTの電極・配線21
7、218を形成する。この時図3(F)に示す如く画
素領域に形成されるTFTの一方の電極218を画素電
極であるITO電極300に接続させる。
Next, contact holes are formed in the interlayer insulators 214 and 215, and a TFT electrode / wiring 21 is formed of a metal material, for example, a multilayer film of titanium nitride and aluminum.
7 and 218 are formed. At this time, as shown in FIG. 3F, one electrode 218 of the TFT formed in the pixel region is connected to the ITO electrode 300 which is the pixel electrode.

【0027】最後に、1気圧の水素雰囲気で350℃、
30分のアニールを行い、アクティブマトリクスの画素
回路と該画素回路を駆動する周辺駆動回路を同時に形成
させる。(図2(F)、図3(F))
Finally, in a hydrogen atmosphere at 1 atm, 350 ° C.,
Annealing is performed for 30 minutes to simultaneously form an active matrix pixel circuit and a peripheral drive circuit for driving the pixel circuit. (Figure 2 (F), Figure 3 (F))

【0028】[0028]

【発明の効果】本発明の如くアクティブマトリクス型の
液晶表示装置の画素領域と周辺回路領域とに形成さえる
TFTを結晶化を助長する触媒元素の導入によって結晶
化させ、さらに周辺回路領域に形成されるTFTを構成
する結晶性珪素膜に対してレーザー光または強光を照射
することによって、周辺回路領域に適したTFTを選択
的に構成することができる。
According to the present invention, the TFT formed in the pixel region and the peripheral circuit region of the active matrix type liquid crystal display device is crystallized by the introduction of the catalytic element for promoting the crystallization, and is further formed in the peripheral circuit region. By irradiating the crystalline silicon film forming the TFT with the laser light or the intense light, the TFT suitable for the peripheral circuit region can be selectively formed.

【図面の簡単な説明】[Brief description of drawings]

【図1】 アクティブマトリクス型の液晶表示装置の概
要を示す。
FIG. 1 shows an outline of an active matrix type liquid crystal display device.

【図2】 TFTの作製工程を示す。FIG. 2 shows a manufacturing process of a TFT.

【図3】 TFTの作製工程を示す。FIG. 3 shows a manufacturing process of a TFT.

【符号の説明】[Explanation of symbols]

201・・・・ガラス基板 202・・・・下地膜(酸化珪素膜) 203・・・・非晶質珪素膜 205・・・・酢酸塩溶液 208・・・・活性層 209・・・・酸化珪素膜(ゲイト絶縁膜) 210・・・・ゲイト電極 211・・・・陽極酸化物層 212・・・・ソース/ドレイン領域 213・・・・ドレイン/ソース領域 201 ... Glass substrate 202 ... Base film (silicon oxide film) 203 ... Amorphous silicon film 205 ... Acetate solution 208 ... Active layer 209 ... Oxidation Silicon film (gate insulating film) 210 ... Gate electrode 211 ... Anodic oxide layer 212 ... Source / drain region 213 ... Drain / source region

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/20 8418−4M 21/268 Z 27/12 R ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display location H01L 21/20 8418-4M 21/268 Z 27/12 R

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 絶縁表面を有する基板上に形成された結
晶性珪素膜であって、 前記結晶性珪素膜は結晶化を助長する触媒元素が添加さ
れており、 前記結晶性珪素膜は基板に概略垂直な方向に結晶成長が
成されており、 前記結晶性珪素膜を用いてアクティブマトリクス型の液
晶表示装置の画素領域に配置されるTFTと周辺回路領
域に配置されるTFTとが形成されており、 前記周辺回路領域に配置されたTFTを構成する結晶性
珪素膜は、レーザー光または強光を照射することにより
その結晶性が高められていることを特徴とする半導体装
置。
1. A crystalline silicon film formed on a substrate having an insulating surface, wherein the crystalline silicon film contains a catalytic element for promoting crystallization, and the crystalline silicon film is formed on the substrate. Crystals are grown in a substantially vertical direction, and the crystalline silicon film is used to form TFTs arranged in a pixel region of an active matrix type liquid crystal display device and TFTs arranged in a peripheral circuit region. The crystalline silicon film forming the TFT arranged in the peripheral circuit region has its crystallinity enhanced by irradiation with laser light or strong light.
【請求項2】 アクティブマトリクス型の液晶表示装置
を構成する基板において、 前記基板の表面には、画素領域に配置されるTFTと周
辺回路領域に配置されるTFTとが形成されており、 前記画素領域に配置されるTFTと前記周辺回路領域に
配置されるTFTとは触媒元素が添加された領域を結晶
化させた結晶性珪素膜を用いて構成されており、 前記周辺回路領域の結晶性珪素膜はレーザー光または強
光の照射によりその結晶性が高められていることを特徴
とする半導体装置。
2. A substrate constituting an active matrix type liquid crystal display device, wherein a TFT arranged in a pixel region and a TFT arranged in a peripheral circuit region are formed on a surface of the substrate, The TFT arranged in the region and the TFT arranged in the peripheral circuit region are formed by using a crystalline silicon film obtained by crystallizing the region to which the catalytic element is added, and the crystalline silicon in the peripheral circuit region is formed. A semiconductor device characterized in that the crystallinity of the film is enhanced by irradiation with laser light or intense light.
【請求項3】 絶縁表面を有する基板上に非晶質珪素膜
を形成する工程と、 前記非晶質珪素膜の結晶化を助長する触媒元素を前記非
晶質珪素膜に直接または間接的に接して設ける工程と、 前記非晶質珪素膜を加熱処理し、前記触媒元素が直接ま
たは間接的に接して設けられた領域を結晶化させる工程
と、 該工程において結晶成長が行なわれた領域の一部にレー
ザー光または強光を照射する工程と、 該工程においてレーザー光が照射された領域の結晶性珪
素膜を用いてアクティブマトリクス型の液晶表示装置の
周辺回路部分に配置されるTFTを作製する工程と、 を有する半導体装置の作製方法。
3. A step of forming an amorphous silicon film on a substrate having an insulating surface, and a catalyst element for promoting crystallization of the amorphous silicon film directly or indirectly on the amorphous silicon film. A step of contacting, a step of heat-treating the amorphous silicon film to crystallize a region provided with the catalytic element directly or indirectly, and a step of crystallizing a region where crystal growth is performed in the step. A step of irradiating a part with laser light or strong light, and a TFT arranged in a peripheral circuit portion of an active matrix liquid crystal display device using a crystalline silicon film in a region irradiated with laser light in the step And a method for manufacturing a semiconductor device.
【請求項4】 絶縁表面を有する基板上に配置された複
数のTFTを有し、 前記TFTは結晶化を助長する触媒元素が添加され、基
板に概略垂直な方向に結晶成長した結晶性珪素膜で構成
されており、 前記TFTの一部はアクティブマトリクス型の液晶表示
装置の画素領域に配置され、 前記TFTの他の一部はアクティブマトリクス型の液晶
表示装置の周辺回路領域に配置され、 前記周辺回路領域に配置されたTFTを構成する結晶性
珪素膜はレーザー光または強光の照射によってその結晶
性が高められていることを特徴とする半導体装置。
4. A crystalline silicon film comprising a plurality of TFTs arranged on a substrate having an insulating surface, wherein the TFT is added with a catalytic element for promoting crystallization and crystal-grown in a direction substantially perpendicular to the substrate. A part of the TFT is arranged in a pixel region of an active matrix type liquid crystal display device, and another part of the TFT is arranged in a peripheral circuit region of the active matrix type liquid crystal display device, A semiconductor device characterized in that a crystalline silicon film forming a TFT arranged in a peripheral circuit region has its crystallinity enhanced by irradiation with laser light or strong light.
JP34671293A 1993-12-22 1993-12-22 Semiconductor device and manufacturing method thereof Expired - Lifetime JP2762219B2 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
JP34671293A JP2762219B2 (en) 1993-12-22 1993-12-22 Semiconductor device and manufacturing method thereof
KR1019940035849A KR100319332B1 (en) 1993-12-22 1994-12-22 Semiconductor device and electro-optical device
US08/592,513 US5705829A (en) 1993-12-22 1996-01-26 Semiconductor device formed using a catalyst element capable of promoting crystallization
KR1020000022831A KR100315888B1 (en) 1993-12-22 2000-04-28 An active matrix display device and its manufacturing method
US10/135,773 US6624445B2 (en) 1993-12-22 2002-05-01 Semiconductor device and method of manufacturing the same
US10/747,165 US6955954B2 (en) 1993-12-22 2003-12-30 Semiconductor device and method for manufacturing the same
US11/250,635 US7402471B2 (en) 1993-12-22 2005-10-17 Semiconductor device and method for manufacturing the same
US12/175,481 US7700421B2 (en) 1993-12-22 2008-07-18 Semiconductor device and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34671293A JP2762219B2 (en) 1993-12-22 1993-12-22 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH07183536A true JPH07183536A (en) 1995-07-21
JP2762219B2 JP2762219B2 (en) 1998-06-04

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005526396A (en) * 2002-05-22 2005-09-02 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Active matrix display device and its manufacture
US7232714B2 (en) 2001-11-30 2007-06-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US8334536B2 (en) 2007-03-16 2012-12-18 Samsung Display Co., Ltd. Thin film transistor, organic light emitting diode display device having the same, flat panel display device, and semiconductor device, and methods of fabricating the same
US8455044B2 (en) 2010-11-26 2013-06-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor film, method for manufacturing the same, and power storage device
US8896098B2 (en) 2010-05-28 2014-11-25 Semiconductor Energy Laboratory Co., Ltd. Power storage device and method for manufacturing the same
US10141120B2 (en) 2010-02-26 2018-11-27 Semiconductor Energy Laboratory Co., Ltd. Power storage system and manufacturing method thereof and secondary battery and capacitor

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Publication number Priority date Publication date Assignee Title
JPS6445162A (en) * 1987-08-13 1989-02-17 Hitachi Ltd Manufacture of semiconductor device
JPH03280420A (en) * 1990-03-29 1991-12-11 G T C:Kk Manufacture of semiconductor thin film

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
JPS6445162A (en) * 1987-08-13 1989-02-17 Hitachi Ltd Manufacture of semiconductor device
JPH03280420A (en) * 1990-03-29 1991-12-11 G T C:Kk Manufacture of semiconductor thin film

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7232714B2 (en) 2001-11-30 2007-06-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US7538348B2 (en) 2001-11-30 2009-05-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US7935968B2 (en) 2001-11-30 2011-05-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2005526396A (en) * 2002-05-22 2005-09-02 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Active matrix display device and its manufacture
US8334536B2 (en) 2007-03-16 2012-12-18 Samsung Display Co., Ltd. Thin film transistor, organic light emitting diode display device having the same, flat panel display device, and semiconductor device, and methods of fabricating the same
US10141120B2 (en) 2010-02-26 2018-11-27 Semiconductor Energy Laboratory Co., Ltd. Power storage system and manufacturing method thereof and secondary battery and capacitor
US8896098B2 (en) 2010-05-28 2014-11-25 Semiconductor Energy Laboratory Co., Ltd. Power storage device and method for manufacturing the same
US8455044B2 (en) 2010-11-26 2013-06-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor film, method for manufacturing the same, and power storage device
US8643182B2 (en) 2010-11-26 2014-02-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor film, method for manufacturing the same, and power storage device

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