JP3488441B2 - Method for manufacturing active liquid crystal display device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a thin film transistor (TFT) or a thin film diode (T) formed on an insulating substrate such as glass or various substrates.
FD) or a thin film integrated circuit to which they are applied, in particular, a method for manufacturing a thin film integrated circuit for an active liquid crystal display device (liquid crystal display).

[0002]

2. Description of the Related Art In recent years, semiconductor devices having TFTs on an insulating substrate such as glass, for example, active type liquid crystal display devices using TFTs for driving pixels and image sensors have been developed. As a glass substrate, Corning 7 is used due to problems such as precipitation of impurities from the glass substrate and price problems.
059 glass is commonly used. The 7059 glass has a transition temperature of 628 ° C and a strain point of 593 ° C. As other practical industrial glass materials having a strain point of 550 to 650 ° C., those shown in Table 1 are known.

[0003]

[Table 1]

Thin film silicon semiconductors are generally used for the TFTs used in these devices. The thin-film silicon semiconductor is roughly classified into two, that is, an amorphous silicon semiconductor (a-Si) and a crystalline silicon semiconductor. Amorphous silicon semiconductors are the most commonly used because they have a low manufacturing temperature, can be relatively easily manufactured by the vapor phase method, and have high mass productivity. Since it is inferior to the silicon semiconductors it has,
In order to obtain higher speed characteristics in the future, establishment of a method for manufacturing a TFT made of a crystalline silicon semiconductor has been strongly demanded. As the crystalline silicon semiconductor, polycrystalline silicon, microcrystalline silicon, amorphous silicon containing a crystalline component, semi-amorphous silicon having an intermediate state between crystalline and amorphous are known. .

As a method for obtaining these thin film silicon semiconductors having crystallinity, an amorphous semiconductor film is formed and then heat energy is applied (thermal annealing) for a long time to obtain crystallinity. The method of burrowing is known. However, it is necessary to set the heating temperature to a high temperature of 600 ° C. or higher, which causes a problem that the substrate contracts irreversibly. In particular, it has been impossible to perform such high temperature processing after the patterning step. Further, since the heating time required for crystallization reaches several tens of hours or more, it is necessary to shorten the heating time.

With respect to such a problem, recently, by adding a certain metal element having an effect as a catalyst for promoting crystallization, the crystallization temperature is lowered, and
It was found that the crystallization time can be shortened. Examples of metal elements (catalytic metal elements) that promote crystallization used for such purposes include Fe, Co, Ni, Ru, Rh, and P.
d, Os, Ir, Pt, Sc, Ti, V, Cr, Mn,
The effects of Cu, Zn, Au and Ag have been confirmed.

These elements are distributed over the entire surface of the silicon film.
If it is introduced evenly, crystal growth occurs in the direction perpendicular to the film, that is, in the direction of the film thickness, whereas it is introduced into a specific part of the silicon film and the part introduced when crystallization is performed is used as a starting point to surround the film. Has a characteristic that the crystallized region expands (lateral growth), and the silicon film crystallized in this way exhibits higher field effect mobility than that in which the catalytic metal element is uniformly introduced. .

However, in order to selectively introduce the catalytic metal element as described above, patterning must be performed before the thermal annealing step for crystallization, and the introduction of the catalytic metal element due to the contraction of the substrate described above. There was a case where the pattern of was significantly shifted from the patterns of other elements and circuits. FIG. 4 shows an example of manufacturing a TFT by using such a means. Area 4 written with a dotted line in FIG.
Reference numerals 02 and 403 respectively indicate ones where the active layer (silicon film) and the gate electrode should be originally patterned. A rectangular region 401 indicated by a solid line is a pattern into which a catalytic metal element is introduced.

By this step, when the catalytic metal element is introduced and then thermal annealing is performed, the region 404 indicated by the ellipse in FIG. 4B is crystallized. That is, the area 404
Is a lateral crystal region. The size of this ellipse depends on the concentration of the catalytic metal element and the thermal annealing time / temperature. Figure 4
As shown in (B), if the gate electrode and the active layer are formed at the positions where they should be, the channel forming region of the TFT is formed in the lateral crystal region, and there is no problem.
However, since the substrate actually shrinks due to the thermal annealing process, the gate electrode and the active layer are each 40
5, 406, the region 404 and the channel formation region do not overlap. That is, in the channel formation region, the region shown by the hatched portion 407 remains amorphous. As a result, the characteristics of the TFT are significantly deteriorated.

Due to the shrinkage of the substrate, it has been extremely difficult to perform patterning before the treatment at a high temperature. The high temperature in this case varies depending on the type of the substrate, but it is a temperature of 500 ° C. or higher in comparatively often used Corning No. 7059 glass.

[0011]

SUMMARY OF THE INVENTION The present invention provides means for solving the above problems. More specifically, a means for suppressing the contraction of the substrate is disclosed, and a means for obtaining a semiconductor circuit / element having a higher yield and better characteristics is provided.

[0012]

According to the present invention, a glass substrate is thermally annealed at a temperature equal to or higher than its strain point (strain temperature), preferably equal to or higher than its glass transition point, and then 2 ° C./min or less, preferably 0. 5 ° C / min or less, more preferably 0.
By gradually cooling to a temperature below the strain point at a rate of 3 ° C./minute or less, shrinkage of the glass substrate itself in subsequent heat treatment is suppressed. The cooling rate varies depending on the type of substrate. Generally, the lower the temperature lowering rate, the better the characteristics obtained. However, if the temperature lowering rate is slower, the processing time becomes longer and the mass productivity is lowered. Therefore, in selecting the cooling rate, the processing time and the required characteristics must be taken into consideration. This heat treatment may be performed in an oxidizing or nitriding atmosphere.

Further, after forming an appropriate base film on the substrate thus treated, an amorphous silicon film is formed and crystallized. As the base film, a silicon oxide film,
It is preferable to use a silicon nitride film, aluminum nitride, or a multilayer film in which two or more layers are stacked. To perform the thermal annealing as described above, the following method may be used.
FIG. 8 shows an example of the heating furnace used in the present invention, in which a quartz reaction tube 11, a substrate holding means (substrate holder) 12, and a substrate 13 arranged horizontally are shown. Further, although not shown in the figure, this apparatus is provided with a heater for heating the reaction tube 11 from the outside. Further, it is provided with means for supplying a predetermined gas into the reaction tube and means for moving the substrate holding means from the reaction tube to the outside.

FIG. 8 shows a state in which the glass substrate 13 is horizontally held by the substrate holding portion 12. Here, holding the glass substrate horizontally was effective in preventing the substrate from bending and impairing its planarity. Such a configuration is useful when a step of applying a temperature above the strain point to the glass substrate is required. In addition, in the subsequent thermal annealing process such as crystallization and activation of the silicon film, the above-mentioned configuration may be adopted.

In addition, film formation performed after the above-mentioned pre-heat treatment,
In the heat treatment required for crystal growth, oxidation, activation, etc., it is important to quench the material after heating at a rate of 10 ° C / min to 300 ° C / min. Especially ± 1 near the strain point of glass material
At 00 ° C., when the glass material was rapidly cooled at the above rate, the expansion and contraction of the glass material could be suppressed. For example, Corning 7
In a process that requires a treatment temperature of 493 to 693 ° C. for 059 glass, at least quenching to 493 ° C. is effective in suppressing further shrinkage (elongation in some cases) to 30 ppm or less.

[0016]

The glass substrate shrinks by heating, especially when it is cooled slowly after the heating, the glass substrate shrinks extremely greatly, and at the same time, the local stress in the glass substrate is relaxed. As a result, the greater the shrinkage, the smaller the shrinkage of the substrate in the subsequent heating step. Further, the higher the heat treatment temperature, the greater the effect. Therefore, even if the heat treatment is performed again thereafter, the stress of the glass substrate is relaxed, and there is little room for further shrinking or warping. Further, it was found that in the heat treatment step after the crystallization annealing or the like, the glass substrate subjected to the thermal annealing treatment of the present invention hardly shrinks when it is rapidly cooled from the heating temperature.

For example, for Corning 7059 substrate (strain point 593 ° C.), after thermal annealing at 640 ° C. for 4 hours,
The substrate taken out after being gradually cooled to 550 ° C at a rate of 0.2 ° C / min was 1900p before and after this thermal annealing and annealing.
Although pm also shrinks, it hardly shrinks thereafter. For example, even if heat treatment is performed at 550 ° C. for 8 hours, only 20 ppm of shrinkage occurs, and after heat treatment at 600 ° C. for 4 hours, only 70 ppm shrinks. It was Although there was no shrinkage that would hinder the use in the range where the heat treatment is performed at a temperature not exceeding the initial thermal annealing temperature (640 ° C. in this case), use at a temperature below the strain point is preferable. That is, the Corning 7059 substrate is heat-treated (crystallization annealing, etc.) at a temperature of 593 ° C. or lower.
Is preferably performed. The thermal annealing temperature is preferably ± 30 ° C. which is the crystallization temperature of the silicon film.

55 for a substrate that has not undergone any processing
Heat treatment at 0 ° C. for 8 hours shrank by 1000 ppm or more, and if there was a patterning step before and after the heat treatment, mask alignment became impossible. Further, the shrinkage of the substrate due to the difference in the cooling rate after the heat treatment at 600 ° C. for 4 hours is as shown in Table 2, and it was possible to suppress the shrinkage to a practical level by quenching at a rate higher than the normal cooling rate.

[0019]

[Table 2]

As described above, if the patterning step is carried out after the step of gradually cooling after the thermal annealing at the temperature above the strain point, there is no problem even in the subsequent heat treatment step (crystallization thermal annealing etc.). It was However, in order to form a semiconductor circuit or the like with a higher yield, it was preferable that the base film be formed after the above-described steps of thermal annealing and slow cooling of the substrate.

On the contrary, it is not preferable to perform the above-described substrate thermal annealing and gradual cooling after forming the base film on the substrate. This is because the substrate undergoes large shrinkage (compared to the untreated state) due to thermal annealing at a high temperature above the strain point and gradual cooling, and the underlayer cannot follow the shrinkage, and the underlayer is partially peeled. This is because Further, when an amorphous silicon film is formed on the base film and crystallized, excessive stress is accumulated in the base film as the substrate shrinks, and the stress caused by the crystallization of the silicon film is reduced. It was confirmed that it became resistant to fluctuations and hindered the progress of crystallization.

As described above, when the base film is in an unstable state, the characteristics of the element formed thereon are also unstable. Therefore, it is not appropriate to perform the thermal annealing and the gradual cooling after forming the base film on the substrate. To broaden this further, do not form any body of semiconductor circuitry prior to the step of thermal annealing the substrate above the strain point and further annealing. Means On the contrary, when the base film is formed in a state where the substrate is sufficiently shrunk, the base film absorbs the strain caused by the crystallization of the silicon film and promotes the crystallization to proceed well.

The glass substrate which has been subjected to the thermal annealing treatment as described above does not shrink even by the subsequent heat treatment at a lower temperature, which is very convenient for forming a semiconductor element / circuit. In particular, the reliability of the element can be improved because the stress due to the contraction of the substrate is not applied to the object constituting the semiconductor element including the base film.

In addition, in the case of adopting the crystallization method in which the catalytic metal element must be selectively added, 50
Since there is a patterning process between the thermal annealing process (crystallization process) of 0 to 600 ° C.
Although the shrinkage of the substrate was a big problem, according to the present invention,
It was possible to perform stable patterning and to form devices with high yield.

In the present invention, it takes time for the thermal annealing and slow cooling of the substrate, which may hinder the productivity. However, in the present invention, since no object relating to the semiconductor element / circuit is formed on the substrate,
Such a thermal annealing process can be collectively performed in a glass factory, and this does not lead to a decrease in productivity in manufacturing a semiconductor circuit.

[0026]

DETAILED DESCRIPTION OF THE INVENTION

[Embodiment] [Embodiment 1] This embodiment is shown in FIGS.
This is an example of forming a circuit in which a P-channel type TFT (referred to as PTFT) and a N-channel type TFT (referred to as NTFT) using a crystalline silicon film formed on the glass substrate shown in FIG. The structure of this embodiment can be used for a switching element of a pixel electrode of an active type liquid crystal display device, a peripheral driver circuit, an image sensor and an integrated circuit.

FIG. 1 shows a sectional view of the manufacturing process of this embodiment. The patterning process and the main heat treatment process (excluding the substrate thermal annealing / slow cooling process) in this embodiment are as follows. Patterning of nickel doping mask (Fig. 1
(See (A)) Crystallization annealing (550 ° C. or 600 ° C., FIG. 1)
(B)) Active layer patterning (see FIG. 1C) Gate electrode patterning Contact hole patterning Source / drain electrode / wiring patterning (FIG. 1)
(See (D)) Of these, since the patterning process exists before and after the thermal annealing process, it is required that the substrate does not shrink in the thermal annealing process.

First, the substrate (Corning 7059) is heated to 600 to 660 ° C. higher than the strain point (593 ° C.), for example, 6
Anneal at 40 ° C. for 1 to 4 hours, for example, 1 hour, and then gradually cool at 0.1 to 0.5 ° C./minute, for example, 0.2 ° C./minute, and increase the temperature to 450 to 590 ° C., for example 550 ° C. It was taken out when it was lowered. It is desirable that this take-out temperature be equal to or lower than the maximum temperature of the subsequent heat treatment step. That is, in this embodiment, the crystallization annealing temperature becomes the maximum temperature thereafter, so that if the crystallization annealing temperature is 600 ° C., it is desirable to take out at a temperature of 600 ° C. or lower. Further, the above thermal annealing treatment was performed in an oxygen stream. This thermal annealing is preferably performed at an angle of ± 30 degrees or less from the horizontal in order to prevent the substrate from being curved.

The substrate 101 thus treated was washed, and a base film 102 of silicon oxide having a thickness of 2000 Å was formed by a sputtering method. Next, a mask 103 is formed of photoresist or an etchable polyimide or photosensitive polyimide (photonice),
It was patterned to form a region 100 in which the underlying film was selectively exposed. (Fig. 1 (A))

Then, a thickness of 5 to 2 is obtained by the sputtering method.
A nickel film of 0Å, for example, 10Å was formed. Since this nickel film is extremely thin, it does not exhibit a film shape in a strict sense. The above film thickness numbers are average values. At this time, since it was preferable to heat the substrate to 150 to 300 ° C., it was preferable that the mask 103 had some heat resistance. After that, the mask 103 was removed. And, by the plasma CVD method, the thickness of 300 to
An intrinsic (I-type) amorphous silicon film 104 having a thickness of 1500 Å, for example, 800 Å was formed.

Then, a nitrogen inert atmosphere (atmospheric pressure),
Crystallization was performed by thermal annealing at 550 ° C. for 8 hours or at 600 ° C. for 4 hours. At this time, in the region of 100 where the nickel film was selectively formed, the crystallization of the crystalline silicon film 104 proceeded in the direction perpendicular to the substrate 101. Then, in areas other than the area 100, as indicated by arrows,
Crystal growth proceeded in the lateral direction (direction parallel to the substrate) from the region 100. The periphery of the region 100 where nickel was directly formed and the region at the tip of crystal growth were the region 105 where the nickel concentration was high. (Fig. 1 (B))

After this step, the silicon film was patterned to form an island-shaped active layer 104 'of the TFT. At this time, a tip of crystal growth is formed at a portion which will be a channel formation region (that is, at the boundary between the crystalline silicon region and the amorphous silicon region,
It is important that there is no (high nickel concentration) present. This makes it possible to prevent carriers moving between the source / drain from being affected by the nickel element in the channel formation region. The crystal growth distance in this step, that is, the distance from the nickel-added region 100 to the tip of the crystal growth is 100 μm at most.
Met.

Conventionally, the nickel introduction mask 103 is used.
1000 pp due to the crystallization anneal step existing between the patterning of the active layer 104 'and the patterning of the active layer 104'.
m, that is, 5 on the top and bottom of a 100 mm square substrate
Due to the substrate shrinkage of 0 μm, such delicate patterning could not be performed. However, in this embodiment, the shrinkage of the substrate is suppressed to 70 ppm or less, that is, 4 μm or less in the vertical direction, which is sufficiently possible.

The size of the active layer 104 'is determined in consideration of the channel length and channel width of the TFT. 50 μm × 20 μm for small ones, 100 μm × for large ones
It was 1000 μm. Many such active layers were formed on the substrate. Then, a silicon oxide film 10 having a thickness of 1200 Å is formed by a plasma CVD method using TEOS (tetra-ethoxy-silane, Si (OC ₂ H ₅ ) ₄ ) and oxygen as raw materials.
6 was formed as a gate insulating film. (Fig. 1 (C))

Subsequently, by the sputtering method,
A film of aluminum (containing 0.01 to 0.2% scandium) having a thickness of 6000 to 8000Å, for example, 6000Å was formed. Then, the aluminum film was patterned to form the gate electrodes 107 and 109. Further, the surface of the aluminum electrode was anodized to form oxide layers 108 and 110 on the surface. This anodic oxidation was performed in an ethylene glycol solution containing 1-5% tartaric acid. The resulting oxide layers 108, 110 have a thickness of 2
It was 000Å. Since the oxides 108 and 110 have a thickness to form the offset gate region in the subsequent ion doping process, the length of the offset gate region can be determined in the anodizing process.

Next, a gate electrode portion (gate electrode 107 and its surrounding oxide layer 108, gate electrode 10) is formed in the active layer region (which constitutes a source / drain and a channel) by an ion doping method (also called a plasma doping method).
Using 9 and its surrounding oxide layer 110) as a mask, impurities imparting P or N conductivity type were added in a self-aligned manner. Phosphine (PH ₃ ) and diborane (B ₂ H ₆ ) were used as the doping gas, and the acceleration voltage was 60 to 90 kV, for example 80 kV in the former case, and 40 to 80 kV, for example 65 kV in the latter case. The dose is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ^-2 , for example, phosphorus is 2 × 1
0 ¹⁵ cm ^-2 and boron was 5 × 10 ¹⁵ . Upon doping, one region was covered with a photoresist to selectively dope each element. As a result, N-type impurity regions 114 and 116 and P-type impurity regions 111 and 113 are formed, and P-channel TFTs are formed.
(PTFT) area and N-channel TFT (NTFT)
It was possible to form the area with.

After that, annealing was performed by irradiation with laser light. As the laser light, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was used, but another laser may be used. The laser light irradiation condition is that the energy density is 200 to 400 mJ / c.
m ² , for example, 250 mJ / cm ^2, and 2 per place
Irradiation was performed for 10 shots, for example, 2 shots. The effect may be increased by heating the substrate to about 200 to 450 ° C. during the irradiation of the laser light. (Fig. 1
(D))

Then, a silicon oxide film 11 having a thickness of 6000Å is formed.
8 was formed by the plasma CVD method as an interlayer insulator. As this interlayer insulator, polyimide or a two-layer film of silicon oxide and polyimide may be used. Further, a contact hole is formed, and a TFT electrode / wiring 1 is formed of a metal material, for example, a multilayer film of titanium nitride and aluminum.
17, 120, 119 were formed. Finally, annealing is performed at 350 ° C. for 30 minutes in a hydrogen atmosphere at 1 atm, and T
A semiconductor circuit in which the FT is configured in a complementary type has been completed. (Fig. 1
(E)) The circuit shown above has a CMOS structure in which PTFT and NTFT are provided in a complementary type. In the above process, two TFTs are formed at the same time and cut at the center to form two independent TFTs. It is also possible to fabricate them at the same time.

In this embodiment, as a method of introducing nickel, nickel is selectively thinned on the underlying film 102 under the amorphous silicon film 104 (it is extremely thin, so it is difficult to observe it as a film). The amorphous silicon film 10 was formed by using the method described above.
A method of selectively forming a nickel film after forming 4 may be used. That is, crystal growth may be performed from the upper surface or the lower surface of the amorphous silicon film. Alternatively, a method of forming an amorphous silicon film in advance and then selectively implanting nickel ions into the amorphous silicon film 104 by using an ion doping method may be adopted. In this case, the nickel element concentration can be finely controlled. Alternatively, a plasma treatment or a CVD method may be used.

[Embodiment 2] This embodiment is an example in which an N-channel TFT is provided in each pixel as a switching element in an active liquid crystal display device. Although one pixel will be described below, a large number of pixels (generally several hundreds of thousands) are formed in the same structure. Also, N
It goes without saying that not only the channel type TFT but also the P channel type TFT may be used. Further, instead of being provided in the pixel portion of the liquid crystal display device, it can be used in the peripheral circuit portion. It can also be used for image sensors and other devices. That is, if it is used as a thin film transistor, its use is not particularly limited.

An outline of the manufacturing process of this embodiment is shown in FIG.
In this example, as the substrate 201, an OA-2 substrate manufactured by Nippon Electric Glass Co., Ltd. (strain point 635 ° C., thickness 1.1 mm, 3 mm
00 × 400 mm) was used. First, the substrate is annealed at 700 ° C. above the strain point for 1 hour and then 0.2 ° C.
It was gradually cooled to 600 ° C. at a speed of about 1 minute. The heat treatment described above significantly reduced the shrinkage of the substrate. For example, only shrinkage of 20 ppm was observed in annealing at 600 ° C. for 4 hours, and shrinkage of 10 ppm was observed in annealing at 550 ° C. for 4 hours.

A base film 202 (silicon oxide) is formed on the substrate 201 which has been subjected to such heat treatment by a plasma CVD method to 2000.
Formed to a thickness of Å. TEO as a CVD source gas
S and oxygen were used. After that, a mask 203 was formed of polyimide in order to selectively introduce nickel. Then, a nickel film was formed by the sputtering method. This nickel film is formed by the sputtering method.
The thickness was 5 to 200Å, for example, 20Å. In this way, the nickel film was selectively formed in the region 204. (Fig. 2 (A))

After this, the LPCVD method or plasma C
An amorphous silicon film 205 was formed in a thickness of 1000Å by the VD method. After dehydrogenation at 450 ° C. for 1 hour, crystallization was performed by heat annealing. This annealing process was performed at 600 ° C. for 4 hours in a nitrogen atmosphere. In this annealing step, the amorphous silicon film 205
Since a nickel film was formed in the lower region 204, crystallization occurred from this portion. During this crystallization,
In the region 204 where the nickel film is formed, the substrate 201
The crystal growth of silicon progressed in a direction perpendicular to the direction. Further, as indicated by the arrow, in the region where nickel was not formed (region other than the region 205), crystal growth proceeded in a direction parallel to the substrate. (Fig. 2 (B))

After this thermal annealing step, the crystallized silicon film was patterned to leave only the island-shaped active layer 205 'of the TFT and remove the others. At this time, it is important that the tip of the grown crystal does not exist in the active layer, especially in the channel formation region. Specifically, of the silicon film 205 in FIG. 2B, at least the crystallization tip and the portion of nickel introduced 204 are removed by etching, and the crystalline silicon film 205 is removed in a direction parallel to the substrate. It is preferable to use the middle portion where the crystal has grown as the active layer. This is to prevent the nickel concentrated in the tip portion from adversely affecting the characteristics of the TFT, in consideration of the fact that nickel is concentrated in the crystal growth tip portion and the introduction portion.

Then, tetra ethoxy silane (TE
(OS) as a raw material by a plasma CVD method in an oxygen atmosphere, and a gate insulating film of silicon oxide (thickness 70 to 120).
nm, typically 120 nm) 206. The substrate temperature was 350 ° C. (Fig. 2 (C))

Next, a well-known film containing polycrystalline silicon as a main component is formed by the CVD method, and patterning is performed.
The gate electrode 207 was formed. Phosphorus was introduced into polycrystalline silicon as an impurity in an amount of 0.1 to 5% in order to improve conductivity.

Thereafter, phosphorus is implanted as an N-type impurity by an ion doping method, and the source region 20 is self-aligned.
8, the channel formation region 209, and the drain region 210 were formed. Then, by performing annealing at 550 ° C. for 4 hours, the crystallinity of the silicon film having deteriorated crystallinity due to ion implantation was improved. Originally, the active layer was easily crystallized because it contained nickel, which has the effect of promoting crystallization. By this thermal annealing, the sheet resistance of the source / drain of this TFT is 300-80.
It became 0 Ω / cm ² . (Fig. 2 (D))

After that, an interlayer insulator 211 is formed of silicon oxide or polyimide, and the pixel electrode 212 is further formed.
Was formed of ITO. Then, a contact hole is formed, and chromium /
The electrodes 213 and 214 were formed of an aluminum multilayer film, and one of the electrodes 214 was connected to the ITO 212. Finally, hydrogenation was performed by annealing in hydrogen at 200 to 400 ° C. for 2 hours. In this way
The TFT is completed. This process is simultaneously performed on many other pixel regions at the same time. In addition, in order to further improve the moisture resistance, a passivation film may be formed on the entire surface with silicon nitride or the like. (Fig. 2 (E))

The TFT manufactured in this example uses a crystalline silicon film which is crystal-grown in the direction of carrier flow as an active layer forming a source region, a channel forming region and a drain region. Since the carriers do not traverse, that is, the carriers move along the crystal grain boundaries of needle-like crystals, a TFT with high carrier mobility can be obtained. TFT manufactured in this example
Is an N-channel type, and its mobility is 90 to 130.
(Cm ² / Vs). The movement to the conventional N-channel TFT using the crystalline silicon film obtained by crystallization by thermal annealing at 600 ° C. for 48 hours is 50 to 70 (c
m ² / Vs), this is a great improvement in characteristics.

In this embodiment, the thermal annealing means is used to activate the doping impurities, but this is a mild reaction as compared with the case of using the laser light as in the first embodiment. In particular, in laser annealing, the discontinuity of crystallinity at the boundary between the shadow portion of the gate electrode portion and the portion to be irradiated with laser has been a cause of deterioration in reliability. Since the / drain region is also heated in the same manner, it was particularly excellent in reliability.

[Embodiment 3] This embodiment will be described with reference to FIG. As the substrate, No. 1733 glass (strain point 640 ° C.) manufactured by Corning Incorporated was used. The glass is annealed at 700 ° C above the strain point for 1 hour and then at 6 ° C at 0.2 ° C / min.
It was gradually cooled to 00 ° C. Then, a base film 302 was formed on the glass substrate 301 by the plasma CVD method, and further, an amorphous silicon film 304 having a thickness of 300 to 800 Å was formed by the plasma CVD method. And thickness 1000
Using the silicon oxide mask 303 of Å, a nickel film was formed in the region indicated by 300 in the same manner as in Example 1. Next, thermal annealing was performed at 550 ° C. for 8 hours to crystallize the silicon film 304. At this time, as indicated by an arrow 305, crystal growth proceeded in a direction parallel to the substrate. (Fig. 3 (A))

Next, the silicon film 304 is patterned to
Island-shaped active layer regions 306 and 307 were formed. At this time, the region indicated by 300 in FIG. 3A is a region into which nickel is directly introduced, and is a region in which nickel exists in a high concentration. Further, as shown in Examples 1 and 2, nickel also exists in high concentration at the end point of crystal growth. It has been found that the nickel concentration in these regions is higher than that of the crystallized regions by almost one digit. Therefore, in this embodiment, the active layer regions 306 and 307, which are regions for forming active elements such as TFTs, are patterned by avoiding the regions having a high nickel concentration, and the high nickel concentration regions are intentionally formed. Removed. The etching of the active layer was performed by the RIE method having anisotropy in the vertical direction. (Fig. 3 (B))

In this embodiment, a complementary TFT circuit is obtained using the active layers 306 and 307. That is, the circuit of this embodiment is different from the structure of Embodiment 1 shown in FIG. 1D in that the PTFT and the NTFT are separated.
That is, in the structure shown in FIG.
The active layers of the FT are continuously connected, and the nickel concentration is high in the intermediate region, but this embodiment has a feature that the nickel concentration is low regardless of which part is taken. Therefore, the stability of operation can be improved.

Then, a silicon oxide or silicon nitride film 308 having a thickness of 200 to 3000 Å was formed by the plasma CVD method. Then, lamp annealing of visible / near infrared light was performed. A halogen lamp was used as the infrared light source. The wavelength is 0.5, which is well absorbed by crystalline silicon.
.About.4 .mu.m, preferably 0.8 to 1.3 .mu.m. As for the intensity of visible / near infrared light, the temperature on the monitor single crystal silicon wafer is 800 to 1300 ° C, typically 900 to 1
It was adjusted to be between 200 ° C. Specifically, the temperature of the thermocouple embedded in the silicon wafer was monitored and fed back to the infrared light source. The infrared light irradiation was performed in an H ₂ atmosphere. 0.1 to 10% of HCl, other hydrogen halides, and compounds of fluorine, chlorine, and bromine may be mixed in the H ₂ atmosphere.

In this embodiment, during irradiation of visible / near infrared light,
Since a protective film of silicon oxide or silicon nitride is formed on the surface of the active layer, it was possible to prevent the surface from being roughened or contaminated during infrared light irradiation. By using such a lamp annealing process together, it was possible to improve the crystallinity, which was not sufficient only by crystallization by thermal annealing. (Fig. 3 (C))

After irradiation with visible / near infrared light, the protective film 308 was removed. After that, the gate insulating film 30 is formed as in the first embodiment.
9, gate electrodes 310 and 311 were formed. Tantalum is used for the gate electrode, and a tantalum oxide film is formed on the surface of the gate electrode by an anodic oxidation method to a thickness of 1000 to 300.
0Å, for example 3000Å was formed. Then, as in Example 1, the impurity element was introduced by the ion doping method to form the source / drain regions.

A lamp annealing method was used to activate the impurities. A halogen lamp was used as the infrared light source. Wavelength is 0.5-4 μm, preferably 0.8-1.3
Irradiation with visible / infrared light of μm was performed for 30 to 180 seconds. In the visible / near infrared rays of the above wavelength, phosphorus or boron is 10 ¹⁹ to 10 ^21.
It is easily absorbed by the amorphous silicon added with cm ^-3.
It is possible to perform effective annealing comparable to thermal annealing at 00 ° C. or higher. On the other hand, since it is difficult to be absorbed by the glass substrate, it does not require heating the glass substrate to a high temperature and requires only a short treatment time, so it can be said that it is the optimal method in the process where shrinkage of the glass substrate is a problem. . Particularly, in the present embodiment, the treatment is performed in advance so that the substrate does not shrink, which is all the more remarkable.

The intensity of visible / near-infrared light was adjusted so that the temperature on the monitor single crystal silicon wafer was 800 to 1300 ° C, typically 900 to 1200 ° C. Specifically, the temperature of the thermocouple embedded in the silicon wafer was monitored and fed back to the infrared light source. The infrared light irradiation was performed in an H ₂ atmosphere. 0.1 to 10% of HCl, other hydrogen halides, and compounds of fluorine, chlorine, and bromine may be mixed in the H ₂ atmosphere. (Fig. 3 (D))

After that, an interlayer insulating film 312 is formed, contact holes are formed in the film, and metal wirings 313 and 3 are formed.
14 and 315 were formed. Further, hydrogenation was performed by annealing at 250 to 400 ° C., for example 350 ° C., in a hydrogen atmosphere of 1 atm. (FIG. 3E) In this way, a complementary TFT circuit was formed. In this embodiment, a protective film is formed on the surface of the active layer during lamp annealing (visible / near infrared light irradiation) to prevent the surface from being roughened or contaminated. Therefore, the characteristics (electric field mobility and threshold voltage) and reliability of the TFT of this example were extremely good.

[Embodiment 4] This embodiment will be described with reference to FIG. As the substrate, NA4 manufactured by NH Techno Glass Co., Ltd.
5 glass (strain point 610 ° C.) was used. First, the substrate was annealed in a nitrous oxide (N ₂ O) atmosphere at 650 ° C. above the strain point for 1 hour and then gradually cooled to 500 ° C. at 0.2 ° C./min. A base film was formed on the glass substrate 501 by the plasma CVD method. First, the silicon nitride film 50 is formed on the substrate.
2 is formed into 1000 Å, and a silicon oxide film 503 is formed into 10
A film of 00Å was formed to form a two-layer base film. The reason for forming the silicon nitride film 702 is to eliminate contamination by mobile ions or the like from the glass substrate.

Then, a thickness of 3 is formed by the plasma CVD method.
00-800Å, for example, 500Å amorphous silicon film 50
4 was deposited. Further, a silicon oxide mask 505 having a thickness of 1000 Å was formed. Then, the nickel acetate film 5 is formed by spin coating using a nickel acetate solution.
06 was formed. Nickel concentration is 50-300pp
m, for example, 100 ppm. At this time, the nickel acetate film 506 is not necessarily a film because it is extremely thin, about several to several tens of liters. (Figure 5 (A))

Next, heating annealing was performed at 550 ° C. for 8 hours to crystallize the amorphous silicon film 504. At this time, as indicated by an arrow, crystal growth proceeded in a direction parallel to the substrate. Next, after removing the mask 505 (which is also a protective film at the time of crystallization annealing), laser crystallization was performed to improve crystallinity. KrF excimer laser light (wavelength 248 nm) is 200 to 300 mJ / c
By irradiating with m ² , a crystalline silicon film 607 was obtained. (Fig. 5 (B))

After that, the crystalline silicon film 507 was patterned to form an island-shaped active layer region 511. On this occasion,
A region denoted by 508 in FIG. 5B is a region into which nickel is directly introduced, and is a region in which nickel is present at a high concentration. Further, as shown in Examples 1 and 2, nickel also exists in high concentration at the crystal growth end points 509 and 510. It has been found that the nickel concentration in these regions is higher than that of the crystallized regions by almost one digit. Therefore, in the present embodiment, the active layer region, which is a region for forming an active element such as a pixel TFT, is patterned while avoiding the regions having a high nickel concentration, and the high concentration region of nickel is intentionally removed. . The etching of the active layer was performed by the RIE method having anisotropy in the vertical direction.

Next, as the gate insulating film 512, a silicon oxide film having a thickness of 200 to 3000 Å, for example, 1000 Å, was formed by the plasma CVD method. Then thickness 1
An aluminum (containing 1 wt% Si or 0.1 to 0.3 wt% Sc) film having a thickness of 000 Å to 3 μm, for example, 5000 Å, was formed by a sputtering method.
Then, a photoresist was formed by spin coating. If an aluminum oxide film having a thickness of 100 to 1000 Å is formed on the surface by anodic oxidation before the photoresist is formed, the adhesion of the photoresist is improved. Then, the photoresist and the aluminum film were patterned to form a gate electrode 513. The photoresist is not peeled off after the etching, and the gate electrode 51 is not removed.
3 was left as a mask film 514.

Further, a porous anodic oxide 515 having a thickness of 3000 to 6000 Å, for example, 5000 Å, was formed by carrying out a porous anodic oxidation in the electrolytic solution by applying an electric current. Porous anodic oxidation may be performed using an acidic aqueous solution of 3 to 20% citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid, or the like, and a constant current of 5 to 30 V may be applied to the gate electrode. In this example, the voltage was set to 10 V and anodized in an oxalic acid solution (30 ° C.) for 20 to 40 minutes. The thickness of the porous anodic oxide was controlled by the time of anodic oxidation. (Fig. 5 (C))

After that, the mask 514 was peeled off and barrier anodic oxidation was performed. At this time, the substrate should have a pH of approximately 7, 1
It was immersed in an ethylene glycol solution of tartaric acid of ˜3%, platinum was used as a cathode, and an aluminum electrode was used as an anode, and the voltage was gradually increased to proceed anodization. In this way, a dense barrier type anodic oxide 616 having a high breakdown voltage was formed.

Then, the gate insulating film 512 was etched by the dry etching method. At this time, the anodic oxides 515 and 516 are not etched and the gate insulating film 5 is not etched.
When only 12 was etched and the island-shaped active layer 511 appeared, the etching was finished. As a result, the gate insulating film 512 ′ under the porous anodic oxide 515 remained without being etched. (Figure 5 (D))

Then, the porous anodic oxide 515 was etched and removed. Then, by ion doping, boron is injected as an impurity in a self-alignment manner into the island-shaped active layer 511 using the gate electrode portion (gate electrode, barrier type anodic oxide, silicon oxide film) as a mask to form a P type impurity region. 517 was formed. Here, diborane (B ₂ H ₆ ) was used as the doping gas. At this time, the dose amount of boron is 1 to 4 × 10 ¹⁵ atoms / cm ² , and the acceleration voltage is 1
It was set to 0 kV. Here, since the accelerating voltage is low, boron was not introduced into the lower portion of the gate insulating film, and an offset region was formed. (Fig. 5 (E))

Further, this was subjected to thermal annealing at 350 to 550 ° C., for example, 500 ° C. for 4 hours to activate the doped impurities. The deformation of the substrate at this time was extremely small. Further, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated for further activation. The energy density of the laser is 200 to 400 mJ / cm ² , preferably 25.
0 to 300 mJ / cm ² was suitable. At this time, the PI junction existing under the gate insulating film 512 ′ was sufficiently activated by laser irradiation. Next, a silicon oxide film was formed as the interlayer insulating film 519 to a thickness of 3000 Å by the plasma CVD method.

Then, the interlayer insulating film 519 was etched to form a contact hole in the source region.
After that, an aluminum film was formed by a sputtering method and patterned to form a source electrode 519. (FIG. 5 (F)) Finally, as the passivation film 520, the thickness of 1000-
A 6000 Å, for example 3000 Å, silicon nitride film was formed by plasma CVD, and this and the interlayer insulating film 518 were etched to form a contact hole in the drain. After that, an indium tin oxide film (ITO film) was formed, and this was etched to form the pixel electrode 521. (FIG. 5G) As described above, the pixel TFT having the P-channel type offset region was formed.

[Embodiment 5] This embodiment will be described with reference to FIG. Corning No. 1733 glass was used as the substrate. First, the substrate is annealed in a nitrogen (N ₂ ) atmosphere at 700 ° C. above the strain point for 1 hour, and then 0.2 ° C. /
It was gradually cooled to 600 ° C. in minutes. Then, the glass substrate 601
A base film was formed on top. Here, the aluminum nitride film 602 is formed on the substrate by a sputtering method at 1000 Å
A silicon oxide film 6 is formed by the plasma CVD method.
03 was deposited to 1000 Å to form a two-layer base film. The reason for forming the aluminum nitride film 702 is to eliminate contamination by mobile ions or the like from the glass substrate.

Then, a thickness of 3 is obtained by the plasma CVD method.
00-800Å, for example, 500Å amorphous silicon film 60
4 was deposited. Further, a mask 605 of silicon oxide having a thickness of 1000Å was formed. Then, the nickel acetate film 6 is formed by a spin coating method using a nickel acetate solution.
06 was formed. (FIG. 6 (A)) Next, heating annealing was performed at 550 ° C. for 8 hours to crystallize the amorphous silicon film 604. At this time, as indicated by an arrow, crystal growth proceeded in a direction parallel to the substrate.

Next, after removing the mask, laser crystallization was performed to improve the crystallinity. The crystalline silicon film 607 was obtained by irradiating with KrF excimer laser light at 200 to 300 mJ / cm ² . (Fig. 6
(B) After that, the crystalline silicon film 607 was patterned to form an island-shaped active layer region 611. At this time, as in Example 4, the active layer was formed while avoiding the region where the nickel concentration was high.

Next, as the gate insulating film 612, a silicon oxide film having a thickness of 200 to 3000 Å, for example, 1200 Å was formed by the plasma CVD method. Then thickness 1
An aluminum film of 000Å to 3 μm, for example, 6000Å was formed by the sputtering method. Then, a gate electrode 613, a photoresist mask 614, and a porous anodic oxide 615 were formed in the same manner as in Example 4. (FIG. 6C) After that, the mask 614 was peeled off and barrier anodic oxidation was performed to form a barrier type anodic oxide 616. And
As a result of etching the gate insulating film by the dry etching method, the gate insulating film 612 ′ under the porous anodic oxide 616 remained. (Figure 6 (D))

After that, the porous anodic oxide 615 is etched and removed, and the ion doping method is used to remove the porous anodic oxide 615.
The gate electrode portion (gate electrode,
Using the barrier type anodic oxide and the silicon oxide film) as a mask, boron was implanted as an impurity in a self-aligned manner to form a P type impurity region 617. (Fig. 6 (E))

Furthermore, a KrF excimer laser (wavelength 2
Irradiation with 48 nm and a pulse width of 20 nsec) was performed to activate the impurity region 617. Further, in order to improve the junction between the source / channel and the drain / channel, thermal annealing was performed at 350 to 550 ° C., for example, 500 ° C. for 4 hours. Next, a silicon oxide film is formed as the interlayer insulating film 618 by the plasma CVD method at 3000 Å
It was formed into a film.

Then, the interlayer insulating film 618 was etched to form a contact hole in the source region.
After that, an aluminum film was formed by a sputtering method and patterned to form a source electrode 619. (FIG. 6 (F)) Finally, a passivation film 620 having a thickness of 2000 to
A 6000 Å, for example, 3000 Å silicon nitride film was formed by the plasma CVD method, and this and the interlayer insulating film 618 were etched to form a contact hole in the drain. After that, an indium tin oxide film (ITO film) was formed, and this was etched to form a pixel electrode 621. (FIG. 6G) As described above, the pixel TFT having the P-channel type offset region was formed.

[Sixth Embodiment] This embodiment will be described with reference to FIG. Corning 7059 glass was used as the substrate. First, after annealing the substrate in an ammonia (NH ₃ ) atmosphere at 640 ° C. above the strain point for 1 hour,
It was gradually cooled to 400 ° C at 0.2 ° C / min. After that, a base film was formed on the glass substrate 701. Here, a silicon oxide film 702 is formed on the substrate by a plasma CVD method.
Then, a silicon nitride film 703 having a thickness of 1000 Å was formed by a plasma CVD method to form a base film having two layers.

Then, a thickness of 3 is formed by the plasma CVD method.
00-800Å, for example, 500Å amorphous silicon film 70
4 was deposited. Further, a silicon oxide mask 705 having a thickness of 1000 Å was formed. Then, the nickel acetate film 7 is formed by a spin coating method using a nickel acetate solution.
06 was formed. (FIG. 7A) Next, heat anneal was performed at 550 ° C. for 8 hours to crystallize the amorphous silicon film 704. At this time, as indicated by an arrow, crystal growth proceeded in a direction parallel to the substrate.

Next, after removing the mask, laser crystallization was performed to improve the crystallinity. A crystalline silicon film 707 was obtained by irradiating with KrF excimer laser light at 200 to 300 mJ / cm ² . (Fig. 7
(B) After that, the crystalline silicon film 707 was patterned to form an island-shaped active layer region 711. At this time, as in Example 4, the active layer was formed while avoiding the region where the nickel concentration was high. At this time, etching was performed by the RIE method, but since the etching rate of the silicon oxynitride film 703 was much smaller than that of the silicon film, overetching of the base film was small.

Next, as the gate insulating film 712, a silicon oxide film having a thickness of 200 to 3000 Å, for example, 1200 Å, was formed by the plasma CVD method. Then thickness 1
An aluminum film of 000Å to 3 μm, for example, 6000Å was formed by the sputtering method. Then, a gate electrode 713, a photoresist mask 714, and a porous anodic oxide 715 were formed in the same manner as in Example 4. (Fig. 7 (C))

After that, the mask 714 was peeled off and barrier anodic oxidation was performed to form a barrier type anodic oxide 716. Then, as a result of etching the gate insulating film by the dry etching method, the porous anodic oxide 71
The gate insulating film 712 'under 6 remained. (Fig. 7
(D))

After that, the porous anodic oxide 715 is etched and removed, and the ion doping method is used to remove the porous anodic oxide 715.
The gate electrode portion (gate electrode,
Using the barrier type anodic oxide and the silicon oxide film as a mask, boron was implanted as an impurity in a self-aligned manner to form a P type impurity region 717. (Fig. 7 (E))

Furthermore, 350 to 550 ° C., for example, 50
Thermal annealing was performed at 0 ° C. for 4 hours to activate the doped impurities. Then, in order to perform activation more preferably, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated. Then, in order to improve the characteristics of the source / channel junction and the drain / channel junction, 350 to 550 ° C.,
For example, annealing was performed at 480 ° C. for 1 hour. Next, a silicon oxide film was formed as the interlayer insulating film 718 to a thickness of 3000 Å by the plasma CVD method.

Then, the interlayer insulating film 718 was etched to form a contact hole in the source region.
After that, an aluminum film was formed by a sputtering method and patterned to form a source electrode 719. (FIG. 7 (F)) Finally, a passivation film 720 having a thickness of 2000 to
A 6000 Å, for example, 3000 Å silicon nitride film was formed by a plasma CVD method, and this and the interlayer insulating film 718 were etched to form a contact hole in the drain. After that, an indium tin oxide film (ITO film) was formed, and this was etched to form a pixel electrode 721. (FIG. 7G) As described above, the pixel TFT having the P-channel type offset region was formed.

[0086]

As described above, by thermally annealing the substrate at a temperature equal to or higher than the strain point and gradually cooling, the shrinkage of the substrate due to the subsequent heat treatment becomes very small. Generally, the patterning step (mask alignment step) of introducing nickel as shown in the embodiment does not require so much accuracy as compared with other patterning steps. On the other hand, patterning for forming contact holes and forming gate electrodes requires accuracy of several μm or less. For this reason, conventionally, the activation of doping impurities has been centered on laser annealing that does not involve a substantially thermal process.

However, since the present invention makes it possible to suppress the shrinkage of the substrate to a considerable temperature, the thermal annealing as shown in Example 2 and the lamp annealing as shown in Example 3 are more suitable for mass production. It became possible to use the means. As described above, the present invention is extremely effective in forming a semiconductor device on an insulating substrate.

[Brief description of drawings]

1A to 1C show steps of manufacturing a TFT of Example 1. FIG.

FIG. 2 shows a process of manufacturing a TFT of Example 2.

FIG. 3 shows a manufacturing process of a TFT of Example 3.

FIG. 4 shows an example of deviation of patterning due to conventional substrate contraction.

FIG. 5 shows a manufacturing process of the TFT of Example 4.

FIG. 6 shows a process of manufacturing a TFT of Example 5.

FIG. 7 shows a manufacturing process of a TFT of Example 6.

FIG. 8 shows a structural example of a thermal annealing furnace used in the present invention.

[Explanation of symbols]

100 Nickel introduction part 101 glass substrate 102 Base film (silicon oxide film) 103 mask 104 Silicon film 104 'island-shaped silicon film (active layer) 105 Area with high nickel concentration 106 Gate insulating film (silicon oxide film) 107 Gate electrode (aluminum) 108 Anodized layer (aluminum oxide) 109 Gate electrode 110 Anodized layer 111 Source (drain) region 112 channel formation region 113 drain region 114 source (drain) region 115 channel formation region 116 drain region 117 electrodes 118 Interlayer insulation 119 electrodes 120 electrodes

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hisashi Otani Hisashi Otani 398 Hase, Atsugi City, Kanagawa Prefecture, Semiconductor Energy Laboratory Co., Ltd. ) Inventor Yasuhiko Takemura 398 Hase, Atsugi City, Kanagawa Prefecture Semiconductor Energy Laboratory Co., Ltd. (56) Reference JP-A-7-99324 (JP, A) JP-A-2-102150 (JP, A) JP-A-63- 315141 (JP, A) JP-A-4-85969 (JP, A) JP-A-6-296023 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21 / 336 H01L 21/324 H01L 27/12 C30B 25/02 G02F 1/1333 G02F 1/1368

Claims (8)

(57) [Claims] 1. A glass substrate horizontally held by a substrate holding means.
The thermal annealing at a first temperature above the strain point of the glass substrate
And slow cooling from the first temperature to a second temperature equal to or lower than the strain point at a rate of 2 ° C./min or less, and then a silicon oxide film or a silicon nitride film is formed on the glass substrate. , Al nitride
Forming a minium film or a multilayer film in which two or more layers are stacked
The silicon oxide film, silicon nitride film, aluminum nitride film,
Forms an amorphous silicon film on a multilayer film in which two or more layers are stacked.
And then at a third temperature that does not exceed the first temperature,
Active type characterized by processing glass substrate
A method for manufacturing a liquid crystal display device . 2. A glass substrate horizontally held by a substrate holding means.
The thermal annealing at a first temperature above the strain point of the glass substrate
And slow cooling from the first temperature to a second temperature equal to or lower than the strain point at a rate of 2 ° C./minute or less, and then using a plasma CVD method on the glass substrate by silicic oxide.
Element film, silicon nitride film, aluminum nitride film, or these
Forming a multilayer film of two or more layers, the silicon oxide film, the silicon nitride film, the aluminum nitride film, or
Forms an amorphous silicon film on a multilayer film in which two or more layers are stacked.
And then at a third temperature that does not exceed the first temperature,
Active type characterized by processing glass substrate
A method for manufacturing a liquid crystal display device . 3. A substrate holding means horizontally held,
After thermal annealing at a first temperature above the strain point, the first
From a glass substrate obtained by gradually cooling from a temperature of 2 to a second temperature below the strain point at a rate of 2 ° C./min or less.
And a silicon oxide film, a silicon nitride film, and an aluminum nitride film on the glass substrate.
Forming a minium film or a multilayer film in which two or more layers are stacked
The silicon oxide film, silicon nitride film, aluminum nitride film,
Forms an amorphous silicon film on a multilayer film in which two or more layers are stacked.
After being formed , the glass is heated at a third temperature not exceeding the first temperature.
Active type liquid crystal display characterized by processing substrate
A method for manufacturing a device. 4. A substrate holding means horizontally held,
After thermal annealing at a first temperature above the strain point, the first
Second temperature below the strain point at a rate of 2 ° C / min or less from the temperature of
The glass substrate obtained by gradually cooling to the temperature of
And a silicon oxide film on the glass substrate by a plasma CVD method.
Element film, silicon nitride film, aluminum nitride film, or these
Forming a multilayer film of two or more layers, the silicon oxide film, the silicon nitride film, the aluminum nitride film, or
Forms an amorphous silicon film on a multilayer film in which two or more layers are stacked.
After being formed , the glass is heated at a third temperature not exceeding the first temperature.
Active liquid crystal display characterized by processing substrate
Method for manufacturing device. 5. The thermal annealing at the first temperature and the temperature up to the second temperature according to any one of claims 1 to 4.
The gradual cooling consists of placing multiple glass substrates at intervals.
Active type liquid crystal display device characterized by being performed by
Of manufacturing. 6. A thermal anneal at the first temperature and up to the second temperature according to any one of claims 1 to 4.
Gradually cooling, the plurality of glass substrates are arranged at intervals,
Characterized by being performed in an oxidizing atmosphere or a nitriding atmosphere
The method for manufacturing a active liquid crystal display device according to. 7. The gradual cooling to the second temperature according to claim 1, wherein the cooling rate is 0.5 ° C./min or less.
Active liquid crystal display device characterized by being performed in
Of manufacturing. 8. The gradual cooling to the second temperature according to claim 1, wherein the slow cooling is performed at a rate of 0.3 ° C./min or less.
Active liquid crystal display device characterized by being performed in
Of manufacturing.