JP2001342031A - Glass substrate and method of manufacturing it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a glass substrate for an integrated circuit including a thin film transistor(TFT) whose contraction by heat treatment is suppressed. SOLUTION: The manufacturing process of the glass substrate comprises a patterning process on the substrate and a heat treatment process. The substrate (CORNING 7059) is annealed at 640 deg.C which is higher than a strain point (593 deg.C) for 1 hr in a gaseous oxygen stream, cooled slowly at a rate of 0.1-0.5 deg.C/min and taken out at 550 deg.C. The heat-treated substrate 101 is washed and patterned.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device formed on an insulating substrate such as glass or various substrates, for example, a thin film transistor (TFT) or a thin film diode (T).
The present invention relates to a method for manufacturing a thin film integrated circuit (FD) or a thin film integrated circuit using the same, particularly a thin film integrated circuit for an active liquid crystal display device (liquid crystal display).

[0002]

2. Description of the Related Art In recent years, semiconductor devices having TFTs on an insulating substrate such as glass, for example, active type liquid crystal display devices and image sensors using TFTs for driving pixels have been developed. As a glass substrate, Corning 7 is used because of problems such as precipitation of impurities from the glass substrate and price.
059 glass is commonly used. The transition point temperature of this 7059 glass is 628 ° C., and the strain point is 593 ° C. Other practical glass materials having a strain point of 550 to 650 ° C. shown in Table 1 are known.

[0003]

[Table 1]

[0004] Thin film silicon semiconductors are generally used for TFTs used in these devices. Thin-film silicon semiconductors are roughly classified into two types: those made of an amorphous silicon semiconductor (a-Si) and those made of a crystalline silicon semiconductor. Amorphous silicon semiconductors are most commonly used because they have a low manufacturing temperature, can be manufactured relatively easily by a gas phase method, and have high mass productivity. Since it is inferior to a silicon semiconductor having
In order to obtain higher-speed characteristics in the future, it has been strongly required to establish a method for manufacturing a TFT made of a crystalline silicon semiconductor. Note that, as a silicon semiconductor having crystallinity, polycrystalline silicon, microcrystalline silicon, amorphous silicon containing a crystal component, semi-amorphous silicon having an intermediate state between crystalline and amorphous, and the like are known. .

As a method of obtaining a silicon semiconductor in the form of a thin film having crystallinity, an amorphous semiconductor film is formed, and thermal energy is applied (thermal annealing) for a long time to obtain a crystalline silicon semiconductor. There is a known method. However, it is necessary to set the heating temperature to a high temperature of 600 ° C. or higher, which causes a problem that the substrate shrinks irreversibly. In particular, it has been impossible to perform such high-temperature processing after the patterning step. In addition, since the heating time required for crystallization is several tens of hours or more, it is necessary to shorten the heating time.

[0006] Regarding such a problem, recently, by adding a certain metal element having an effect as a catalyst for promoting crystallization, the crystallization temperature is lowered, and
It has been found that the crystallization time can be reduced. Metal elements (catalytic metal elements) that promote crystallization used for such purposes include Fe, Co, Ni, Ru, Rh, and P.
d, Os, Ir, Pt, Sc, Ti, V, Cr, Mn,
The effects of Cu, Zn, Au, and Ag have been confirmed.

These elements are formed over the entire surface of the silicon film.
When introduced evenly, crystal growth occurs perpendicular to the film, that is, in the direction of the film thickness. On the other hand, when crystal is introduced into a specific portion of the silicon film and crystallization is performed, the introduced portion is used as a starting point. Has the property of expanding the crystallization region (lateral growth property), and the silicon film crystallized in this manner has a higher field-effect mobility than that in which the catalytic metal element is uniformly introduced. .

However, in order to selectively introduce the catalytic metal element in this manner, patterning must be performed before the thermal annealing step of crystallization, and the introduction of the catalytic metal element due to the contraction of the substrate described above. In some cases may significantly deviate from the patterns of other elements and circuits. FIG. 4 shows an example in which a TFT is manufactured using such a means. Area 4 written by a dotted line in FIG.
Numerals 02 and 403 indicate ones where the active layer (silicon film) and the gate electrode should be originally patterned. A rectangular area 401 shown by a solid line is a pattern into which a catalytic metal element is introduced.

In this step, when thermal annealing is performed after the introduction of the catalytic metal element, the region 404 indicated by the ellipse in FIG. 4B is crystallized. That is, the area 404
Is a lateral crystal region. The size of the ellipse depends on the concentration of the catalytic metal element and the time and temperature of the thermal annealing. FIG.
As shown in (B), when the gate electrode and the active layer were formed at the positions where they should be, there was no problem because the channel formation region of the TFT was formed in the lateral crystal region.
However, since the substrate is actually shrunk by the thermal annealing step, the gate electrode and the active layer are each 40
5, 406, the region 404 does not overlap with the channel forming region. That is, in the channel formation region, the region indicated by the shaded portion 407 remains amorphous. As a matter of course, the characteristics of the TFT significantly deteriorate.

As described above, it is extremely difficult to perform patterning before processing at a high temperature due to shrinkage of the substrate. The high temperature in this case varies depending on the type of the substrate, but is relatively higher than 500 ° C. in the case of glass No. 7059 manufactured by Corning, which is often used.

[0011]

SUMMARY OF THE INVENTION The present invention provides means for solving the above problems. More specifically, the present invention discloses a means for suppressing the shrinkage of the substrate and a means for obtaining a semiconductor circuit / element having a higher yield and good characteristics.

[0012]

According to the present invention, a glass substrate is thermally annealed at a temperature not lower than its strain point (strain temperature), preferably not lower than the glass transition point, and then not higher than 2.degree. 5 ° C./min or less, more preferably 0.
By gradually cooling the glass substrate to a temperature below the strain point at a rate of 3 ° C./min or less, the glass substrate itself is prevented from shrinking in the subsequent heat treatment. The cooling rate varies depending on the type of the substrate. In general, the lower the cooling rate, the better the characteristics are obtained. However, if the cooling rate is reduced, the processing time becomes longer and the mass productivity is reduced. Therefore, in selecting the temperature lowering rate, the processing time and the required characteristics must be considered. This heat treatment may be performed in an oxidizing or nitriding atmosphere.

Further, after forming an appropriate base film on the substrate thus treated, an amorphous silicon film is formed and crystallized. In addition, as a base film, a silicon oxide film,
It is preferable to use a silicon nitride film, aluminum nitride, or a multilayer film in which two or more layers are stacked. The above-described thermal annealing may be performed by the following method.
FIG. 8 shows an example of a heating furnace used in the present invention, in which a reaction tube 11 made of quartz, a substrate holding means (substrate holder) 12, and a substrate 13 arranged horizontally are shown. Although not shown in the figure, the apparatus is provided with a heater for heating the reaction tube 11 from outside. Also provided are means for supplying a predetermined gas into the reaction tube and means for moving the substrate holding means from the reaction tube to the outside.

FIG. 8 shows a state where the glass substrate 13 is held horizontally by the substrate holding portion 12. Here, when the glass substrate is held horizontally, the substrate is bent, which is effective in preventing the planarity from being impaired. Such a configuration is useful when a step of applying a temperature higher than the strain point to the glass substrate is required. In the subsequent thermal annealing step such as crystallization and activation of the silicon film, the above configuration may be adopted.

Further, a film formed after the above pre-heat treatment,
In the heat treatment necessary for crystal growth, oxidation, activation, etc., it is important to rapidly cool at a rate of 10 ° C./min to 300 ° C./min after heating. Especially ± 1 around the strain point of glass material
At 00 ° C., the rapid expansion and contraction of the glass material could suppress the expansion and contraction of the glass material. For example, Corning 7
In a process requiring a processing temperature of 493 to 693 ° C. for 059 glass, at least quenching up to 493 ° C. is effective in suppressing further shrinkage (elongation in some cases) to 30 ppm or less.

[0016]

The glass substrate shrinks by heating, and particularly when cooled slowly after the heating, shrinks extremely greatly and at the same time relieves the local stress in the glass substrate. As a result, the larger the shrinkage, the smaller the shrinkage of the substrate in the subsequent heating step. In addition, the higher the heating temperature, the greater the effect. Therefore, even if the heat treatment is performed again thereafter, since the stress of the glass substrate is relaxed, there is little room for further shrinking or warping. Further, it has been found that in the heat treatment step after crystallization annealing or the like, when the glass substrate is rapidly cooled from the heating temperature, the glass substrate subjected to the thermal annealing treatment of the present invention hardly shrinks.

For example, for a Corning 7059 substrate (strain point 593 ° C.), after thermal annealing at 640 ° C. for 4 hours,
The substrate taken out after being gradually cooled to 550 ° C. at a rate of 0.2 ° C./min, was subjected to 1900p before and after this thermal annealing and slow cooling.
pm also shrinks, but hardly shrinks thereafter. For example, heat treatment at 550 ° C. for 8 hours causes only 20 ppm shrinkage, and heat treatment at 600 ° C. for 4 hours shrinks only 70 ppm. Was. There was no shrinkage that would hinder use in the temperature range that does not exceed the initial thermal annealing temperature (640 ° C. in this case) and then heat treatment is performed, but it is preferable to use a temperature below the strain point. That is, heat treatment (crystallization annealing, etc.) at a temperature of 593 ° C. or lower for the Corning 7059 substrate.
Is preferably performed. Further, the temperature of the thermal annealing is preferably performed at a temperature of ± 30 ° C. of the crystallization temperature of the silicon film.

For a substrate on which no processing was performed, 55
It shrank by 1000 ppm or more in a heat treatment at 0 ° C. for 8 hours, and if there was a patterning step before and after the heat treatment, mask alignment became impossible. Further, the shrinkage of the substrate due to the difference in the cooling rate after the heat treatment at 600 ° C. for 4 hours is as shown in Table 2, and it was possible to suppress the shrinkage to a practical degree by rapidly cooling at a speed higher than the normal cooling.

[0019]

[Table 2]

As described above, if a patterning step is performed after performing a annealing step after annealing at a temperature equal to or higher than the strain point, there is no problem in the subsequent heat treatment step (such as crystallization thermal annealing). Was. However, in order to form a semiconductor circuit or the like with a higher yield, it is preferable that the base film is formed after the above-described steps of thermal annealing and slow cooling of the substrate.

Conversely, it is not preferable to perform the above-described substrate thermal annealing and slow cooling after forming the base film on the substrate. This is because the substrate shrinks greatly (compared to the untreated state) due to thermal annealing and slow cooling at a high temperature exceeding the strain point, the base film cannot follow the shrinkage, and the base film partially peels off To do that. In addition, when an amorphous silicon film is formed on an underlayer and crystallized, an excessive stress is accumulated in the underlayer as the substrate shrinks, and the stress caused by the crystallization of the silicon film is reduced. It was found that it became resistant to fluctuation and hindered the progress of crystallization.

As described above, when the underlying film is in an unstable state, the characteristics of the element formed thereon become unstable. Therefore, it is not appropriate to perform thermal annealing and slow cooling after forming a base film on the substrate. To extend this more broadly, any object that constitutes a semiconductor circuit must not be formed before the substrate is thermally annealed at a temperature above the strain point and then slowly cooled. Means Conversely, when the base film is formed in a state where the substrate is sufficiently shrunk, the base film absorbs the strain accompanying the crystallization of the silicon film, and promotes the crystallization to progress satisfactorily.

The glass substrate that has been subjected to the above-described thermal annealing treatment does not shrink even after the subsequent heat treatment at a lower temperature, which is very convenient for forming a semiconductor element / circuit. In particular, since an object constituting a semiconductor element such as a base film is not subjected to stress due to shrinkage of the substrate or the like, the reliability of the element can be improved.

In addition, when employing a crystallization method in which a catalytic metal element must be selectively added, 50
Since there is a patterning step between the thermal annealing step (crystallization step) of 0 to 600 ° C.,
Although shrinkage of the substrate was a major problem, according to the present invention,
The patterning could be performed stably, and the device could be formed with high yield.

In the present invention, it takes a long time for thermal annealing and slow cooling of the substrate, which may hinder productivity. However, in the present invention, since no object related to the semiconductor element / circuit is formed on the substrate,
Such a thermal annealing step can be performed at once in a glass factory, and this does not lead to a decrease in productivity in manufacturing a semiconductor circuit.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION

[Embodiment 1] This embodiment is shown in FIGS. 1 (A) to 1 (E).
In this example, a circuit is formed in which a P-channel TFT (referred to as PTFT) using a crystalline silicon film formed on a glass substrate and an N-channel TFT (referred to as NTFT) are combined in a complementary manner. The configuration of this embodiment can be used for a switching element of a pixel electrode and a peripheral driver circuit of an active type liquid crystal display device, as well as an image sensor and an integrated circuit.

FIG. 1 is a sectional view showing a manufacturing process of this embodiment. The patterning step and the main heat treatment step (excluding the thermal annealing / gradual cooling step of the substrate) in this embodiment are as follows. Patterning of nickel doping mask (Fig. 1
(See (A)) Crystallization annealing (550 ° C. or 600 ° C., FIG. 1)
(See (B)) Active layer patterning (See FIG. 1 (C)) Gate electrode patterning Contact hole patterning Source / drain electrode / wiring patterning (FIG. 1
(Refer to (D).) Among them, since a patterning step exists before and after the thermal annealing step, it is required that the substrate does not shrink in the thermal annealing step.

First, the substrate (Corning 7059) is heated to a temperature of 600 to 660 ° C. higher than the strain point (593 ° C.), for example, 6 ° C.
Anneal at 40 ° C. for 1 to 4 hours, for example, 1 hour, and then gradually cool at 0.1 to 0.5 ° C./minute, for example, 0.2 ° C./minute, until the temperature reaches 450 to 590 ° C., for example, 550 ° C. Removed when lowered. It is desirable that this take-out temperature be equal to or lower than the maximum temperature of the subsequent heat treatment step. That is, in this embodiment, since the crystallization annealing temperature is the highest temperature thereafter, if the crystallization annealing temperature is 600 ° C., it is desirable to take out at a temperature of 600 ° C. or less. In addition, the above-described thermal annealing was performed in an oxygen stream. This thermal annealing is desirably performed at an angle of ± 30 degrees or less from the horizontal in order to prevent the substrate from bending.

The substrate 101 thus treated was washed, and a 2000-nm-thick silicon oxide base film 102 was formed by a sputtering method. Next, a mask 103 is formed using a photoresist, an etchable polyimide, or a photosensitive polyimide (photonise).
It was patterned to form a region 100 where the underlying film was selectively exposed. (Fig. 1 (A))

Then, by sputtering, a thickness of 5 to 2
A nickel film of 0 °, for example, 10 ° was formed. Since this nickel film is extremely thin, it does not strictly exhibit a shape as a film. The above figures of the film thickness are average. At this time, it is preferable that the substrate be heated to 150 to 300 ° C., so that the mask 103 preferably has a certain level of heat resistance. After that, the mask 103 was removed. Then, a thickness of 300 to
An intrinsic (I-type) amorphous silicon film 104 of 1500 °, for example, 800 ° was formed.

Then, a nitrogen inert atmosphere (atmospheric pressure),
It was crystallized by thermal annealing at 550 ° C. for 8 hours or at 600 ° C. for 4 hours. At this time, in the region 100 where the nickel film was selectively formed, the crystallization of the crystalline silicon film 104 progressed in the direction perpendicular to the substrate 101. Then, in an area other than the area 100, as indicated by an arrow,
Crystal growth proceeded from the region 100 in the lateral direction (the direction parallel to the substrate). The area around the area 100 where nickel was directly formed and the area at the tip of the crystal growth were areas 105 where the nickel concentration was high. (FIG. 1 (B))

After this step, the silicon film was patterned to form an island-shaped active layer 104 'of the TFT. At this time, a tip portion of crystal growth (that is, a boundary between the crystalline silicon region and the amorphous silicon region,
(High nickel concentration) is important. This makes it possible to prevent carriers moving between the source and the drain from being affected by the nickel element in the channel formation region. The crystal growth distance in this step, that is, the distance from the nickel added region 100 to the tip of the crystal growth is at most 100 μm.
Met.

Conventionally, the nickel introduction mask 103
1000 pp due to the crystallization annealing step between the patterning of
m, that is, 5 on the top and bottom for a 100 mm square substrate
Such fine patterning could not be performed because the substrate shrank by as much as 0 μm. However, in the present embodiment, the shrinkage of the substrate is suppressed to 70 ppm or less, that is, 4 μm or less in the upper and lower directions, which is sufficiently possible.

The size of the active layer 104 'is determined in consideration of the channel length and channel width of the TFT. 50 μm × 20 μm for small objects, 100 μm ×
It was 1000 μm. Many such active layers were formed on the substrate. The silicon oxide film 10 having a thickness of 1200 ° is formed by plasma CVD using TEOS (tetraethoxysilane, Si (OC ₂ H ₅ ) ₄ ) and oxygen as raw materials.
6 was formed into a gate insulating film. (Fig. 1 (C))

Subsequently, by a sputtering method,
Aluminum (including 0.01 to 0.2% scandium) having a thickness of 6000 to 8000 °, for example, 6000 ° was deposited. Then, the aluminum film was patterned to form gate electrodes 107 and 109. Further, the surface of the aluminum electrode was anodized to form oxide layers 108 and 110 on the surface. This anodization was performed in an ethylene glycol solution containing tartaric acid at 1 to 5%. The thickness of the obtained oxide layers 108 and 110 is 2
000Å. Since the oxides 108 and 110 have a thickness for forming an offset gate region in a later ion doping process, the length of the offset gate region can be determined in the anodic oxidation process.

Next, by an ion doping method (also referred to as a plasma doping method), a gate electrode portion (a gate electrode 107, an oxide layer 108 around the gate electrode 107, and a gate electrode 10) is formed in an active layer region (which constitutes a source / drain and a channel).
9 and the surrounding oxide layer 110) were used as a mask, and an impurity imparting P or N conductivity was added in a self-aligned manner. Phosphine (PH ₃ ) and diborane (B ₂ H ₆ ) were used as the doping gas. In the former case, the acceleration voltage was 60 to 90 kV, for example, 80 kV, and in the latter case, the acceleration voltage was 40 to 80 kV, for example, 65 kV. The dose is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, 2 × 1
0 ¹⁵ cm ^-2 and boron was set to 5 × 10 ¹⁵ . At the time of doping, each element was selectively doped by covering one region with a photoresist. As a result, N-type impurity regions 114 and 116 and P-type impurity regions 111 and 113 are formed.
(PTFT) region and N-channel TFT (NTFT)
Area was formed.

Thereafter, annealing was performed by laser light irradiation. As the laser light, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was used, but another laser may be used. The irradiation condition of the laser light is such that the energy density is 200 to 400 mJ / c.
m ² , for example, 250 mJ / cm ^2, and 2
Irradiation was performed for 10 to 10 shots, for example, 2 shots. The effect may be increased by heating the substrate to about 200 to 450 ° C. during the irradiation with the laser light. (Figure 1
(D))

Subsequently, a silicon oxide film 11 having a thickness of 6000.degree.
8 was formed as an interlayer insulator by a plasma CVD method. As the interlayer insulator, polyimide or a two-layer film of silicon oxide and polyimide may be used. Further, a contact hole is formed, and a metal material, for example, a multilayer film of titanium nitride and aluminum is used to form a TFT electrode / wiring 1.
17, 120 and 119 were formed. Finally, annealing is performed at 350 ° C. for 30 minutes in a hydrogen atmosphere at 1 atm.
A semiconductor circuit in which the FT has a complementary structure has been completed. (Figure 1
(E) The circuit shown above has a CMOS structure in which PTFTs and NTFTs are provided in a complementary manner. In the above-described process, two TFTs are simultaneously formed and cut at the center to form two independent TFTs. It is also possible to manufacture them at the same time.

In this embodiment, as a method for introducing nickel, nickel is selectively thinned on the base film 102 under the amorphous silicon film 104 (it is difficult to observe nickel as a thin film). And a method of growing crystals from this portion is adopted.
After the formation of 4, a method of selectively forming a nickel film may be used. That is, crystal growth may be performed from the upper surface of the amorphous silicon film, or may be performed from the lower surface. Alternatively, a method in which an amorphous silicon film is formed in advance and nickel ions are selectively implanted into the amorphous silicon film 104 by using an ion doping method may be employed. This case has a feature that the concentration of the nickel element can be finely controlled. Alternatively, a method using a plasma treatment or a CVD method may be used.

[Embodiment 2] This embodiment is an example in which an N-channel TFT is provided in each pixel as a switching element in an active liquid crystal display device. Hereinafter, one pixel will be described, but a large number (generally, hundreds of thousands) of other pixels are formed in a similar structure. Also, N
It goes without saying that a P-channel TFT may be used instead of a channel TFT. Further, it can be used not only for the pixel portion of the liquid crystal display device but also for the peripheral circuit portion. Further, it can be used for image sensors and other devices. That is, as long as it is used as a thin film transistor, its use is not particularly limited.

FIG. 2 shows an outline of the manufacturing process of this embodiment.
In this embodiment, as the substrate 201, an OA-2 substrate manufactured by NEC Corporation (strain point 635 ° C., thickness 1.1 mm,
00 × 400 mm). First, the substrate was annealed at 700 ° C. for 1 hour at a temperature equal to or higher than the strain point, and then 0.2 ° C.
At 600 ° C./min. The shrinkage of the substrate was greatly reduced by the above heat treatment. For example, annealing at 600 ° C. for 4 hours showed only 20 ppm, and annealing at 550 ° C. for 4 hours showed only a shrinkage of 10 ppm.

A base film 202 (silicon oxide) is formed on the substrate 201 having been subjected to such a heat treatment by a plasma CVD method for 2000 times.
Å was formed. TEO as source gas for CVD
S and oxygen were used. Thereafter, a mask 203 was formed of polyimide in order to selectively introduce nickel. Then, a nickel film was formed by a sputtering method. This nickel film is formed by a sputtering method.
It was formed to a thickness of 5 to 200 mm, for example, 20 mm. Thus, the nickel film was selectively formed in the region 204. (Fig. 2 (A))

Thereafter, LPCVD or plasma C
An amorphous silicon film 205 was formed to a thickness of 1000 ° by the VD method. Then, after dehydrogenation was performed at 450 ° C. for 1 hour, crystallization was performed by heat annealing. This annealing step was performed at 600 ° C. for 4 hours in a nitrogen atmosphere. In this annealing step, the amorphous silicon film 205
Since a nickel film was formed in the lower region 204, crystallization occurred from this portion. During this crystallization,
In the region 204 where nickel is deposited, the substrate 201
The crystal growth of silicon proceeded in the vertical direction. In addition, as indicated by arrows, in regions where nickel was not deposited (regions other than region 205), crystal growth proceeded in a direction parallel to the substrate. (FIG. 2 (B))

After this thermal annealing step, the crystallized silicon film was patterned to leave only the island-like active layer 205 'of the TFT and to remove the others. At this time, it is important that the tip of the grown crystal does not exist in the active layer, especially in the channel formation region. Specifically, in the silicon film 205 of FIG. 2B, at least the tip of crystallization and the portion of 204 into which nickel has been introduced are removed by etching, and the crystalline silicon film 205 is removed in a direction parallel to the substrate. It is preferable to use the intermediate portion where the crystal has grown as an active layer. This is to prevent the nickel concentrated at the front end portion from adversely affecting the characteristics of the TFT based on the fact that nickel is concentrated at the front end portion and the introduction portion of the crystal growth.

Thereafter, tetraethoxysilane (TE)
OS) as a raw material, a gate insulating film of silicon oxide (thickness of 70 to 120) is formed by a plasma CVD method in an oxygen atmosphere.
nm, typically 120 nm) 206 was formed. The substrate temperature was 350 ° C. (Fig. 2 (C))

Next, a known film containing polycrystalline silicon as a main component is formed by a CVD method, and is subjected to patterning.
A gate electrode 207 was formed. Phosphorus was introduced into polycrystalline silicon as an impurity in an amount of 0.1 to 5% in order to improve conductivity.

Thereafter, phosphorus is implanted as an N-type impurity by ion doping, and the source region 20 is self-aligned.
8, a channel formation region 209 and a drain region 210 were formed. Then, by performing annealing at 550 ° C. for 4 hours, the crystallinity of the silicon film having deteriorated crystallinity due to ion implantation was improved. The active layer was easily crystallized because it originally contained nickel which has the effect of promoting crystallization. Due to this thermal annealing, the source / drain sheet resistance of this TFT becomes 300 to 80.
It was 0 Ω / cm ² . (FIG. 2 (D))

Thereafter, an interlayer insulator 211 is formed of silicon oxide or polyimide, and further, a pixel electrode 212 is formed.
Was formed by ITO. Then, a contact hole is formed, and a chromium /
The electrodes 213 and 214 are formed of an aluminum multilayer film, and one of the electrodes 214 is also connected to the ITO 212. Finally, hydrogenation was performed by annealing in hydrogen at 200 to 400 ° C. for 2 hours. In this way,
The TFT was completed. This step is performed simultaneously in other many pixel regions. In order to further improve the moisture resistance, a passivation film may be formed on the entire surface using silicon nitride or the like. (FIG. 2 (E))

In the TFT manufactured in this embodiment, a crystalline silicon film grown in the direction in which carriers flow is used as an active layer constituting a source region, a channel formation region, and a drain region. Is not traversed by the carrier, that is, the carrier moves along the crystal grain boundary of the needle-like crystal, so that a TFT having high carrier mobility can be obtained. TFT manufactured in this example
Is an N-channel type, and its mobility is 90 to 130.
(Cm ² / Vs). Movement to a conventional N-channel TFT using a crystalline silicon film obtained by crystallization by thermal annealing at 600 ° C. for 48 hours is 50 to 70 (c).
m ² / Vs), which is a great improvement in characteristics.

In this embodiment, the thermal annealing means is used for activating the doping impurities. This is a milder reaction than the case where laser light is used as in the first embodiment. In particular, in laser annealing, the discontinuity of crystallinity at the boundary between the shadowed portion of the gate electrode portion and the portion irradiated with the laser caused a decrease in reliability. Since the / drain region was similarly heated, it was particularly excellent in reliability.

[Embodiment 3] This embodiment will be described with reference to FIG. No. 1733 glass (strain point: 640 ° C.) manufactured by Corning Incorporated was used as the substrate. The glass is annealed at 700 ° C. above the strain point for 1 hour and then at 0.2 ° C./min for 6 hours.
It was gradually cooled to 00 ° C. Then, a base film 302 was formed on the glass substrate 301 by a plasma CVD method, and an amorphous silicon film 304 having a thickness of 300 to 800 ° was formed by a plasma CVD method. And a thickness of 1000
A nickel film was formed in a region indicated by 300 using the silicon oxide mask 303 in the same manner as in Example 1. Next, heat annealing at 550 ° C. for 8 hours was performed to crystallize the silicon film 304. At this time, as indicated by an arrow 305, crystal growth proceeded in a direction parallel to the substrate. (FIG. 3 (A))

Next, the silicon film 304 is patterned
Island-shaped active layer regions 306 and 307 were formed. At this time, a region indicated by 300 in FIG. 3A is a region where nickel is directly introduced, and is a region where nickel is present at a high concentration. Also, as shown in Examples 1 and 2, nickel also exists at a high concentration at the end point of crystal growth. It has been found that these regions have a nickel concentration that is nearly an order of magnitude higher than the crystallized regions between them. Therefore, in this embodiment, the active layer regions 306 and 307, which are regions for forming an active element, for example, a TFT, are patterned so as to avoid these regions having a high nickel concentration, and the regions having a high nickel concentration are intentionally formed. Removed. The etching of the active layer was performed by the RIE method having anisotropy in the vertical direction. (FIG. 3 (B))

In this embodiment, a complementary TFT circuit is obtained by utilizing the active layers 306 and 307. That is, the circuit of the present embodiment is different from the configuration of the first embodiment shown in FIG. 1D in that the PTFT and the NTFT are separated.
That is, in the structure shown in FIG.
The active layer of the FT is continuously connected, and the nickel concentration is high in the intermediate region. However, the present embodiment has a feature that the nickel concentration is low regardless of which part is taken. Therefore, operation stability can be improved.

Next, a silicon oxide or silicon nitride film 308 having a thickness of 200 to 3000 ° was formed by a plasma CVD method. Then, lamp annealing of visible / near infrared light was performed. A halogen lamp was used as an infrared light source. The wavelength is 0.5 which is well absorbed by crystalline silicon.
４4 μm, preferably 0.8-1.3 μm. The intensity of the visible / near-infrared light is 800 to 1300 ° C. on the single crystal silicon wafer of the monitor, typically 900 to 1
Adjusted to be between 200 ° C. Specifically, the temperature of the thermocouple embedded in the silicon wafer was monitored and fed back to the infrared light source. Note that the infrared light irradiation was performed in an H ₂ atmosphere. 0.1% to 10% HCl, a compound of hydrogen halide, fluorine, chlorine, or bromine may be mixed in the H ₂ atmosphere.

In this embodiment, when irradiating visible / near infrared light,
Since a protective film of silicon oxide or silicon nitride was formed on the surface of the active layer, it was possible to prevent the surface from being roughened and contaminated upon irradiation with infrared light. By using such a lamp annealing step together, it was possible to improve the crystallinity, which was insufficient only by crystallization by thermal annealing. (FIG. 3 (C))

After the irradiation with visible / near infrared light, the protective film 308 was removed. Thereafter, as in the first embodiment, the gate insulating film 30 is formed.
9. Gate electrodes 310 and 311 were formed. Tantalum is used as a gate electrode, and a tantalum oxide film is coated on the surface of the gate electrode by anodization at 1000-300.
0 °, for example, 3000 ° was formed. Then, as in Example 1, an impurity element was introduced by ion doping to form source / drain regions.

The lamp annealing method was used to activate the impurities. A halogen lamp was used as an infrared light source. The wavelength is 0.5-4 μm, preferably 0.8-1.3.
Irradiation with visible / infrared light of μm was performed for 30 to 180 seconds. Visible / near infrared rays of the above wavelengths contain 10 ¹⁹ to 10 ²¹ phosphorus or boron.
It is easily absorbed by amorphous silicon to which cm ^{-3 is} added.
Effective annealing comparable to thermal annealing of 00 ° C. or more can be performed. On the other hand, since it is hardly absorbed by the glass substrate, it is not necessary to heat the glass substrate to a high temperature, and the process can be performed in a short time. . In particular, in the present embodiment, the processing is performed in advance so as not to cause the contraction of the substrate.

The intensity of the visible / near-infrared light was adjusted so that the temperature of the monitor on the single crystal silicon wafer was 800 to 1300 ° C., typically 900 to 1200 ° C. Specifically, the temperature of the thermocouple embedded in the silicon wafer was monitored and fed back to the infrared light source. Note that the infrared light irradiation was performed in an H ₂ atmosphere. 0.1% to 10% HCl, a compound of hydrogen halide, fluorine, chlorine, or bromine may be mixed in the H ₂ atmosphere. (FIG. 3 (D))

Thereafter, an interlayer insulator 312 is formed, a contact hole is formed in the interlayer insulator 312, and the metal wirings 313 and 33 are formed.
14, 315 were formed. Further, hydrogenation was performed by annealing at 250 to 400 ° C., for example, 350 ° C. in a hydrogen atmosphere at 1 atm. (FIG. 3E) Thus, a complementary TFT circuit was formed. In the present embodiment, a protective film is formed on the surface of the active layer during lamp annealing (visible / near-infrared light irradiation), so that surface roughness and contamination are prevented. Therefore, the characteristics (electric field mobility and threshold voltage) and reliability of the TFT of this example were extremely good.

[Embodiment 4] This embodiment will be described with reference to FIG. The substrate used was NA4 manufactured by NH Techno Glass Co., Ltd.
Five glasses (strain point 610 ° C.) were used. First, the substrate was annealed in a nitrous oxide (N ₂ O) atmosphere at 650 ° C. above the strain point for 1 hour, and then gradually cooled to 500 ° C. at 0.2 ° C./min. A base film was formed over a glass substrate 501 by a plasma CVD method. First, a silicon nitride film 50 is formed on a substrate.
2 is formed to a thickness of 1000 °, and a silicon oxide film 503 is further
The film was formed at 00 ° to form an underlayer consisting of two layers. The reason for forming the silicon nitride film 702 is to eliminate contamination by mobile ions and the like from the glass substrate.

Then, a thickness of 3
Amorphous silicon film 50 having a thickness of 100 to 800 °, for example, 500 °
4 was formed. Further, a mask 505 of silicon oxide having a thickness of 1000 ° was formed. Then, a nickel acetate film 5 is formed by spin coating using a nickel acetate solution.
06 was formed. Nickel concentration is 50 ~ 300pp
m, for example, 100 ppm. At this time, the nickel acetate film 506 is not necessarily a film because it is extremely thin, about several to several tens of degrees. (FIG. 5 (A))

Next, heat annealing at 550 ° C. for 8 hours was performed to crystallize the amorphous silicon film 504. At this time, as indicated by arrows, crystal growth proceeded in a direction parallel to the substrate. Next, after removing the mask 505 (which is also a protective film at the time of crystallization annealing), laser crystallization was performed to improve crystallinity. KrF excimer laser light (wavelength 248 nm) is 200 to 300 mJ / c
By irradiation with m ² , a crystalline silicon film 607 was obtained. (FIG. 5 (B))

Thereafter, the crystalline silicon film 507 was patterned to form an island-shaped active layer region 511. On this occasion,
An area indicated by 508 in FIG. 5B is an area where nickel is directly introduced, and an area where nickel is present at a high concentration. Also, as shown in Examples 1 and 2, nickel also exists at a high concentration at the end points 509 and 510 of the crystal growth. It has been found that these regions have a nickel concentration that is nearly an order of magnitude higher than the crystallized regions between them. Therefore, in the present embodiment, the active layer region, which is a region for forming an active element, for example, a pixel TFT, is patterned so as to avoid these regions having a high nickel concentration, and the high concentration region of nickel is intentionally removed. . The etching of the active layer was performed by the RIE method having anisotropy in the vertical direction.

Next, a silicon oxide film having a thickness of 200 to 3000 Å, for example, 1000 Å was formed as a gate insulating film 512 by a plasma CVD method. After that, thickness 1
An aluminum (containing 1 wt% of Si or 0.1 to 0.3 wt% of Sc) film of 000 to 3 μm, for example, 5000 Å was formed by a sputtering method.
Then, a photoresist was formed by a spin coating method. If an aluminum oxide film having a thickness of 100 to 1000 ° is formed on the surface by anodic oxidation before forming the photoresist, the adhesiveness of the photoresist is improved. Thereafter, the photoresist and the aluminum film were patterned to form a gate electrode 513. After the etching is completed, the photoresist is not removed, and the gate electrode 51 is not removed.
3 as a mask film 514.

Further, a porous anodic oxide 515 having a thickness of 3000 to 6000 °, for example, 5000 °, was formed by passing a current through the electrolytic solution in the electrolytic solution. The porous anodic oxidation may be performed using a 3 to 20% aqueous acid solution of citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid, or the like, and a constant current of 5 to 30 V may be applied to the gate electrode. In this example, in a oxalic acid solution (30 ° C.), the voltage was set to 10 V, and anodic oxidation was performed for 20 to 40 minutes. The thickness of the porous anodic oxide was controlled by the time for performing anodic oxidation. (FIG. 5 (C))

Thereafter, the mask 514 was peeled off and barrier anodic oxidation was performed. In this case, the substrate was adjusted to pH 7, 7, 1
The electrode was immersed in an ethylene glycol solution of ~ 3% tartaric acid, and the anode was used as a cathode with platinum as the anode and the voltage was gradually increased to proceed anodic oxidation. Thus, a dense and high withstand voltage barrier-type anodic oxide 616 was formed.

Then, the gate insulating film 512 was etched by a dry etching method. At this time, the anodic oxides 515 and 516 are not etched, and the gate insulating film 5 is not etched.
When only island 12 was etched and island-shaped active layer 511 appeared, etching was terminated. As a result, the gate insulating film 512 ′ under the porous anodic oxide 515 remained without being etched. (FIG. 5 (D))

Thereafter, the porous anodic oxide 515 was removed by etching. Then, boron is implanted into the island-like active layer 511 as an impurity in the island-like active layer 511 in a self-aligned manner using the gate electrode portion (gate electrode, barrier type anodic oxide, silicon oxide film) as a mask. 517 were formed. Here, diborane (B ₂ H ₆ ) was used as the doping gas. At this time, the dose of boron is 1 to 4 × 10 ¹⁵ atoms / cm ² , and the acceleration voltage is 1
0 kV. Here, since the acceleration voltage is low, the lower part of the gate insulating film is not doped and boron is not introduced, and an offset region is formed. (FIG. 5E)

Further, this was subjected to thermal annealing at 350 to 550 ° C., for example, at 500 ° C. for 4 hours to activate the doped impurities. At this time, the deformation of the substrate was extremely small. Further, in order to further promote activation, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was irradiated. The energy density of the laser is 200-400 mJ / cm ² , preferably 25
0 to 300 mJ / cm ² was appropriate. At this time, the PI junction existing under the gate insulating film 512 'was sufficiently activated by laser irradiation. Next, a silicon oxide film was formed as an interlayer insulating film 519 at 3000 ° by a plasma CVD method.

Then, the interlayer insulating film 519 was etched to form a contact hole in the source region.
Thereafter, an aluminum film was formed by a sputtering method, and patterning was performed to form a source electrode 519. (FIG. 5F) Finally, a passivation film 520 having a thickness of 1000 to 1000
A silicon nitride film of 6000Å, for example, 3000Å was formed by a plasma CVD method, and the interlayer insulating film 518 was etched to form a contact hole in the drain. Thereafter, an indium tin oxide film (ITO film) was formed, and this was etched to form a pixel electrode 521. (FIG. 5G) As described above, a pixel TFT having a P-channel type offset region was formed.

[Embodiment 5] This embodiment will be described with reference to FIG. No. 1733 glass manufactured by Corning was used as the substrate. First, the substrate is annealed in a nitrogen (N ₂ ) atmosphere at 700 ° C. above the strain point for 1 hour,
It was gradually cooled to 600 ° C. in minutes. After that, the glass substrate 601
An underlayer was formed thereon. Here, an aluminum nitride film 602 is formed on a substrate by sputtering at 1000Å.
A silicon oxide film 6 is formed by plasma CVD.
03 was formed to a thickness of 1000 ° to form an underlayer consisting of two layers. The reason for forming the aluminum nitride film 702 is to eliminate contamination by mobile ions and the like from the glass substrate.

Then, a thickness of 3
The amorphous silicon film 60 having a thickness of 100 to 800 °, for example, 500 °
4 was formed. Further, a silicon oxide mask 605 having a thickness of 1000 ° was formed. Then, a nickel acetate film 6 is formed by a spin coating method using a nickel acetate solution.
06 was formed. (FIG. 6A) Next, heat annealing at 550 ° C. for 8 hours was performed to crystallize the amorphous silicon film 604. At this time, as indicated by arrows, crystal growth proceeded in a direction parallel to the substrate.

Next, after removing the mask, laser crystallization was performed to improve the crystallinity. The crystalline silicon film 607 was obtained by irradiating a KrF excimer laser beam at 200 to 300 mJ / cm ² . (FIG. 6
(B)) Thereafter, the crystalline silicon film 607 was patterned to form an island-shaped active layer region 611. At this time, as in Example 4, the active layer was formed avoiding the region where the nickel concentration was high.

Next, a silicon oxide film having a thickness of 200 to 3000 Å, for example, 1200 Å was formed as a gate insulating film 612 by a plasma CVD method. After that, thickness 1
An aluminum film of 000 ° to 3 μm, for example, 6000 ° was formed by a sputtering method. Then, a gate electrode 613, a photoresist mask 614, and a porous anodic oxide 615 were formed in the same manner as in Example 4. (FIG. 6 (C)) Thereafter, the mask 614 was peeled off and barrier anodic oxidation was performed to form a barrier type anodic oxide 616. And
As a result of etching the gate insulating film by a dry etching method, a gate insulating film 612 ′ under the porous anodic oxide 616 remained. (FIG. 6 (D))

Thereafter, the porous anodic oxide 615 is etched and removed, and the porous anodic oxide 615 is removed by ion doping.
A gate electrode portion (gate electrode,
Using a barrier-type anodic oxide, a silicon oxide film) as a mask, boron as an impurity was implanted in a self-aligned manner to form a P-type impurity region 617. (FIG. 6E)

Further, a KrF excimer laser (wavelength 2
Irradiation of 48 nm and a pulse width of 20 nsec) was performed to activate the impurity region 617. Further, in order to improve the junction between the source / channel and the drain / channel, thermal annealing was performed at 350 to 550 ° C., for example, 500 ° C. for 4 hours. Next, a silicon oxide film is formed as an interlayer insulating film 618 by a plasma CVD method at 3000.
Was formed.

Then, the interlayer insulating film 618 was etched to form a contact hole in the source region.
Thereafter, an aluminum film was formed by a sputtering method, and patterning was performed to form a source electrode 619. (FIG. 6F) Finally, a passivation film 620 having a thickness of 2000 to 2000 is formed.
A silicon nitride film of 6000Å, for example, 3000Å was formed by a plasma CVD method, and the interlayer insulating film 618 was etched to form a contact hole in the drain. Thereafter, an indium tin oxide film (ITO film) was formed, and this was etched to form a pixel electrode 621. (FIG. 6G) As described above, a pixel TFT having a P-channel type offset region was formed.

[Embodiment 6] This embodiment will be described with reference to FIG. No. 7059 glass manufactured by Corning was used as the substrate. First, after annealing the substrate in an ammonia (NH ₃ ) atmosphere at 640 ° C. above the strain point for 1 hour,
It was gradually cooled to 400 ° C. at 0.2 ° C./min. After that, a base film was formed over the glass substrate 701. Here, a silicon oxide film 702 is formed on a substrate by a plasma CVD method to a thickness of 1000.
A film was formed, and a silicon nitride film 703 was further formed to a thickness of 1000 by a plasma CVD method to form a two-layer base film.

Then, a thickness of 3
Amorphous silicon film 70 having a thickness of 100 to 800, for example, 500
4 was formed. Further, a mask 705 of silicon oxide having a thickness of 1000 ° was formed. Then, a nickel acetate film 7 is formed by a spin coating method using a nickel acetate solution.
06 was formed. (FIG. 7A) Next, heat annealing was performed at 550 ° C. for 8 hours to crystallize the amorphous silicon film 704. At this time, as indicated by arrows, crystal growth proceeded in a direction parallel to the substrate.

Next, after removing the mask, laser crystallization was performed to improve the crystallinity. The crystalline silicon film 707 was obtained by irradiating a KrF excimer laser beam at 200 to 300 mJ / cm ² . (FIG. 7
(B)) Thereafter, the crystalline silicon film 707 was patterned to form an island-shaped active layer region 711. At this time, as in Example 4, the active layer was formed avoiding the region where the nickel concentration was high. At this time, etching was performed by the RIE method. However, since the etching rate of the silicon nitride oxide film 703 was much lower than that of the silicon film, overetching of the base film was small.

Next, a silicon oxide film having a thickness of 200 to 3000 Å, for example, 1200 Å was formed as a gate insulating film 712 by a plasma CVD method. After that, thickness 1
An aluminum film of 000 ° to 3 μm, for example, 6000 ° was formed by a sputtering method. Then, a gate electrode 713, a photoresist mask 714, and a porous anodic oxide 715 were formed in the same manner as in Example 4. (FIG. 7 (C))

Thereafter, the mask 714 was peeled off and barrier anodic oxidation was performed to form a barrier type anodic oxide 716. Then, as a result of etching the gate insulating film by the dry etching method, the porous anodic oxide 71 is formed.
The gate insulating film 712 'under 6 remains. (FIG. 7
(D))

After that, the porous anodic oxide 715 is removed by etching, and the porous anodic oxide 715 is removed by ion doping.
A gate electrode portion (gate electrode,
Using a barrier-type anodic oxide, a silicon oxide film) as a mask, boron as an impurity was implanted in a self-aligned manner to form a P-type impurity region 717. (FIG. 7E)

Further, at 350 to 550 ° C., for example, at 50
Thermal annealing at 0 ° C. for 4 hours was performed to activate the doped impurities. Then, in order to more preferably activate, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated. Thereafter, in order to improve the characteristics of the source / channel junction and the drain / channel junction, 350 to 550 ° C.
For example, annealing was performed at 480 ° C. for one hour. Next, a silicon oxide film was formed as an interlayer insulating film 718 at 3000 ° by a plasma CVD method.

Then, the interlayer insulating film 718 was etched to form a contact hole in the source region.
Thereafter, an aluminum film was formed by a sputtering method, and patterning was performed to form a source electrode 719. (FIG. 7F) Finally, a passivation film 720 having a thickness of 2000 to 2000
A silicon nitride film of 6000Å, for example, 3000Å was formed by a plasma CVD method, and the interlayer insulating film 718 was etched to form a contact hole in the drain. Thereafter, an indium tin oxide film (ITO film) was formed, and this was etched to form a pixel electrode 721. (FIG. 7G) As described above, the pixel TFT having the P-channel type offset region was formed.

[0086]

As described above, the substrate is thermally annealed at a temperature equal to or higher than the strain point and gradually cooled, whereby the shrinkage of the substrate due to the subsequent heat treatment becomes very small. Generally, the patterning step (mask alignment step) of introducing nickel as shown in the embodiment does not require much accuracy compared to other patterning steps. On the other hand, patterning for forming contact holes and forming gate electrodes requires an accuracy of several μm or less. For this reason, conventionally, activation of doping impurities has mainly been performed by laser annealing which does not substantially involve a thermal process.

However, according to the present invention, since the substrate shrinkage can be suppressed to a considerable temperature, it is more suitable for mass production such as thermal annealing as shown in Embodiment 2 and lamp annealing as shown in Embodiment 3. Means can be used. As described above, the present invention is extremely effective for forming a semiconductor device on an insulating substrate.

[Brief description of the drawings]

FIG. 1 shows a manufacturing process of a TFT of Example 1.

FIG. 2 illustrates a manufacturing process of a TFT of Example 2.

FIG. 3 illustrates a manufacturing process of a TFT according to a third embodiment.

FIG. 4 shows an example of a conventional patterning shift due to substrate shrinkage.

FIG. 5 shows a manufacturing process of the TFT of Example 4.

FIG. 6 illustrates a manufacturing process of a TFT of Example 5.

FIG. 7 shows a manufacturing process of the TFT of Example 6.

FIG. 8 shows a configuration example of a thermal annealing furnace used in the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 nickel-introduced portion 101 glass substrate 102 base film (silicon oxide film) 103 mask 104 silicon film 104 ′ island-like silicon film (active layer) 105 region with high nickel concentration 106 gate insulating film (silicon oxide film) 107 gate electrode ( Aluminum) 108 Anodized layer (aluminum oxide) 109 Gate electrode 110 Anodized layer 111 Source (drain) region 112 Channel formation region 113 Drain (source) region 114 Source (drain) region 115 Channel formation region 116 Drain (source) region 117 Electrode 118 Interlayer insulator 119 Electrode 120 Electrode

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Shoji Miyanaga 398 Hase, Hase, Atsugi, Kanagawa Prefecture (72) Inventor Hisashi Ohtani 398 Hase, Hase, Atsugi, Kanagawa Pref. 72) Inventor Hirohide Zhang 398 Hase, Atsugi City, Kanagawa Prefecture Inside the Semi-Conductor Energy Laboratory Co., Ltd.

Claims (10)

[Claims] 1. A glass substrate formed by heating at a temperature equal to or higher than a strain point, and then cooling it to a temperature equal to or lower than the strain point at a rate of 2 ° C./min or less. 2. A glass substrate formed by heating at a temperature equal to or higher than the strain point, and then cooling it to a temperature equal to or lower than the strain point at a rate of 0.5 ° C./min or less. 3. A glass substrate formed by heating at a temperature equal to or higher than a strain point and then cooling to a temperature equal to or lower than the strain point at a rate of 0.3 ° C./min or less. 4. The glass substrate according to claim 1, wherein the heating at a temperature higher than the strain point is performed in an oxidizing atmosphere or a nitriding atmosphere. 5. The glass substrate according to claim 1, wherein the temperature above the strain point is 600 to 660 ° C. 6. A method for manufacturing a glass substrate, comprising heating at a temperature equal to or higher than the strain point and then cooling at a rate of 2 ° C./min or less to a temperature equal to or lower than the strain point. 7. A method for manufacturing a glass substrate, comprising: heating at a temperature equal to or higher than a strain point, and then cooling to a temperature equal to or lower than the strain point at a rate of 0.5 ° C./min or less. 8. A method for manufacturing a glass substrate, comprising: heating at a temperature equal to or higher than a strain point, and then cooling to a temperature equal to or lower than the strain point at a rate of 0.3 ° C./min or less. 9. The method for manufacturing a glass substrate according to claim 6, wherein the heating at a temperature higher than the strain point is performed in an oxidizing atmosphere or a nitriding atmosphere. 10. The method for manufacturing a glass substrate according to claim 6, wherein the temperature equal to or higher than the strain point is 600 to 660 ° C.