CN112018187A - LDMOS device and manufacturing method thereof - Google Patents

LDMOS device and manufacturing method thereof Download PDF

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CN112018187A
CN112018187A CN202011054814.5A CN202011054814A CN112018187A CN 112018187 A CN112018187 A CN 112018187A CN 202011054814 A CN202011054814 A CN 202011054814A CN 112018187 A CN112018187 A CN 112018187A
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well
region
well region
heavily doped
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CN112018187B (en
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段文婷
房子荃
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The application discloses an LDMOS device and a manufacturing method thereof, and relates to the field of semiconductor manufacturing. The LDMOS device comprises a substrate, a first type deep well, a first type well region and a second type well region, wherein the first type deep well, the first type well region and the second type well region are arranged in the substrate; the first-type well region is positioned between the first-type deep well and the second-type well region; one end of the first-type deep well is provided with a first-type heavily doped region; the surface of the substrate is provided with a grid structure, the first-class well region is positioned below the grid structure, the grid structure is separated from the first-class heavily doped region in the first-class deep well through field oxygen, and one end of the grid structure extends to the surface of the field oxygen above the first deep well; the other end of the grid structure is positioned above the second-type well region; a first type heavily doped region and a second type heavily doped region are arranged in the second type well region; the problem that quasi-saturation occurs in an IDVD curve of the traditional middle-high voltage LDMOS device is solved; the effect of improving the performance of the medium-high voltage LDMOS device is achieved.

Description

LDMOS device and manufacturing method thereof
Technical Field
The application relates to the field of semiconductor manufacturing, in particular to an LDMOS device and a manufacturing method thereof.
Background
LDMOS (laterally Diffused Metal Oxide semiconductor) has the characteristics of high voltage resistance, high current driving capability, extremely low power consumption, capability of being integrated with a CMOS (complementary Metal Oxide semiconductor) and the like, and is widely applied to a power supply management circuit.
Taking a middle-high voltage NLDMOS device as an example, an N-type deep well is formed in a substrate, and the N-type deep well is used for realizing high breakdown voltage, and the N-type deep well can be diffused into a drift region after being thermally advanced, but the concentration of the diffused drift region below a gate oxide layer is low, so that a drain end current (Id) -drain end voltage (Vd) curve of the NLDMOS device is subjected to quasi-saturation.
Disclosure of Invention
In order to solve the problems in the related art, the present application provides an LDMOS device and a method of manufacturing the same. The technical scheme is as follows:
in a first aspect, an embodiment of the present application provides an LDMOS device, which includes a substrate, a first-type deep well, a first-type well region, and a second-type well region in the substrate;
the first-type well region is positioned between the first-type deep well and the second-type well region;
one end of the first-type deep well is provided with a first-type heavily doped region;
the surface of the substrate is provided with a grid structure, the first-class well region is positioned below the grid structure, the grid structure is separated from the first-class heavily doped region in the first-class deep well through field oxygen, and one end of the grid structure extends to the surface of the field oxygen above the first deep well;
the other end of the grid structure is positioned above the second-type well region;
the second type well region is internally provided with a first type heavily doped region and a second type heavily doped region.
Optionally, the opening size range of the first-type well region is 0.2um to 1 um.
Optionally, the first type heavily doped region and the second type heavily doped region in the second type well region are separated by field oxygen.
Optionally, an interlayer dielectric layer is arranged on the substrate, and a contact hole is arranged in the interlayer dielectric layer;
the first heavy doping area, the second heavy doping area and the grid structure are respectively led out through the contact holes and are connected with the metal electrode above the interlayer dielectric layer.
Optionally, the gate structure includes a gate oxide layer, a polysilicon gate, and a gate sidewall.
Optionally, the substrate is P-type, the first-type deep well is N-type deep well, the first-type well region is N-well, and the second-type well region is P-well.
Optionally, the substrate is an N-type substrate, the first-type deep well is a P-type deep well, the first-type well region is a P-type well, and the second-type well region is an N-type well.
In a second aspect, an embodiment of the present application provides a method for manufacturing an LDMOS device, where the method includes:
forming a first type deep well in a substrate;
forming field oxygen on the substrate, wherein one end of the first-type deep well is positioned below the field oxygen;
forming a first well region in a substrate;
forming a second-class well region in the substrate, wherein the first-class well region is positioned between the second-class well region and the first-class deep well;
forming a grid structure, wherein one end of the grid structure extends to the surface of the field oxide above the first deep well, and the other end of the grid structure is positioned above the second-type well region;
and forming a first type heavily doped region in the first type deep well, and forming a first type heavily doped region and a second type heavily doped region in the second type well region, wherein the first type heavily doped region in the first type deep well is separated from the gate structure by field oxygen.
Optionally, forming a first well region in the substrate includes:
defining a first type well region injection region through a photoetching process;
and implanting doping ions into the substrate corresponding to the first-class well region implantation area through an ion implantation process to form a first-class well region.
Optionally, the opening size range of the first-type well region is 0.2um to 1 um.
Optionally, field oxide is formed on the surface of the second-type well region, and the first-type heavily doped region and the second-type heavily doped region formed in the second-type well region are separated by the field oxide.
Optionally, the method further includes:
forming an interlayer dielectric layer;
forming a contact hole in the interlayer dielectric layer;
and forming a metal electrode on the surface of the interlayer dielectric layer, wherein the first type heavily doped region, the second type heavily doped region and the grid structure are respectively connected with the metal electrode through contact holes.
Optionally, forming a gate structure includes:
forming a gate oxide layer;
forming a polysilicon layer;
forming a polysilicon gate through a photoetching process and an etching process, wherein one end of the polysilicon gate extends to the surface of the field oxide above the first deep well, and the other end of the polysilicon gate is positioned above the second well-like region;
and forming grid side walls on two sides of the polysilicon grid.
Optionally, the substrate is P-type, the first-type deep well is N-type deep well, the first-type well region is N-well, and the second-type well region is P-well.
Optionally, the substrate is an N-type substrate, the first-type deep well is a P-type deep well, the first-type well region is a P-type well, and the second-type well region is an N-type well.
The technical scheme at least comprises the following advantages:
the substrate of the LDMOS device provided by the embodiment of the application is provided with a first-class well region, a second-class well region and a first-class deep well, the first-class well region is positioned between the first-class deep well and the second-class well region, the first-class well region is positioned below a gate oxide layer, the depth of the first-class deep well is greater than that of the first-class well region, the first-class deep well and the first-class well region are thermally promoted and then are diffused to the whole drift region, the concentration of the drift region is increased through the first-class well region, and the problem that an IDVD curve of the existing medium-high voltage LDMOS device is quasi-saturated due to the fact that the drift region is light; the quasi-saturation phenomenon in a drain current-drain voltage curve of the LDMOS device is improved, and the performance of the medium-high voltage LDMOS device is improved. In addition, the opening size of the first-class well region is controlled to be smaller, so that the reduced breakdown voltage can still meet the performance requirement of the device under the condition of increasing the concentration of the drift region.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of an LDMOS device provided in an embodiment of the present application;
fig. 2 is a flowchart of a method for manufacturing an LDMOS device according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram of a process for manufacturing an LDMOS device according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram of a process for manufacturing an LDMOS device according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a process for manufacturing an LDMOS device according to an embodiment of the present disclosure;
FIG. 6 is a schematic diagram of a process for manufacturing an LDMOS device according to an embodiment of the present disclosure;
FIG. 7 is a schematic diagram of a process for manufacturing an LDMOS device according to an embodiment of the present disclosure;
FIG. 8 is a schematic diagram of a process for manufacturing an LDMOS device according to an embodiment of the present disclosure;
FIG. 9 is a graph of drain current versus drain voltage for an LDMOS device according to an embodiment of the present disclosure;
fig. 10 is a graph of drain current versus drain voltage for a conventional LDMOS device.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, a schematic structural diagram of an LDMOS device provided by an embodiment of the present application is shown, where the LDMOS device includes a substrate 11, a first-type deep well 12 in the substrate, a first-type well region 13, and a second-type well region 14.
The first-type well regions 13 are located between the first-type deep wells 12 and the second-type well regions 14.
The doping types of the first-class well region and the first-class deep well are the same, and the doping types of the first-class well region and the second-class well region are different.
The surface of the substrate is provided with a gate structure 15, the first well region 13 is positioned below the gate structure 15, and the gate structure 15 is separated from a first heavily doped region 16 in the first deep well 12 by field oxide 17.
One end of the first type deep well 12 is located below the field oxide 17.
The first type heavily doped region 16 in the first type deep well 12 is the drain terminal of the LDMOS device.
One end of the gate structure 15 extends to the surface of the field oxide 17 above the first deep well 12, and the other end of the gate structure 15 is located above the second-type well region 14.
A first type heavily doped region 18 and a second type heavily doped region 19 are disposed in the second type well region 14.
The doping types of the first type heavily doped region and the second type heavily doped region are opposite.
In the process of manufacturing the LDMOS device, after the first-type deep well 11 is formed, the first-type deep well is diffused into a drift region in a subsequent thermal process, the concentration of the drift region is relatively low, but in the subsequent manufacturing process, the first-type well region 12 is formed in the substrate 11, the doping type of the first-type well region 12 is the same as that of the first-type deep well 11, the concentration of the drift region can be increased to a certain extent, the breakdown voltage of the LDMOS device is slightly reduced within an acceptable range, and therefore the quasi-saturation phenomenon of a drain current-drain voltage curve is improved.
In order to control the breakdown voltage of the LDMOS device to be slightly reduced within an acceptable range and not influence the overall performance of the device, the opening size of the first-type well region is set to be 0.2um to 1 um. The specific value of the opening size of the first-type well region is determined according to the performance requirement of an actual device.
In one example, as shown in fig. 1, field oxide 20 is also disposed over the second-type well region 14, and the first-type heavily doped region 18 and the second-type heavily doped region 19 are separated by the field oxide 20.
An interlayer dielectric layer is arranged on the substrate of the LDMOS device, and a contact hole 21 is formed in the interlayer dielectric layer.
The first type heavily doped region, the second type heavily doped region and the grid structure are respectively led out through the contact holes.
The first type heavily doped region, the second type heavily doped region and the grid structure are respectively connected with the metal electrode 22 above the interlayer dielectric layer through the contact hole.
The gate structure 15 includes a gate oxide layer 152, a polysilicon gate 151, and gate spacers. A first type heavily doped region 16 in the first type deep well 12 is led out through a contact hole to be a drain electrode of the LDMOS device; the first type heavily doped region 18 and the second type heavily doped region 19 in the second type well region 14 are connected after being led out through the contact hole, and become a source electrode of the LDMOS device.
It should be noted that the field oxide 20 may not be disposed above the second-type well region 14, and the first-type heavily doped region 18 and the second-type heavily doped region 19 are connected.
In one example, the substrate is P-type, the first type deep well is N-type deep well, the first type well region is N-well, and the second type well region is P-well; the first type heavily doped region is of an N type, and the second type heavily doped region is of a P type.
In another example, the substrate is N-type, the first type deep well is P-type deep well, the first type well region is P-well, and the second type well region is N-well; the first type heavily doped region is of a P type, and the second type heavily doped region is of an N type.
Referring to fig. 2, a flowchart of a method for manufacturing an LDMOS device according to an embodiment of the present application is shown. The method at least comprises the following steps:
step 201, forming a first type deep well in a substrate.
As shown in fig. 3, a first-type deep well 12 is formed in a substrate 11.
Step 202, forming field oxygen on the substrate, wherein one end of the first-type deep well is positioned below the field oxygen.
As shown in fig. 4, a plurality of field oxides are formed on the surface of the substrate 11, and one end of the first-type deep well 12 is located below the field oxide 17; the field oxide 18 is located outside the first-type deep well 12.
Step 203, a first well region is formed in the substrate.
As shown in fig. 5, a first well region 13 is formed in the substrate 11, the first well region 13 is located outside the first deep well 12, and the doping type of the first well region 13 is the same as that of the first deep well 12.
The drift region is formed in the region where the first well region is located in the subsequent manufacturing process.
Step 204, forming a second-type well region in the substrate, wherein the first-type well region is located between the second-type well region and the first-type deep well.
As shown in fig. 6, a first-type deep well 12, a first-type well region 13, and a second-type well region 14 are formed in the substrate 11, the first-type well region 13 is located between the second-type well region 14 and the first-type deep well 12, and the first-type well region 13 is not connected to the second-type well region 14 and the first-type deep well 12.
And step 205, forming a gate structure, wherein one end of the gate structure extends to the surface of the field oxide above the first-type deep well, and the other end of the gate structure is located above the second-type well region.
As shown in fig. 7, one end of the gate structure 15 extends to the surface of the field oxide 17, and the other end of the gate structure 15 is located above one end of the second well-like region 14.
The gate structure 15 includes a gate oxide layer 152, a polysilicon gate 151 and a gate sidewall.
And step 206, forming a first type heavily doped region in the first type deep well, and forming a first type heavily doped region and a second type heavily doped region in the second type well region, wherein the first type heavily doped region in the first type deep well is separated from the gate structure by field oxygen.
As shown in fig. 8, a first type heavily doped region 16 is formed in the first type deep well 12, and a first type heavily doped region 18 and a second type heavily doped region 19 are formed in the second type well region 14; the field oxide 17 separates the gate structure 15 and the first type heavily doped region 16.
Because the thermal process exists in the manufacturing process of the LDMOS device, after the first-class deep well and the first-class well region are formed, the first-class deep well and the first-class well region can be diffused to the whole drift region through the thermal process, and because the first-class well region is added between the first-class deep well and the second-class well region, the concentration of the drift region can be increased to a certain extent, and the quasi-saturation phenomenon of the LDMOS device for improving a drain current-drain voltage curve is improved.
Another embodiment of the present application provides a method for manufacturing an LDMOS device, which at least includes the following steps:
step 301, providing a substrate, defining a first-class deep well region through a photolithography process, implanting doping ions into the substrate corresponding to the first-class deep well region through an ion implantation process, and performing thermal drive to form a first-class deep well in the substrate.
In one example, the substrate is a P-type substrate, and N-type ions are implanted into the substrate and subjected to a thermal drive-in process to form an N-type deep well.
And 302, forming field oxygen in the substrate, wherein one end of the first-type deep well is positioned below the field oxygen.
Optionally, the field oxygen region is opened by active region lithography, the field oxygen region is etched, and field oxygen is grown.
The top of one end of the first type deep well is provided with field oxygen, and the area outside the first type deep well is also provided with field oxygen.
Step 303, defining a first well region implantation region through a photolithography process.
Coating photoresist on the surface of the substrate, exposing through a mask plate with a first well region injection pattern, and defining a first well region injection region on the surface of the substrate after developing.
Optionally, when the first-type well region implantation region is defined, the opening size of the first-type well region implantation pattern is in a range from 0.2um to 1 um.
Step 304, implanting doping ions into the substrate corresponding to the first-type well region implantation region through an ion implantation process to form a first-type well region.
The first-type well region is positioned at the outer side of the first-type deep well, and the top of the first-type well region is free from field oxygen. The first-type well region is unconnected to the first-type deep well.
In one example, the first type well region is an N-well, an implantation region of the first type well region is opened by photolithography, and N-type doped ions are implanted to form the N-well, the N-well is located outside the N-type deep well, and the N-well is not connected to the N-type deep well.
Optionally, the opening size range of the first-type well region is 0.2um to 1 um.
Under the action of the thermal process of the subsequent process, the first-type deep well and the first-type well region diffuse to the whole drift region. Due to the small opening size of the first well region, the concentration of the drift region is not increased too much due to the existence of the first well region.
It should be noted that, when the first type well region is formed in the substrate, other regions with the same doping type may be formed simultaneously with the first type well region, and share the same reticle with the first type well region.
Step 305, a second-type well region is formed in the substrate, and the first-type well region is located between the second-type well region and the first-type deep well.
And determining a second type well region pattern through a photoetching process, and injecting doping ions into the substrate corresponding to the second type well region pattern through an ion injection process to form a second type well region.
The first well type region and the second well type region are different in doping type, and are not connected.
Optionally, the second-type well region is a P-well, the second-type well region injection region is opened by photolithography, P-type doped ions are injected, and the P-well is formed, and an N-well is present between the P-well and the N-type deep well.
In one example, the surface of the second-type well region is formed with well regions, and as shown in fig. 6, the surface of the second-type well region 14 is formed with field oxygen 20.
Step 306, forming a gate oxide layer.
Forming a gate oxide layer on the surface of the substrate.
Step 307, a polysilicon layer is formed.
And depositing a layer of polysilicon on the surface of the substrate to form a polysilicon layer.
And 308, forming a polysilicon gate through a photoetching process and an etching process, wherein one end of the polysilicon gate extends to the surface of the field oxide above the first deep well, and the other end of the polysilicon gate is positioned above the second-class well region.
Defining a polysilicon gate pattern by a photoetching process, and etching the polysilicon layer to form a polysilicon gate, as shown in fig. 7, wherein one end of the polysilicon gate 151 extends to the surface of the field oxide 17 above the first deep well 12, and the other end of the polysilicon gate 151 is located above the second well-like region 14; one end of the second well-like region 14 is covered by a polysilicon gate 151.
Step 309, forming gate spacers on both sides of the polysilicon gate.
And 310, forming a first type heavily doped region in the first type deep well, and forming a first type heavily doped region and a second type heavily doped region in the second type well region, wherein the first type heavily doped region of the first type deep well is separated from the gate structure by field oxygen.
Performing source-drain ion implantation, as shown in fig. 8, forming a first type heavily doped region 16 in the first type deep well 12, and forming a first type heavily doped region 18 and a second type heavily doped region 19 in the second type well region 14; the doping types of the first type heavily doped region and the second type heavily doped region are opposite; the first type heavily doped region 18 and the second type heavily doped region 19 formed in the second type well region 14 are separated by field oxide 20.
In one example, the substrate is P-type, the first type deep well is N-type deep well, the first type well region is N-well, the second type well region is P-well, the first type heavily doped region 16 and the first type heavily doped region 18 are N-type heavily doped regions, and the second type heavily doped region 19 is P-type heavily doped region.
In another example, the substrate is N-type, the first type deep well is P-type deep well, the first type well region is P-well, the second type well region is N-well, the first type heavily doped region 16 and the first type heavily doped region 18 are P-type heavily doped regions, and the second type heavily doped region 19 is N-type heavily doped region.
Step 311, an interlayer dielectric layer is formed.
And depositing an interlayer dielectric layer on the surface of the substrate.
In step 312, a contact hole is formed in the interlayer dielectric layer.
Contact holes are formed in the interlayer dielectric layer through photoetching and etching processes, and as shown in fig. 1, the first type heavily doped regions 16 and 18, the second type heavily doped region 19 and the polysilicon gate 15 are respectively led out through the contact holes 21.
And 313, forming a metal electrode on the surface of the interlayer dielectric layer, wherein the first type heavily doped region, the second type heavily doped region and the grid structure are respectively connected with the metal electrode through contact holes.
And forming a metal layer on the surface of the interlayer dielectric layer, and forming a metal electrode by photoetching and etching processes.
As shown in fig. 1, the first heavily doped region 16, the first heavily doped region 18, the second heavily doped region 19, and the gate structure 15 are respectively connected to the metal electrode 22 in the metal interconnection layer through the contact hole 21.
The first type heavily doped region 16 in the first type deep well 12 is led out and then is used as the drain electrode of the LDMOS device; the first heavily doped region 18 and the second heavily doped region 19 in the second well region 14 are connected after being led out and are used as a source electrode of the LDMOS device, and the polysilicon gate 151 is led out and is used as a gate electrode of the LDMOS device.
As shown in fig. 1, the first-type well region 14 added in the LDMOS device is located below the gate oxide 152, so that the concentration of the drift region below the gate oxide is increased, and because the opening size of the first-type well region 14 is small, the performance requirement of the device can be still met after the breakdown voltage is reduced, and meanwhile, the quasi-saturation phenomenon existing in the ID-VD (drain current-drain voltage) curve is improved.
In an example, an electrical test is performed on the LDMOS device shown in fig. 1 to obtain a drain current-drain voltage curve corresponding to the LDMOS device shown in fig. 1, as shown in fig. 9, the abscissa is the drain voltage v (drain) and the ordinate is the drain current i (drain). Fig. 10 shows a drain current-drain voltage curve diagram corresponding to the conventional LDMOS device, and comparing fig. 9 and fig. 10, it can be seen that the quasi-saturation phenomenon of the drain current-drain voltage curve of the LDMOS device provided by the embodiment of the present application is improved.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims (15)

1. The LDMOS device is characterized by comprising a substrate, a first-class deep well, a first-class well region and a second-class well region, wherein the first-class deep well, the first-class well region and the second-class well region are arranged in the substrate;
the first-type well region is positioned between the first-type deep well and the second-type well region;
one end of the first-type deep well is provided with a first-type heavily doped region;
the surface of the substrate is provided with a gate structure, the first well region is positioned below the gate structure, the gate structure is separated from a first heavily doped region in the first deep well through field oxygen, and one end of the gate structure extends to the surface of the field oxygen above the first deep well;
the other end of the grid structure is positioned above the second-type well region;
and a first type heavily doped region and a second type heavily doped region are arranged in the second type well region.
2. The LDMOS device set forth in claim 1, wherein said first well region has an opening size in the range of 0.2um to 1 um.
3. The LDMOS device of claim 1 or 2, wherein the first type heavily doped region and the second type heavily doped region in the second type well region are separated by field oxygen.
4. The LDMOS device of claim 1 or 2, wherein an interlayer dielectric layer is disposed on the substrate, and a contact hole is disposed in the interlayer dielectric layer;
the first heavily doped region, the second heavily doped region and the grid structure are respectively led out through the contact holes and are connected with the metal electrode above the interlayer dielectric layer.
5. The LDMOS device of claim 1 or 2, wherein the gate structure comprises a gate oxide layer, a polysilicon gate and a gate sidewall.
6. The LDMOS device of any one of claims 1 to 5, wherein the substrate is P-type, the first-type deep well is N-type deep well, the first-type well region is N-well, and the second-type well region is P-well.
7. The LDMOS device of any one of claims 1 to 5, wherein the substrate is N-type, the first-type deep well is a P-type deep well, the first-type well region is a P-well, and the second-type well region is an N-well.
8. A method of fabricating an LDMOS device, the method comprising:
forming a first type deep well in a substrate;
forming field oxygen on the substrate, wherein one end of the first-type deep well is positioned below the field oxygen;
forming a first well region in the substrate;
forming a second-type well region in the substrate, wherein the first-type well region is positioned between the second-type well region and the first-type deep well;
forming a grid structure, wherein one end of the grid structure extends to the surface of the field oxide above the first deep well, and the other end of the grid structure is positioned above the second-type well region;
and forming a first type heavily doped region in the first type deep well, and forming a first type heavily doped region and a second type heavily doped region in the second type well region, wherein the first type heavily doped region in the first type deep well is separated from the gate structure by field oxygen.
9. The method of claim 8, wherein forming a first well-like region in the substrate comprises:
defining a first type well region injection region through a photoetching process;
and injecting doping ions into the substrate corresponding to the first-class well region injection region through an ion injection process to form the first-class well region.
10. The method according to claim 8 or 9, wherein the opening size of the first well region is in a range of 0.2um to 1 um.
11. The method according to any of claims 8 to 10, wherein the surface of the second-type well region is formed with field oxide, and the first-type heavily doped region and the second-type heavily doped region are formed in the second-type well region and separated by the field oxide.
12. The method according to any one of claims 8 to 10, further comprising:
forming an interlayer dielectric layer;
forming a contact hole in the interlayer dielectric layer;
and forming a metal electrode on the surface of the interlayer dielectric layer, wherein the first heavy doping area, the second heavy doping area and the grid structure are respectively connected with the metal electrode through the contact hole.
13. The method of any of claims 8 to 10, wherein the forming a gate structure comprises:
forming a gate oxide layer;
forming a polysilicon layer;
forming a polysilicon gate through a photoetching process and an etching process, wherein one end of the polysilicon gate extends to the surface of the field oxide above the first deep well, and the other end of the polysilicon gate is positioned above the second-type well region;
and forming grid side walls on two sides of the polysilicon grid.
14. The method according to any of claims 8 to 13, wherein the substrate is P-type, the first type deep well is N-type deep well, the first type well region is N-well, and the second type well region is P-well.
15. The method according to any of claims 8 to 13, wherein the substrate is N-type, the first type deep well is P-type deep well, the first type well region is P-well, and the second type well region is N-well.
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