CN109950204A - A kind of stable high current metal-oxide-semiconductor - Google Patents
A kind of stable high current metal-oxide-semiconductor Download PDFInfo
- Publication number
- CN109950204A CN109950204A CN201910282623.5A CN201910282623A CN109950204A CN 109950204 A CN109950204 A CN 109950204A CN 201910282623 A CN201910282623 A CN 201910282623A CN 109950204 A CN109950204 A CN 109950204A
- Authority
- CN
- China
- Prior art keywords
- layer
- metal
- oxide
- trap
- injection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
The invention discloses a kind of stable high current metal-oxide-semiconductors, the preparation process is as follows: double traps, which are infused on silicon wafer, generates n trap and p trap, shallow-trench isolation is for being isolated silicon active area, by growing gate oxide, depositing polysilicon and marking obtain grid structure, LDD injects the shallow implant to form source-drain area, side wall is made in subsequent source, channel is protected in leakage injection, the source of medium energy, leakage injection, the junction depth of formation is greater than the injection depth of LDD, metal, which contacts, to be formed silicide contacts tungsten and silicon is closely linked, local interlinkage forms the first layer metal line between transistor and contact；The beneficial effects of the present invention are: making the high current metal-oxide-semiconductor operation of preparation more stable, there is good promotional value；Preparation is succinct, shortens the time-consuming of preparation, improves preparation efficiency.
Description
Technical field
The invention belongs to metal-oxide-semiconductor technical fields, and in particular to a kind of stable high current metal-oxide-semiconductor.
Background technique
Metal-oxide-semiconductor is metal, oxide, semiconductor field effect transistor, or claims to be metal-insulator, semiconductor.
Existing metal-oxide-semiconductor the problem of there is fluctuations of service.
Summary of the invention
The purpose of the present invention is to provide a kind of stable high current metal-oxide-semiconductors, to solve to mention in above-mentioned background technique
Existing metal-oxide-semiconductor out the problem of there is fluctuations of service.
To achieve the above object, the invention provides the following technical scheme: a kind of stable high current MOS pipe, described
Preparation process is as follows:
Step 1: double traps, which are infused on silicon wafer, generates n trap and p trap；
Step 2: shallow-trench isolation is for being isolated silicon active area；
Step 3: grid structure is obtained by growth gate oxide, depositing polysilicon and marking；
Step 4: LDD injects the shallow implant to form source-drain area；
Step 5: production side wall protects channel in subsequent source, leakage injection；
Step 6: the source of medium energy, leakage injection, the junction depth of formation are greater than the injection depth of LDD；
Step 7: metal, which contacts, to be formed silicide contacts tungsten and silicon is closely linked；
Step 8: local interlinkage forms the first layer metal line between transistor and contact；
Step 9: the deposit of first layer inter-level dielectric, and make the through-hole 1 of connection local interlinkage metal and first layer metal；
Step 10: the first layer metal for first time metal etch deposits metal sandwich structure and marks this layer of gold
Belong to；
Step 11: deposit second layer inter-level dielectric simultaneously makes through-hole 2；
Step 12: second layer metal through-hole 3 deposits second layer metal overlaying structure, and deposits and etch third layer interlayer
Medium；
Step 13: third layer metal to pressure point etches, alloying repeats these film-forming process until layer 5 metal pressure
Weldering deposit finishes, and is followed by the production of layer 6 inter-level dielectric and passivation layer；
Step 14: the reliability of each tube core on silicon wafer is verified in parameter testing.
As a preferred technical solution of the invention, the step of n trap formation: epitaxial growth, former oxidation growth,
First layer exposure mask, the injection of n trap, n trap injection (high energy), annealing.
As a preferred technical solution of the invention, the p trap formation the step of: second layer exposure mask, p trap injection,
P trap injects (high energy), annealing.
As a preferred technical solution of the invention, the step of the shallow-trench isolation: groove etched, oxide filling and
Oxide planarization.
As a preferred technical solution of the invention, the key step of the production through-hole 1: first layer inter-level dielectric
Oxide deposition (chemical vapor deposition), oxide grinding and polishing, the tenth layer of exposure mask, first layer inter-level dielectric etching.
Compared with prior art, the beneficial effects of the present invention are:
(1) make the high current metal-oxide-semiconductor operation of preparation more stable, there is good promotional value；
(2) preparation is succinct, shortens the time-consuming of preparation, improves preparation efficiency.
Detailed description of the invention
Fig. 1 is the formation structural schematic diagram of n trap of the invention；
Fig. 2 is the formation structural schematic diagram of p trap of the invention；
Fig. 3 is the groove etched structural schematic diagram of STL of the invention；
Fig. 4 is the silica-filled structural schematic diagram of STI of the invention；
Fig. 5 is the formation structural schematic diagram of STI of the invention；
Fig. 6 is polysilicon grating structure artwork of the invention；
Fig. 7 is n of the invention-LDD injecting structure schematic diagram；
Fig. 8 is p of the invention-LDD injecting structure schematic diagram；
Fig. 9 is n of the invention+S/D injecting structure schematic diagram；
Figure 10 is p of the invention+S/D injecting structure schematic diagram；
Figure 11 is the formation structural schematic diagram of contact of the invention；
Figure 12 is the LI silica structure schematic diagram of the medium as insertion LI metal of the invention；
Figure 13 is the formation structural schematic diagram of LI silica medium of the invention；
Figure 14 is the formation structural schematic diagram of LI metal of the invention；
Figure 15 is the formation structural schematic diagram of through-hole 1 of the invention；
Figure 16 is the formation structural schematic diagram of tungsten plug 1 of the invention；
Figure 17 is the formation structural schematic diagram that metal 1 of the invention interconnects；
Figure 18 is the formation structural schematic diagram of through-hole 2 of the invention；
Figure 19 is the formation structural schematic diagram of tungsten plug 2 of the invention；
Figure 20 is the formation structural schematic diagram that metal 2 of the invention interconnects；
Figure 21 is whole the schematic diagram of the section structure of the invention.
Specific embodiment
A kind of stable high current metal-oxide-semiconductor, the preparation process are as follows:
Step 1: double traps, which are infused on silicon wafer, generates n trap and p trap；The step of n trap formation: epitaxial growth, former oxidation life
Long, first layer exposure mask, the injection of n trap, n trap injection (high energy), annealing；The step of p trap formation: second layer exposure mask, the injection of p trap, p trap
Inject (high energy), annealing；
Step 2: shallow-trench isolation is for being isolated silicon active area；The step of shallow-trench isolation: groove etched, oxide filling and oxygen
Compound planarization；Wherein groove etched, silicon face grows about 150 angstroms of oxide layers of a layer thickness；It can be protected as separation layer active
From chemical spot during removing nitride, silicon face grows a thin layer silicon nitride since silicon nitride is firm covers in area
Membrane material helps to protect active area in sti oxide deposition process, the barrier material of polishing is served as in CMp；Exposure mask,
Shallow-trench isolation；The chemicals for the region ion and strong corrosive for not being photo-etched glue protection after by photoetching above
Matter etches away silicon nitride, silica and silicon, it should be noted that can help to mention in the inclined side wall of groove and round and smooth bottom surface
The electrology characteristic of highly filled quality and isolation structure；Oxide filling, silicon wafer clean and deoxygenate again the cleaning processes such as compound
Afterwards, the oxide layer for growing 150 angstroms under high temperature on the ditch non-intercommunicating cells lateral wall exposed to the open air, to prevent oxygen molecule from spreading to active area；Together
When oxygen pad layer also improve the interfacial characteristics between silicon and trench fill oxide；The filling of groove CVD oxide；Oxide planarization
Including chemically mechanical polishing and nitride removal；
Step 3: grid structure is obtained by growth gate oxide, depositing polysilicon and marking；Polysilicon grating structure makes base
This step 1: the growth of gate oxide washes the impurity of silicon wafer exposed to air contamination and the oxide layer of formation, into oxygen
Change furnace and grows a thin layer silica；Polysilicon grating structure makes basic step two: polycrystalline silicon deposit, silicon wafer, which is transferred to, is connected with silane
Low-pressure chemical vapor phase deposition equipment, silane decompose to silicon chip surface deposit one layer of polysilicon, later can to poly into
Row doping；Polysilicon grating structure makes basic step three: polysilicon photoetching, is marked in photoetching area using deep ultra violet photolithography
Polysilicon structure；Polysilicon grating structure makes basic step four: etching polysilicon, using incorgruous plasma note etching machine to shallow lake
Long-pending polysilicon performs etching, and obtains the polysilicon gate of vertical section；
Step 4: LDD injects the shallow implant to form source-drain area；Silicon wafer is marked, the photoetching offset plate figure of the area n- injection is obtained,
Its all region is photo-etched glue protection；Enter arsenic ion injection in the region for not being photo-etched glue protection, forms low energy shallow junction；
Silicon wafer is marked, the photoetching offset plate figure of the area p- injection is obtained, other all regions are photo-etched glue protection；Silicon wafer is marked, p- is obtained
The photoetching offset plate figure of area's injection, other all regions are photo-etched glue protection；
Step 5: production side wall protects channel in subsequent source, leakage injection；Large dosage of source and drain injection in order to prevent
Channel is got too close to so as to cause channel is too short or even source and drain connection, it will be the two of polysilicon gate after the LDD injection of CMOS
Side forms side wall, and the formation of side wall mainly has two steps: depositing layer of silicon dioxide using chemical vapor deposition device in thin film region；
Then carve this layer of silica using dry etch process, due to anisotropy used, lithography tool uses ion sputtering
The silica for having fallen the overwhelming majority, can stop the dioxy anti-carving, but at this moment not all after polysilicon exposes
SiClx all eliminates, and a part of silica is remained on the side wall of polysilicon, this step does not need exposure mask；
Step 6: the source of medium energy, leakage injection, the junction depth of formation are greater than the injection depth of LDD；That first to be carried out is n+
Source drain implant after making n-type transistor region by lithography, carries out the injection of median dose, and depth is greater than the junction depth of LDD, and dioxy
The side wall that SiClx is constituted prevents arsenic impurities to enter narrow channel region；Followed by p+ source drain implant, wanted having made by lithography
Same to carry out median dose injection behind the p-type transistor region injected, the junction depth that the junction depth ratio LDD of formation is formed is bigger,
Side wall has played same barrier effect, and the silicon wafer after injection is annealed in Quick annealing device, at high operating temperatures, for preventing
The extension and the diffusion of voltage input/drain impurity of structure are all extremely important；
Step 7: metal, which contacts, to be formed silicide contacts tungsten and silicon is closely linked；Contact hole forms work
The purpose of skill is the active area formation metal contact in all silicon, this layer of metal contacts the conduction material that can make silicon and then deposit
Material closely combines, and after the contamination of silicon chip surface and oxide are cleaned out, can utilize physical vapour deposition (PVD) (pVD)
One layer of metal is deposited in silicon chip surface, i.e., the argon ion bombardment metallic target charged in the cavity of a plasma releases gold
Belong to atom, it is made to be deposited on silicon chip surface, high annealing is carried out to silicon wafer later, metal and silicon form metal silication at high temperature
Object, finally chemically etches away the metal there is no reaction, and the silicide of metal has been stayed in silicon face；Titanium is to do gold
Belonging to the ideal material of contact, its resistance is very low, it can react to be formed TiSi2 (titanizing silicon) with silicon, and titanium and titanium dioxide
Silicon does not react, therefore the bonding of chemistry will not occur for both substances or object is then assembled, therefore titanium can be easily
It is removed from silica surface, without additional exposure mask., under the silicide of titanium remains on the surface of all active silicons
Come；
Step 8: local interlinkage forms the first layer metal line between transistor and contact；Contact hole forms rear next step just
Be transistor and other Titanium silicides contact between cloth metal contact wires, formed local interlinkage the step of with formed shallow slot every
From the step of it is equally complicated, technique require first deposit one layer of dielectric film, followed by chemically mechanical polishing, marking, etching
With tungsten Metal deposition, finally terminated with metal layer polishing, this technique is known as Damascus；The final result of this step process be
Silicon chip surface has obtained a kind of pattern similar to the set jewelry or the art work that refine；Form the step of local interlinkage silica medium
Rapid: silicon nitride chemical vapor deposition uses chemical vapor deposition method first to deposit one layer of silica as barrier layer, this layer of silicon nitride
Silicon active area is protected, is allowed to completely cut off with subsequent doping illuvium；The chemical vapor deposition of doping oxide is locally mutual
Link structure in local interlinkage medium composition be to be provided by the silica of chemical vapor deposition, two layers of silica phosphorus or
Boron lightdoped, impurity is introduced in silica can be improved next dielectric property, and subsequent short annealing can make stream of coming off duty
It is dynamic, obtain more flat surface；Utilize the oxide layer of CMP process planarization local interlinkage；9th layer of exposure mask,
Local interlinkage etching, silicon wafer are marked in photoetching area and are then etched in etched area, and narrow ditch is produced in the oxide layer of local interlinkage
Slot, these grooves define the Path form of local interlinkage metal；The step of making local interlinkage metal: Titanium deposits (pVD
Technique) for thin barrier layer Titanium liner in the bottom and side wall of local interlinkage channel, this layer of titanium acts as tungsten and dioxy
Adhesive between SiClx；Titanium nitride deposition, the diffusion barrier of tungsten is served as on the surface that titanium tungsten is deposited on titanium coating immediately
Layer；Tungsten deposit, tungsten fills up the groove of local interlinkage and covers silicon chip surface, why with tungsten rather than aluminium does local interlinkage gold
Category is because tungsten can form tungsten plug, it is the good grinding and polishing characteristic of tungsten that another original, which is gone through, without hole is filled emptyly；Grinding and polishing tungsten, tungsten
By grinding and polishing to the upper surface of local interlinkage dielectric layer；
Step 9: the deposit of first layer inter-level dielectric, and make the through-hole 1 of connection local interlinkage metal and first layer metal；
Step 10: the first layer metal for first time metal etch deposits metal sandwich structure and marks this layer of gold
Belong to；
Step 11: deposit second layer inter-level dielectric simultaneously makes through-hole 2；
Step 12: second layer metal through-hole 3 deposits second layer metal overlaying structure, and deposits and etch third layer interlayer
Medium；
Step 13: third layer metal to pressure point etches, alloying repeats these film-forming process until layer 5 metal pressure
Weldering deposit finishes, and is followed by the production of layer 6 inter-level dielectric and passivation layer；
Step 14: the reliability of each tube core on silicon wafer is verified in parameter testing.
It although an embodiment of the present invention has been shown and described, for the ordinary skill in the art, can be with
A variety of variations, modification, replacement can be carried out to these embodiments without departing from the principles and spirit of the present invention by understanding
And modification, the scope of the present invention is defined by the appended.
Claims (5)
1. a kind of stable high current metal-oxide-semiconductor, which is characterized in that the preparation process is as follows:
Step 1: double traps, which are infused on silicon wafer, generates n trap and p trap；
Step 2: shallow-trench isolation is for being isolated silicon active area；
Step 3: grid structure is obtained by growth gate oxide, depositing polysilicon and marking；
Step 4: LDD injects the shallow implant to form source-drain area；
Step 5: production side wall protects channel in subsequent source, leakage injection；
Step 6: the source of medium energy, leakage injection, the junction depth of formation are greater than the injection depth of LDD；
Step 7: metal, which contacts, to be formed silicide contacts tungsten and silicon is closely linked；
Step 8: local interlinkage forms the first layer metal line between transistor and contact；
Step 9: the deposit of first layer inter-level dielectric, and make the through-hole 1 of connection local interlinkage metal and first layer metal；
Step 10: the first layer metal for first time metal etch deposits metal sandwich structure and marks this layer of metal；
Step 11: deposit second layer inter-level dielectric simultaneously makes through-hole 2；
Step 12: second layer metal through-hole 3 deposits second layer metal overlaying structure, and deposits and etch third layer interlayer and be situated between
Matter；
Step 13: third layer metal to pressure point etches, alloying repeats these film-forming process until layer 5 metal pressure-welding forms sediment
Product finishes, and is followed by the production of layer 6 inter-level dielectric and passivation layer；
Step 14: the reliability of each tube core on silicon wafer is verified in parameter testing.
2. the stable high current metal-oxide-semiconductor of one kind according to claim 1, it is characterised in that: the step that the n trap is formed
It is rapid: epitaxial growth, former oxidation growth, first layer exposure mask, the injection of n trap, n trap injection (high energy), annealing.
3. the stable high current metal-oxide-semiconductor of one kind according to claim 1, it is characterised in that: the step that the p trap is formed
It is rapid: second layer exposure mask, the injection of p trap, p trap injection (high energy), annealing.
4. the stable high current metal-oxide-semiconductor of one kind according to claim 1, it is characterised in that: the shallow-trench isolation
Step: groove etched, oxide filling and oxide planarization.
5. the stable high current metal-oxide-semiconductor of one kind according to claim 1, it is characterised in that: the production through-hole 1
Key step: first layer inter-level dielectric oxide deposition (chemical vapor deposition), oxide grinding and polishing, the tenth layer of exposure mask, first layer
Inter-level dielectric etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910282623.5A CN109950204A (en) | 2019-04-10 | 2019-04-10 | A kind of stable high current metal-oxide-semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910282623.5A CN109950204A (en) | 2019-04-10 | 2019-04-10 | A kind of stable high current metal-oxide-semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109950204A true CN109950204A (en) | 2019-06-28 |
Family
ID=67014126
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910282623.5A Pending CN109950204A (en) | 2019-04-10 | 2019-04-10 | A kind of stable high current metal-oxide-semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109950204A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1070266A (en) * | 1996-08-26 | 1998-03-10 | Nec Corp | Semiconductor device and fabrication thereof |
| US20030022434A1 (en) * | 1998-12-25 | 2003-01-30 | Yasuhiro Taniguchi | Semiconductor integrated circuit device and a method of manufacturing the same |
| CN102054839A (en) * | 2009-10-28 | 2011-05-11 | 无锡华润上华半导体有限公司 | Metal oxide semiconductor (MOS) field effect transistor (FET) structure and preparation method thereof |
| CN103632942A (en) * | 2012-08-24 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | SONOS device and LDMOS device integration method in CMOS process |
-
2019
- 2019-04-10 CN CN201910282623.5A patent/CN109950204A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1070266A (en) * | 1996-08-26 | 1998-03-10 | Nec Corp | Semiconductor device and fabrication thereof |
| US20030022434A1 (en) * | 1998-12-25 | 2003-01-30 | Yasuhiro Taniguchi | Semiconductor integrated circuit device and a method of manufacturing the same |
| CN102054839A (en) * | 2009-10-28 | 2011-05-11 | 无锡华润上华半导体有限公司 | Metal oxide semiconductor (MOS) field effect transistor (FET) structure and preparation method thereof |
| CN103632942A (en) * | 2012-08-24 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | SONOS device and LDMOS device integration method in CMOS process |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8247262B2 (en) | Method for reducing contact resistance of CMOS image sensor | |
| KR101656136B1 (en) | Contact etch stop layers of a field effect transistor | |
| US6337262B1 (en) | Self aligned T-top gate process integration | |
| CN100442464C (en) | Semiconductor device fabrication method | |
| TWI220301B (en) | Method for manufacturing embedded non-volatile memory with two polysilicon layers | |
| KR19980032299A (en) | Metal oxide semiconductor field effect transistor device and manufacturing method thereof | |
| CN102347361A (en) | Field effect transistor and manufacture method thereof | |
| CN102074479B (en) | Semiconductor device and production method thereof | |
| US7785974B2 (en) | Methods of employing a thin oxide mask for high dose implants | |
| US6107096A (en) | Method of fabricating a salicide-structured MOS semiconductor device having a cobalt disilicied film | |
| JPH07263680A (en) | Manufacture of semiconductor device | |
| TWI613816B (en) | Semiconductor device and methods for forming the same | |
| CN102148198A (en) | Method for fabricating integrated circuit and gate structure | |
| JP3524461B2 (en) | Process for fabricating a dual gate structure for a CMOS device | |
| CN104425247B (en) | A kind of preparation method of insulated gate bipolar transistor | |
| CN109950204A (en) | A kind of stable high current metal-oxide-semiconductor | |
| KR100962020B1 (en) | Fabrication Method of Phase-Change Memory Device | |
| CN102856178B (en) | The formation method of metal gates and MOS transistor | |
| CN102054769B (en) | Forming method of complementary metal oxide semiconductor (CMOS) structure | |
| KR20060033781A (en) | Ultra-uniform silicides in integrated circuit technology | |
| KR20020037942A (en) | Method for manufacturing gate in semiconductor device | |
| KR100880336B1 (en) | Method for manufacturing a semiconductor device | |
| US6674135B1 (en) | Semiconductor structure having elevated salicided source/drain regions and metal gate electrode on nitride/oxide dielectric | |
| CN108346698A (en) | A kind of manufacturing method of semiconductor devices | |
| CN107706110A (en) | The manufacture method of FinFET |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190628 |