KR100962020B1 - Fabrication Method of Phase-Change Memory Device - Google Patents

Abstract

A method of manufacturing a phase change memory device capable of improving the reliability of a diode forming process in a phase change memory device is provided.

The method of manufacturing a phase change memory device according to the present invention includes defining a cell region and a core region in a semiconductor substrate, forming a junction region in a semiconductor substrate of the cell region, and forming a stacked structure for a gate oxide film and a gate stack on the semiconductor substrate. Exposing the semiconductor substrate of the cell region, forming a Selective Epitaxial Growth (SEG) layer on the cell region, and patterning the SEG layer, wherein the SEG layer is incompletely formed. Can be prevented.

PRAM, Diode

Description

Fabrication Method of Phase-Change Memory Device

The present invention relates to a phase change memory device, and more particularly to a method of manufacturing a phase change memory device that can improve the reliability of the diode forming process in a phase change memory device using a diode as a switching device.

Phase-change random access memory (PRAM) is a memory device that records and reads information by a phase change of a phase change material having a high resistance in an amorphous state and a low resistance in a crystalline state. Compared with the above-mentioned method, it has the advantage of having a high operation speed and high integration, and forms a cell by applying a diode as a switching element to improve the integration.

1 is a cross-sectional view of a device for explaining a diode forming process in a general phase change memory device.

As shown, the device isolation film 103 is formed on the semiconductor substrate 101 to separate the core region from the cell region, and ions are implanted into the cell region to form the junction region 105.

Thereafter, the gate stack 107 is formed in the core region, and the interlayer insulating layer 115 is formed on the entire structure including the core region and the cell region. Then, a contact hole for forming a diode is formed by removing the designated portion of the interlayer insulating film 115 formed in the cell region.

Here, the gate stack 107 may be formed of a polyside structure, for example, a stacked structure of a hard mask nitride film (HM Nit) / metal silicide (eg, WSix) / polysilicon layer. In addition, spacers 109 are formed on both sidewalls of the gate stack 107, and first and second dielectric layers 111 and 113 are sequentially formed as diffusion barrier layers on the entire structure. The interlayer insulating film 115 is generally made of an oxide film.

On the other hand, after forming the contact hole, the SEG layer 117 is formed in the contact hole by a selective epitaxial growth (SEG) process.

However, at present, since the SEG layer 117 is grown in the contact hole, the particle 119 generated during the SEG layer forming process may block the contact hole before the SEG layer 117 is completely formed, and thus the SEG layer 117 does not grow to the desired height.

In addition, since the selectivity is changed during the SEG layer 117 forming process, silicon may grow on the interlayer insulating layer 115. In addition, the abnormal silicon layer 121 blocks the contact hole, which hinders the growth of the SEG layer 117, thereby lowering the production yield of the PRAM device.

The present invention has been made to solve the above problems and disadvantages, and provides a method for manufacturing a phase change memory device that can improve the growth characteristics of the SEG layer by forming a SEG layer for use as a diode patterning method There is a technical problem.

Another technical problem of the present invention is to provide a method of manufacturing a phase change memory device capable of increasing the SEG layer formation speed by forming a diode by growing and patterning an SEG layer over the entire cell region.

According to an aspect of the present invention, there is provided a method of fabricating a phase change memory device, the method including: defining a cell region and a core region in a semiconductor substrate, and forming a junction region in the semiconductor substrate of the cell region; Forming a stacked structure for a gate oxide film and a gate stack on the semiconductor substrate; Exposing a semiconductor substrate in the cell region; Forming a selective epitaxial growth (SEG) layer on the cell region; And patterning the SEG layer.

According to the present invention, the SEG layer can be grown at a high speed by forming and patterning the SEG layer over the entire cell region in manufacturing the phase change memory device, thereby shortening the device manufacturing time.

In addition, it is possible to prevent the SEG layer from being incompletely formed, thereby improving the production yield of the device and improving the operating characteristics of the diode.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2A to 2G are cross-sectional views illustrating a method of manufacturing a phase change memory device according to an embodiment of the present invention.

First, as shown in FIG. 2A, an isolation layer 203 is formed on a semiconductor substrate 201 to define a core region and a cell region, and then an junction region 205 is formed by performing an ion implantation process on the cell region. .

A gate oxide film 207 is formed over the entire structure, and a stacked structure for forming a gate stack, that is, a polysilicon layer 209, a metal silicide (for example, WSix) layer 211, and a hard mask nitride film (HM) is formed. Nit) 213 is formed sequentially.

Here, the gate oxide film 207 using the _{700 ~ 900 ℃ H 2/0} 2 gas at a temperature, can be formed to a thickness of 30 ~ 60Å through the dry or how wet oxidation or radical (Radical) oxidation .

In addition, the polysilicon layer 209 may be formed to a thickness of 700 ~ 1000 kPa using SiH ₄ and PH ₃ gas of 0.5 ~ 1.0 Torr at a temperature of 450 ~ 600 ℃, the metal silicide layer 211 is 350 ~ It can be formed to a thickness of 900 ~ 1200Å using WF ₆ and SiH ₄ (or SiH ₂ Cl ₂ ) of 0.5 ~ 1.0 Torr at a temperature of 500 ℃, hard mask nitride film 213 at a temperature of 400 ~ 600 ℃ SiH ₄ and NH ₃ can be used to form a thickness of 1000 to 1500 kPa.

Next, a mask (not shown) is formed in the core region, and the hard mask nitride film 213, the metal silicide layer 211, the polysilicon layer 209, and the gate oxide film 207, which are stacked structures for gate stacks in the cell region, are formed. By etching, the semiconductor substrate 201 in the cell region is exposed as shown in FIG. 2B.

Thereafter, as shown in FIG. 2C, the SEG layer 215 is grown on the cell region. At this time, it is preferable that the cleaning process is preceded to remove the natural oxide film of the cell region.

SEG layer 215 may be formed using any one of Si ₂ H ₆ , SiH ₂ Cl ₂ , SiH ₄ as a source gas at a temperature of 600 ~ 1000 ℃ and a pressure of 0.5 ~ 400 Torr, the growth thickness is 3000 ~ It is preferable to set it as 5000 Hz.

In addition, the SEG layer 215 may be formed of a doped SEG layer. In this case, the concentration of phosphorus (P) ion used as an impurity is preferably 2.0 to 5.0 E20 atoms / cc.

In the present invention, since the SEG layer 215 is formed in the entire cell region, the growth rate can be shortened because the SEG layer 215 is grown in a wider range than the conventional method of forming the SEG layer in the contact hole.

After the SEG layer 215 is formed over the entire cell region, as shown in FIG. 2D, a photo-etching process using a mask is performed, leaving only the SEG layer pattern 215A for use as a diode. The SEG layer 215 is removed.

In this case, a patterning process may be simultaneously performed by applying a mask for forming a gate stack in the core region. Accordingly, the gate stack may be formed in the core region while forming the SEG layer pattern 215A in the cell region. . In addition, a low concentration ion implantation process may be performed without removing the mask used for forming the SEG layer pattern 215A and the mask for forming the gate stack.

In addition, the gate stack may be patterned before or after the SEG layer pattern 215A forming process.

After the SEG layer pattern 215A is formed, the PN impurities are doped to complete formation of the PN diode 215B as shown in FIG. 2E.

Thereafter, as shown in FIG. 2F, an insulating material is formed on the entire structure, and spacers 217 are formed on both sidewalls of the SEG layer pattern 215A and the gate stack by an anisotropic etching process using a spacer mask. A high concentration ion implantation process is performed while the spacer mask is held to form the ion implantation region 219 to be used as a source and a drain. At this time, since the concentration of ions implanted in the ion implantation region 219 is lower than the concentration of the junction region 205 formed in the cell region, the influence applied to the junction region 205 by the ion implantation process can be excluded. have.

As shown in FIG. 2G, the interlayer insulating film 221 is formed on the entire structure, and then the planarization process is performed to remove the spacer mask on the cell region and the core region, thereby removing the SEG layer pattern 215A and the gate stack. Expose the surface.

Although not shown, a process of forming a metal silicide layer on the SEG layer pattern 215A, a bottom electrode contact (BEC) and a bottom electrode, and forming a phase change material layer and an upper electrode after the planarization process may be performed. do.

Those skilled in the art to which the present invention described above belongs will understand that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

In the present invention, the SEG layer to be used as the PN diode can be prevented from being incompletely grown, and the production yield of the device can be improved. In addition, the growth rate can be improved because the SEG layer is grown over a wide range.

Therefore, according to the present invention, it is possible to manufacture a reliable phase change memory device at high speed.

1 is a cross-sectional view of a device for explaining a diode forming process in a general phase change memory device;

2A to 2G are cross-sectional views illustrating a method of manufacturing a phase change memory device according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

201: semiconductor substrate 203: device isolation film

205 junction region 207 gate oxide film

209 polysilicon layer 211 metal silicide layer

213: hard mask nitride film 215: SEG layer

215A: SEG layer pattern 215B: PN diode

217 spacer 219 ion implantation region

221: interlayer insulating film

Claims (10)

As a phase change memory device manufacturing method, Defining a cell region and a core region in the semiconductor substrate, and forming a junction region in the semiconductor substrate of the cell region; Forming a stacked structure for a gate oxide film and a gate stack on the semiconductor substrate; Exposing a semiconductor substrate in the cell region; Forming a selective epitaxial growth (SEG) layer on the cell region; And Patterning the SEG layer; Phase change memory device manufacturing method comprising a. The method of claim 1, And patterning the stack structure for the gate stack simultaneously with patterning the SEG layer. The method of claim 1, And patterning the stack structure for the gate stack before or after patterning the SEG layer. The method of claim 1, The SEG layer is formed in a phase change memory device, characterized in that formed at a temperature of 600 ~ 1000 ℃ and a pressure of 0.5 ~ 400 Torr. The method according to claim 1 or 4, The SEG layer is formed by using any one of Si ₂ H ₆ , SiH ₂ Cl ₂ , SiH ₄ as a source gas. The method according to claim 1 or 4, The SEG layer is a phase change memory device manufacturing method characterized in that formed to a thickness of 3000 ~ 5000Å. The method of claim 1, And the SEG layer is a doped SEG layer. The method of claim 7, wherein The doped SEG layer is formed using a phosphorus (P) ion of 2.0 to 5.0 E20 atoms / cc. The method of claim 1, And exposing the semiconductor substrate of the cell region, and then performing a cleaning process before forming the SEG layer. The method of claim 1, And forming a PN diode by doping P-type impurities after forming the SEG layer pattern.

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