KR101124340B1 - Phase-Change Memory Device and Fabrication Method Thereof - Google Patents

Abstract

A method of manufacturing a phase change memory device using a PN diode, the method comprising: providing a semiconductor substrate in which a cell region in which an impurity region is formed and a core region in which a gate stack is formed is provided, and an entire structure including a gate oxide film formed in the cell region when a gate stack is formed Forming an interlayer insulating film on the substrate, and forming an interlayer insulating film using a material having an etching speed lower than that of the gate oxide film under the same etching conditions; and etching the designated region of the interlayer insulating film and the gate oxide film formed in the cell region once The present invention provides a method of manufacturing a phase change memory device, the method including forming a contact hole by removing the contact hole and forming a PN diode in the contact hole.

Description

Phase Change Memory Device and Fabrication Method Thereof

The present invention relates to a phase change memory device, and more particularly, a phase change memory device capable of reducing a driving current while minimizing the size of a contact hole for forming a PN diode in a phase change memory device using a PN diode and a method of manufacturing the same. It is about.

Currently used memory devices are DRAM, SRAM, and flash memory. While DRAM has the advantage of low cost and random access, it has the disadvantage of volatile memory, and SRAM used as cache memory has the advantage of random access and speed, but it is not only volatile but also large in size There is a limit to this high. In addition, the flash memory is a nonvolatile memory, which is advantageous in cost, power consumption, etc., but has a disadvantage of slow operation speed.

A memory device developed to overcome the drawbacks of such memory devices is a phase-change random access memory (PRAM).

PRAM is a memory device that records and reads information by a phase change of a phase change material having a high resistance in an amorphous state and a low resistance in a crystalline state, and has an advantage of having a faster operation speed and a higher density than a flash memory. In recent years, a cell is formed using a diode structure to improve the degree of integration.

1 is a schematic cross-sectional view of a general phase change memory device.

As shown, the device isolation film 12 is formed in the semiconductor substrate 10 to separate the core region from the cell region, and ions are implanted into the cell region to form a line type junction region 14.

Thereafter, the gate stack 16 is formed in the core region, and the interlayer insulating layer 24 is formed on the entire structure including the core region and the cell region. Then, the contact hole 26 for forming the PN diode is formed by removing the designated portion of the interlayer insulating film 25 in the cell region.

Here, the gate stack 16 may be formed of a polyside structure, for example, a stacked structure of a hard mask nitride film (HM Nit) / metal silicide (eg, WSix) / polysilicon layer. In addition, spacers 18 are formed on both side walls of the gate stack 16, and an oxide film 20 and a nitride film 22 are sequentially formed as a diffusion barrier on the entire structure. The insulating film 24 is generally made of an oxide film.

On the other hand, after the contact hole 26 is formed, a PN diode (not shown) is formed in the contact hole 26 by a selective epitaxial growth process.

In such a PRAM manufacturing process, a smaller size of the contact hole 26 is required for high integration of the device, and thus, after the mask and etching process for forming the contact hole 26, the upper aperture of the interlayer insulating film 24 ( The phenomenon that the lower aperture D2 becomes smaller than D1) occurs. That is, the interlayer insulating film 24 formed in the junction region 14 is formed relatively thick with a thickness of several thousand micrometers, and the amount of etching gas reached toward the lower portion of the interlayer insulating film 24 is reduced, and the interlayer insulating film 24 Since the oxide film used as the oxide film 20 and the oxide film 20 on the upper portion of the junction region 14 have similar etching selectivity, the etching rate decreases toward the bottom of the contact hole, and is actually lower than the critical dimension of the upper surface of the etching target layer. The aperture will be as small as 80%.

As a result, the contact area between the PN diode and the semiconductor substrate 10 formed in the subsequent process is reduced, thereby increasing the resistance, and as a result, the operating current decreases, thereby requiring a large amount of driving current. In addition, as the device is highly integrated, the gap between the PN diodes is reduced, and when the resistance of the bottom surface of the PN diode is increased, there is a problem in that the device malfunctions due to interference with adjacent diodes.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems and disadvantages, and the phase change memory device capable of increasing the size of the bottom of the contact hole by causing a notch phenomenon at the bottom of the contact hole for forming a PN diode and its There is a technical problem in providing a manufacturing method.

Another technical problem of the present invention is to increase the contact area between the PN diode and the semiconductor substrate so as to reduce the driving current of the phase change memory device.

The method of manufacturing a phase change memory device according to an embodiment of the present invention for achieving the above technical problem is a method of manufacturing a phase change memory device using a PN diode, wherein a cell region having an impurity region and a core region having a gate stack are defined. Providing a semiconductor substrate; When the gate stack is formed, an interlayer insulating film is formed on the entire structure including the gate oxide film formed in the cell region, and the interlayer insulating film is formed by using a material having an etching rate lower than that of the gate oxide film under the same etching conditions. step; Forming a contact hole by removing the designated regions of the interlayer insulating layer and the gate oxide layer formed in the cell region by one etching process; And forming a PN diode in the contact hole.

According to the present invention, it is possible to reduce the interface resistance by increasing the contact area between the PN diode and the semiconductor substrate while minimizing the size of the contact hole for forming the PN diode in the phase change memory device.

Accordingly, there is an advantage that the device can be stably operated while realizing high integration by maximizing the operating current of the device while applying a low driving current.

Further, in the present invention, a gate oxide film that is necessarily formed in the cell region is used as the dielectric layer when forming the gate stack. Therefore, it is not necessary to separately proceed with the deposition process for forming the dielectric layer, the planarization process accompanying it, and the like. As a result, in inducing notches at the bottom of the contact hole by using the difference in the etching selectivity between the interlayer insulating layer and the dielectric layer thereunder, the contact hole is formed by one etching process and a separate dielectric layer forming process is not necessary. The process process can be significantly reduced.

1 is a schematic cross-sectional view of a general phase change memory device;
2A through 2D are cross-sectional views sequentially illustrating a method of manufacturing a phase change memory device according to an embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2A to 2D are cross-sectional views illustrating a method of manufacturing a phase change memory device according to an embodiment of the present invention, and show only a cell region defined by an isolation layer.

First, as shown in FIG. 2A, an isolation layer 102 is formed in the semiconductor substrate 100, and impurities are implanted into the cell region by an ion implantation process to form a junction region 104, that is, an impurity region. The first dielectric layer 106 and the second dielectric layer 108 are sequentially formed on the entire structure.

Here, the first dielectric layer 106 may be a thermal oxide film formed of a gate oxide film or a diffusion barrier film that is necessarily formed when the gate stack is manufactured in the core region. In addition, the second dielectric layer 108 may be a nitride film formed of a diffusion barrier and may be omitted in some cases.

Next, as shown in Fig. 2B, an interlayer insulating film 110 is formed over the entire structure. In this case, the interlayer insulating layer 110 may be formed using a material having a lower etching selectivity than that of the first dielectric layer 106. Preferably, the interlayer insulating layer 110 may be a nitride layer. That is, the interlayer insulating layer 110 may be formed using a material having an etching rate lower than that of the first dielectric layer 106 under the same etching conditions, and may be formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD). It can be formed to a thickness of 4000 to 8000 kPa.

As illustrated in FIG. 2C, the contact hole 112 is formed by performing a mask and etching process to expose the PN diode formation region of the junction region 104. In this case, the notch A is generated at the bottom of the contact hole 112 because the etch selectivity of the interlayer insulating layer 110 is lower than that of the first dielectric layer 106.

Here, the amount of loss of the bottom of the contact hole 112 due to the excessive etching during the mask and etching process for forming the contact hole 112 is less than 30 kW, preferably 1 to 30 kW. In addition, the aperture of the bottom of the contact hole 112 after the mask and etching process is 101 to 120% of the upper aperture, for example, when the upper aperture is 110nm, the aperture of the bottom becomes 111 to 130nm.

After the mask and the etching process, a cleaning process may be performed, and the cleaning process may include a first cleaning liquid (B), a second cleaning liquid (O), a third cleaning liquid (N), or a combination thereof, which has an excellent selectivity to an oxide film. 10 seconds to 10 minutes using BN or BON, or 10 seconds to 10 minutes using a cleaning liquid mixed with hydrogen fluoride (HF) and pure water. In addition, the cleaning process may be performed for 10 to 50 seconds with LET (Light Etch Treatment).

Herein, the first cleaning solution is a cleaning solution containing sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ) in a ratio of 4: 1, and the second cleaning solution is ammonium fluoride (NH ₄ F) and hydrogen fluoride (HF). ) Is a BOE (Buffered Oxide Etchant) solution with a ratio of 20: 1 to 300: 1, and the third cleaning solution has a ratio of 1: 4 of ammonium hydroxide (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ), and pure water. Mean solution of 20.

Moreover, as for the washing | cleaning liquid which mixed hydrogen fluoride and pure water, it is preferable to make ratio of pure water: hydrogen fluoride 40: 1-200: 1.

Thereafter, as illustrated in FIG. 2D, the PN diode 114 is formed in the contact hole 112 by a selective epitaxial growth process. As can be seen in the figure, the contact area between the bottom of the PN diode 114 and the junction region 104 increases, resulting in a decrease in resistance, resulting in an increase in operating current.

Although not shown, a BEC is formed after the PN diode 114 is formed, and the phase change memory device is manufactured by forming a phase change material layer, an upper electrode, a word line, and a bit line.

The phase change memory device manufactured by the above method is a phase change memory device including a semiconductor substrate having a junction region, a PN diode formed on the junction region, and a lower electrode contact contacting the PN diode. The aperture is formed to be equal to or larger than the upper aperture. In addition, the phase change memory device according to the present invention further includes a dielectric layer sequentially stacked on both sides of the PN diode and an interlayer insulating layer having an etching selectivity lower than that of the dielectric layer.

In the present invention, when the gate stack is formed in the core region, a gate oxide film necessarily formed in the cell region is used as the dielectric layer. By using the difference in etching selectivity between the gate oxide film and the nitride film used as the interlayer insulating film, the contact area between the PN diode and the semiconductor substrate is increased by causing a notch in the bottom of the contact hole for forming the PN diode after the etching and cleaning process. This can maximize the operating current of the device.

In addition, since the gate oxide film is inevitably formed when the gate stack is formed of a dielectric layer having a different etching selectivity from the interlayer insulating film, a notch may be caused in the bottom of the contact hole without performing a process of separately depositing the dielectric layer and the subsequent planarization process. Can be.

Those skilled in the art to which the present invention described above belongs will understand that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

100: semiconductor substrate
102: device isolation film
104: active area
106: the first dielectric layer
108: second dielectric layer
110: interlayer insulating film
112: contact hall
114: PN diode

Claims (12)

A method of manufacturing a phase change memory device using a PN diode,
Providing a semiconductor substrate defining a cell region in which an impurity region is formed and a core region in which a gate stack is formed;
An interlayer insulating film is formed on the entire structure including a gate oxide film formed in the cell region when the gate stack is formed and a nitride film as a diffusion barrier formed on the gate oxide film of the cell region when the gate stack is formed, under the same etching conditions. Forming the interlayer insulating layer using a material having an etch rate lower than that of the gate oxide layer;
Forming a contact hole by removing the designated regions of the interlayer insulating layer and the gate oxide layer formed in the cell region by one etching process; And
Forming a PN diode in the contact hole;
Phase change memory device manufacturing method comprising a. delete The method of claim 1,
And the interlayer insulating film is a nitride film. The method of claim 1,
And said interlayer insulating film is formed to a thickness of 4000 to 8000 Å. The method of claim 1,
The loss amount of the impurity region during the formation of the contact hole is 1 to 30 GPa, characterized in that the manufacturing method of the phase change memory device. The method of claim 1,
And the aperture of the bottom of the contact hole is 101 to 120% of the aperture of the upper portion of the contact hole. The method of claim 1,
And after the forming of the contact hole, performing a cleaning process. The method of claim 7, wherein
The cleaning process is a method of manufacturing a phase change memory device, characterized in that performed using a cleaning solution containing sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ) in a ratio of 4: 1. The method of claim 7, wherein
The cleaning process is performed by using a BOE (Buffered Oxide Etchant) solution in which ammonium fluoride (NH ₄ F) and hydrogen fluoride (HF) are mixed at a ratio of 20: 1 to 300: 1. Manufacturing method. The method of claim 7, wherein
The cleaning process is a method of manufacturing a phase change memory device, characterized in that performed using a solution of a ratio of 1: 4: 20 ammonium hydroxide (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ) and pure water. The method of claim 7, wherein
The cleaning process is a method of manufacturing a phase change memory device, characterized in that performed using a solution of the ratio of pure water and hydrogen fluoride 40: 1 ~ 200: 1. The method of claim 7, wherein
The cleaning process is a method of manufacturing a phase change memory device, characterized in that performed for 10 to 50 seconds by LET (Light Etch Treatment).

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