CN202159671U - High-pressure metal oxide semiconductor (MOS) transistor structure in Bipolar CMOS DMOS (BCD) technology - Google Patents
High-pressure metal oxide semiconductor (MOS) transistor structure in Bipolar CMOS DMOS (BCD) technology Download PDFInfo
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Abstract
The utility model provides a high-pressure metal oxide semiconductor (MOS) transistor structure in Bipolar CMOS DMOS (BCD) technology, which comprises a first mixing type semiconductor substrate, a second mixing type embedding layer arranged in the semiconductor substrate, a second mixing type semiconductor layer covering the semiconductor substrate and the embedding layer, a first mixing type pit, a second mixing type pit, a field oxidation layer arranged in the first mixing type pit, a grating medium layer covering the semiconductor layer, gate electrodes arranged on the grating medium layer and the field oxidation layer, a source area arranged in the second mixing type pit on a first side of the grate electrodes, and a leakage area arranged in the first mixing type pit on a second side of the grate electrodes. The first mixing type pit and the second mixing type pit are arranged in the semiconductor layer side by side. The high-pressure MOS transistor structure is compatible with the BCD technology, and the problem that mixing density is low due to adsorption of P type ions by the field oxidation layer is avoided.
Description
Technical field
The utility model relates to the BCD semiconductor process techniques, relates in particular to the high-voltage MOS transistor structure in a kind of BCD technology.
Background technology
BCD technology is a kind of monolithic integrated technique technology, and this technology can be made Bipolar, CMOS and DMOS device on same chip, abbreviate BCD technology as.Since the BCD process synthesis above three kinds of devices advantages separately, this makes BCD technology become the main flow technology of integrated circuit.
BCD technology can select different devices to reach the optimization of corresponding electronic circuit device for different circuits, realizes the low-power consumption, high integration of entire circuit, the requirement of high-speed, high driving ability.BCD technology is the excellent selection of IC manufacturing process such as power management, display driver, automotive electronics, has vast market prospect.It is not high that but the MOS transistor in the BCD technology is withstand voltage, and this has just limited the application space of BCD technology in some fields.
Publication number is to disclose a kind of PMOS transistor and forming method thereof in the Chinese patent document of CN101111942A; Fig. 1 shows the transistorized sectional structure chart of this PMOS; It is the basis with the silicon substrate that the P type mixes; Be formed with the following epitaxial loayer (being n type buried layer NBL) of N type above that, be formed with on the n type buried layer NBL P type on epitaxial loayer, on the P type, form the N trap afterwards in the part of epitaxial loayer; Epitaxial loayer drifts about as P on another part P type that keeps, and forms field oxide 100, gate dielectric layer 101, gate electrode G, source S and drain D afterwards again.In addition, in the disclosed PMOS transistor arrangement, between N trap and n type buried layer NBL, also be formed with p type buried layer PBL.
But there is following problem in the compatibility of above method and BCD technology: 1, said PMOS transistor, and it does n type buried layer earlier; And then in n type buried layer, do p type buried layer, then the p type buried layer zone needs and should form after the n type buried layer transoid in zone, needs higher dosage when p type buried layer forms; In BCD technology, if p type buried layer dosage is higher, auto-doping phenomenon can appear in time-delay outside; And p type buried layer dosage is high more; Auto-doping phenomenon is obvious more, and this phenomenon can cause the extension CONCENTRATION DISTRIBUTION unusual, causes device parameters unusual then; 2, said PMOS transistor, epitaxial loayer on the P type is used in its P drift region, if said PMOS transistor is used for BCD technology; Because of the concentration of epitaxial loayer in the BCD technology lower; Then the concentration of P drift region is lower, when carrying out the field oxide growth, because of " inhaling boron row phosphorus " effect of oxide layer; Below the field oxide of P drift region, be easy to form N type inversion layer, cause component failure.Said above method and BCD technology compatible relatively poor can not well be applied in the BCD technology.
The utility model content
The technical problem that the utility model will solve provides the high-voltage MOS transistor structure in a kind of BCD technology, and its forming process is compatible mutually with BCD technology, and can tolerate higher voltage.
For solving the problems of the technologies described above, the utility model provides the high-voltage MOS transistor structure in a kind of BCD technology, comprising:
The Semiconductor substrate of first doping type;
The buried regions of second doping type is arranged in Semiconductor substrate;
The semiconductor layer of second doping type covers said Semiconductor substrate and buried regions, and said second doping type is opposite with said first doping type;
The trap of the trap of first doping type and second doping type is arranged in said semiconductor layer side by side;
Field oxide is between the trap of the trap of the trap of the trap of said first doping type, second doping type, first doping type and second doping type;
Gate dielectric layer covers said semiconductor layer;
Gate electrode is positioned on said gate dielectric layer and the field oxide, and said gate electrode has the first relative side and second side, and wherein first side extends on the gate dielectric layer of trap top of said second doping type, and second side extends on the said field oxide;
The source region is arranged in the trap of second doping type of said gate electrode first side;
The drain region is arranged in the trap of first doping type of said gate electrode second side.
Alternatively, said first doping type is the P type, and second doping type is the N type, and the length of said field oxide is 2 to 6 μ m, and said length is along the direction in said source region to drain region.
Alternatively; Said first doping type is the P type; Second doping type is the N type, and said field oxide has first side and second side, and first side of said field oxide is positioned at said gate electrode below; Second side is near said drain region, and the distance that first side of said field oxide and the trap of said second doping type are positioned at the border of gate electrode below is 0 to 6 μ m.
Alternatively, said first doping type is the P type, and second doping type is the N type, and the length that said gate electrode is positioned at the part on the said field oxide is 1 to 4 μ m, and said length is along the direction in said source region to drain region.
Alternatively, said first doping type is the P type, and second doping type is the N type, and the length that said gate electrode is positioned at the part beyond the said field oxide is 3 to 6 μ m, and said length is along the direction in said source region to drain region.
Alternatively, said high-voltage MOS transistor structure also comprises the side wall that is positioned at around the said gate electrode.
Alternatively, said high-voltage MOS transistor structure also comprises the light doping section of the semiconductor layer that is arranged in said side wall below, and the doping type of said light doping section is identical with said source region and drain region, and doping content is less than the doping content in said source region and drain region.
Alternatively, said gate dielectric layer thickness is optional between 150～
.
Alternatively, said high-voltage MOS transistor structure also comprise in the trap of said second doping type and/or the trap of the trap of first doping type and second doping type between form field oxide.
Compared with prior art, the utlity model has following advantage:
The trap that high-voltage MOS transistor in the BCD technology of the utility model embodiment uses ion to inject to form different doping types is with channel region and drift region as device; The implantation concentration of said trap is based on the result that the actual flow water test obtains; Can not only take into account the performance of high-voltage MOS pipe preferably; And can with the BCD process compatible, making has the device of using trap in the BCD technology, functional like electric capacity, resistance, bipolar transistor, low pressure metal-oxide-semiconductor, DMOS pipe etc.; Save mask and injection technology effectively, practical more economically.
In addition, in the high-voltage MOS transistor structure in the BCD technology of present embodiment, adopt the trap of trap and second doping type of first doping type to be used as the drift region and the channel region of device, can with the BCD process compatible.And present embodiment has also carried out preferably making it can tolerate higher voltage to the relative dimensions of gate electrode, field oxide.
Description of drawings
Fig. 1 is the transistorized cross-sectional view of a kind of PMOS of prior art;
Fig. 2 is the schematic flow sheet of the manufacturing approach of the high-voltage MOS transistor in the BCD technology of the utility model embodiment;
Fig. 3 to Fig. 9 is the cross-sectional view of each step in the manufacturing approach of the high-voltage MOS transistor in the BCD technology of the utility model embodiment.
Embodiment
In the PMOS transistor formation method of the prior art; At first form the last epitaxial loayer of P type; And then form the N trap therein, use epitaxial loayer on a part of P type of this N trap and reservation respectively as the channel region and the drift region of device, but compatible relatively poor with BCD technology of this method.
The trap that high-voltage MOS transistor in the BCD technology of the utility model embodiment uses ion to inject to form different doping types is with channel region and drift region as device; The implantation concentration of said trap is based on the result that the actual flow water test obtains; Can not only take into account the performance of high-voltage MOS pipe preferably; And can with the BCD process compatible, making has the device of using trap in the BCD technology, functional like electric capacity, resistance, bipolar transistor, low pressure metal-oxide-semiconductor, DMOS pipe etc.; Save mask and injection technology effectively, practical more economically.
In addition, in the high-voltage MOS transistor structure in the BCD technology of present embodiment, adopt the trap of trap and second doping type of first doping type to be used as the drift region and the channel region of device, can with the BCD process compatible.And present embodiment has also carried out preferably making it can tolerate higher voltage to the relative dimensions of gate electrode, field oxide.
Below in conjunction with specific embodiment and accompanying drawing the utility model is described further, but should limit the protection range of the utility model with this.
The structure of the high-voltage MOS transistor in the BCD technology that present embodiment provided is as shown in Figure 9, comprising: the Semiconductor substrate 10 of first doping type (being specially the P type in the present embodiment); The buried regions 11 of second doping type is arranged in Semiconductor substrate 10; The semiconductor layer 12 of second doping type (being specially the N type in the present embodiment) covers said Semiconductor substrate 10 and buried regions 11; The trap 14 of first doping type and the trap 13 of second doping type are arranged in semiconductor layer 12 side by side; Field oxide 16 is between the trap 13 of the trap 14 of the trap 13 of the trap 14 of first doping type, second doping type or first doping type and second doping type; Gate dielectric layer 17 covers semiconductor layer 12; Gate electrode 18 is positioned on gate dielectric layer 17 and the field oxide 16, and gate electrode 18 has the first relative side and second side, and wherein first side extends on the gate dielectric layer 17 of trap 13 tops of second doping type, and second side extends on the field oxide 16; Source region 20 is arranged in the trap 13 of second doping type of gate electrode 18 first sides; Drain region 21 is arranged in the trap 14 of first doping type of gate electrode 18 second sides.
In addition; The device architecture of present embodiment also comprises: the light doping section 19 that is arranged in the semiconductor layer of side wall 22 and side wall 22 belows around the gate electrode 18; The doping type of light doping section 19 is identical with drain region 21 with source region 20, and doping content is less than the doping content in source region 20 and drain region 21; In the trap 13 of second doping type and/or the field oxide 16 between the trap 13 of the trap 14 of first doping type and second doping type
Fig. 2 shows the schematic flow sheet of the manufacturing approach of the high-voltage MOS transistor in the BCD technology of the utility model embodiment, comprising:
Step S11 provides the Semiconductor substrate of first doping type, on said Semiconductor substrate, forms the buried regions of second doping type, forms the semiconductor layer of second doping type then, and said second doping type is opposite with first doping type;
Step S12 uses ion implantation in said semiconductor layer, to form the trap of first doping type arranged side by side and the trap of second doping type;
Step S13 forms field oxide in the trap of said first doping type;
Step S14 forms the gate dielectric layer that covers said semiconductor layer;
Step S15; On said gate dielectric layer and field oxide, form gate electrode; Said gate electrode has the first relative side and second side, and wherein first side extends on the gate dielectric layer of trap top of said second doping type, and second side extends on the said field oxide;
Step S16 forms the source region in the trap of second doping type of said gate electrode first side, in the trap of first doping type of said gate electrode second side, form the drain region.
Fig. 3 to Fig. 9 shows the cross-sectional view of each step of the utility model embodiment, is elaborated below in conjunction with Fig. 2 and Fig. 3 to Fig. 9.
At first combine Fig. 2 and Fig. 3; Execution in step S11; The Semiconductor substrate 10 of first doping type (in the present embodiment be example to form the PMOS transistor, first doping type is specially the P type) is provided, on said Semiconductor substrate 10, forms the buried regions 11 of second doping type (being specially the N type in the present embodiment); Form the semiconductor layer 12 of second doping type then, said second doping type is opposite with first doping type.
Further, can also to pass through initial oxidation and form thickness on its surface be the oxide layer (not shown) of 0.2～0.6 μ m to Semiconductor substrate 10.
In the present embodiment, the formation method of concrete buried regions 11 is that the use lithography mask version is oriented the zone of the buried regions 11 of N type doping, carries out ion injection and annealing then.The ion that injects in the present embodiment is an antimony ion, and the injection energy is 55～65KeV, and dosage is optional between 1E15～2E15/cm2, and the annealing temperature of the buried regions 11 that the N type mixes is optional between 1000～1250 ℃, and the time is optional between 0.5～2H.
After forming buried regions 11, use epitaxial growth method to form semiconductor layer 12.As preferred embodiment, before epitaxial growth, at first use 1: 10～1: 20 hydrofluoric acid to clean.The thickness of the formed semiconductor layer 12 of present embodiment is 3.0～10.0 μ m, and resistivity is 1.0～3.0 Ω cm, and doping type is the N type.
In conjunction with Fig. 2 and Fig. 4, execution in step S 12, use ion implantation in said semiconductor layer 12, to form the trap 14 of first doping type arranged side by side and the trap 13 of second doping type.Concrete, first doping type is the P type in the present embodiment, second doping type is the N type.In addition, as signal, show the N trap 13 of P trap 14 both sides among Fig. 4 simultaneously.
Concrete, in step S12, form before N trap 13 and the P trap 14, can be at the superficial growth thin oxide layer 15 of semiconductor layer 12, its thickness does
Between optional; Use the position of N trap mask positioning N trap 13 afterwards and inject phosphonium ion, inject energy and be 70 to 90KeV, implantation dosage is 1E12 to 1E13/cm
2Use the position of P trap mask positioning P trap 14 then and inject the boron ion, inject energy and be 90 to 110KeV, implantation dosage is 5E12 to 5E13/cm
2Certainly, in other specific embodiments, the formation order of N trap 13 and P trap 14 can exchange, and the injection ion of being selected for use also can be other ions of the same type.Form after N trap 13 and the P trap 14, can thin oxide layer 15 be removed.
Adopt ion to inject in the present embodiment and form P trap 14 and N trap 13, P trap 14 is as the drift region of device, and N trap 13 is as the channel region of device, and its technical process belongs to the conventional twin well process in the BCD technology, can with the BCD process compatible, practical more economically.
In conjunction with Fig. 2 and Fig. 7, execution in step S13 forms field oxide 16 in the trap 14 of said first doping type; Execution in step S14 forms the gate dielectric layer 17 that covers said semiconductor layer 12.
Describe in the face of the detailed process of step S13 and S14 down.At first with reference to figure 5, at first on the surface of semiconductor layer 12, form pad oxide 151, on pad oxide 151, form mask layer 152 then, the material of mask layer 152 is SiN, and mask layer 152 is carried out graphically defining the figure of field oxide 16.Wherein the thickness of pad oxide 151 is 200～
optional.The graphical process of mask layer 152 can comprise steps such as photoetching, etching.In other specific embodiments, the material of mask layer 152 can also be that other well known to a person skilled in the art hard mask material.
Afterwards with reference to figure 6, form photoresist layer 153 on the mask layer 152 after graphical and it is carried out graphically exposing the zone of P trap 14.Preferably, employed mask can be the P trap mask that forms P trap 14 before in the photoresist layer 153 graphical processes, to save the expense of extra mask.Afterwards; With the photoresist layer after graphical 153 with graphical after mask layer 152 be mask; The ion injection is carried out in the zone (this zone also can be described as P type buried channel zone) that will form field oxide, and injecting ion is P type ion, is specially the boron ion in the present embodiment; Inject energy and be 25 to 50KeV, implantation dosage is 5E13 to 1E14/cm
2, after injecting the photoresist layer after graphical 153 is removed.Certainly, in other specific embodiments, the ion that injects in P type buried channel zone can also be other P type ions, like indium ion etc.
Will form field oxide owing to follow-up; And thicker field oxide has ion adsorption for P type ion; Make the doping contents on P trap 14 surface descend, inject through P type buried channel zone being carried out ion in the present embodiment, increased should the zone ion concentration; Thereby the suction-operated in the time of can offsetting follow-up formation field oxide, the suction-operated that prevents field oxide causes the problem of surface doping lowering of concentration.
Need to prove, in P trap 14, form in the process of field oxide 16, can also in N trap 13 and/or between N trap 13 and the P trap 14, form field oxide in the lump.Concrete, in the present embodiment, also simultaneously in N trap 13 and between N trap 13 and the P trap 14, formed field oxide 16, with as the isolation between the device.
Combine Fig. 6 and Fig. 7 afterwards; Photoresist layer 153 after removing graphically is a mask with the mask layer 152 after graphical after removing, and semiconductor layer 12 is carried out oxidation; The method of oxidation can be a localized oxidation of silicon (LOCOS) etc., in P trap 14, forms field oxide 16.
Forming after the field oxide 16, can also carry out sacrificial oxidation, form the sacrificial oxide layer (not shown) the surface of semiconductor layer 12, the thickness of sacrificial oxide layer is 300～
Optional; Be that mask carries out the ion injection to semiconductor layer 12 with field oxide 16 afterwards, concrete with the threshold voltage of trim, inject ion and can be the boron ion, it is optional between 25～40KeV to inject energy, and dosage is at 1.0E12～3.0E12/cm
2Between optional.Certainly, in the injection process of regulating threshold voltage, the zone that also can use mask that needs are regulated threshold voltage positions.
Afterwards; Form the gate dielectric layer 17 that covers semiconductor layer 12; Its thickness is optional between 150～
, and its formation method can be to well known to a person skilled in the art method.
In conjunction with Fig. 2 and Fig. 8; Execution in step S 15; On said gate dielectric layer 17 and field oxide 16, form gate electrode 18; Said gate electrode 18 has the first relative side and second side, and wherein first side extends on the gate dielectric layer 17 of trap 13 tops of said second doping type, and second side extends on the said field oxide 16.More specifically, gate electrode 18 is across N trap 13 and P trap 14, and covers on the field oxide 16 in the P trap.
The material of gate electrode 18 is a polysilicon in the present embodiment, and its formation method can comprise: at first use CVD to form polysilicon layer, and its thickness is 2500～
Between optional; Afterwards this polysilicon layer is carried out ion and inject, injecting ion in the present embodiment is phosphonium ion, and the injection energy is 35～45KeV, and dosage is 2E15～8E15/cm
2Between optional; Through technologies such as photoetching, etchings polysilicon layer is carried out graphically then, form gate electrode 18.
In conjunction with Fig. 2 and Fig. 9, execution in step S16 forms source region 20 in the trap 13 of second doping type of said gate electrode 18 first sides, in the trap 14 of first doping type of said gate electrode 18 second sides, forms drain region 21.
Concrete, in the present embodiment, at first use reticle to orient the zone in source region 20 and drain region 21, it is carried out the light dope ion inject.Light dope ion injection ion is a P type ion in the present embodiment, is specially the boron ion, and the injection energy is 35～45KeV, and dosage is 2E13/cm
2, to anneal after the injection, annealing temperature is optional between 800～900 ℃, annealing time is optional between 0.5～2H.
After the light dope ion injects, around gate electrode 18, form side wall (spacer) 22, the material of side wall 22 can be silica, silicon nitride or the like.To be mask carry out the source to the zone in source region 20 and drain region 21 leaks ion and inject with side wall 22 then, the source leak implantation dosage that ion injects greater than before the implantation dosage that injects of light dope ion.Concrete, in the present embodiment, the injection ion that the ion injection is leaked in the source is the boron ion, and the injection energy is 75～85KeV, and implantation dosage is 1E15～4E15/cm
2The source is leaked ion and is injected the ion that can anneal afterwards and inject to activate, and annealing temperature is optional between 850～900 ℃, and annealing time is optional between 10～60min.Because the effect of blocking of side wall 22 after the injection of source leakage ion, remains with light doping section 19 in the semiconductor layer 12 of side wall 22 belows.Afterwards,, can form the dielectric layer that covers entire device, then dielectric layer carried out etching and expose source electrode 20, drain electrode 21 and gate electrode 18, form metal line then each electrode of device is drawn as known in those skilled in the art.
Different with device mentioned in the background technology, in the device architecture of present embodiment, N trap 13 belows do not form p type buried layer.If the adding p type buried layer, thin out the shortening of knot that can cause the buried regions 11 of N type doping, the β of Semiconductor substrate 10 these parasitic PNP pipes that the buried regions 11-P type that makes P trap 14-N type mix mixes becomes greatly, causes parasitic leakage current to increase.Because therefore the buried regions that below N trap 13, does not have the P type to mix in the device architecture of present embodiment has avoided the problems referred to above.
As a preferred embodiment, the length d 2 of field oxide 16 is 2 to 6 μ m, length d 2 along the source region 20 to the drain region 21 direction; Field oxide 16 has first side and second side, and wherein first side is positioned at gate electrode 18 belows, and second side is near drain region 21, first side of field oxide 16 and the trap 14 of first doping type be positioned at gate electrode 18 belows the border be 0 to 6 μ m apart from d1; The length d 4 that gate electrode 18 is positioned at the part on the field oxide 16 is 1 to 4 μ m, length d 4 along the source region 20 to the drain region 21 direction; The length d 3 that gate electrode 18 is positioned at the part beyond the field oxide 16 is 3 to 6 μ m, length d 3 along the source region 20 to the drain region 21 direction.
The inventor uses processing simulation device TSUPREM-4 and device simulation device Medici that the device architecture (being specially the PMOS transistor) that present embodiment forms has been carried out emulation, and wherein the influence of 1 pair of device withstand voltage of length d is as shown in the table:
| Length d 1 | 0um | 0.5um | 1um |
| Withstand voltage | 29.8V | 28.2V | 26.8V |
The influence of 3 pairs of device withstand voltages of length d is as shown in the table:
| Length d 3 | 3um | 4um | 5um | 6um |
| Withstand voltage | 29.9V | 30.3V | 30.8V | 30.1V |
Visible by above-mentioned simulation result, adopt the preferred sizes scope that present embodiment adopted, can be so that device has higher withstand voltage.
Need to prove; Be that example describes with the PMOS transistor in the present embodiment, in other specific embodiments, also can be under the constant condition of subregion doping type; Size through changing other regional doping types, adjustment length d 1-d4 forms nmos pass transistor; Promptly first doping type is the N type, and second doping type is the P type, and the doping content of the energy that ion is injected, dosage, doped region is done corresponding adjustment.Certainly, under also can the be constant prerequisite, change other regional doping types, thereby realize the forming process of nmos pass transistor at the doping type of semiconductor layer 12.
Though the utility model with preferred embodiment openly as above; But it is not to be used for limiting the utility model; Any those skilled in the art are in spirit that does not break away from the utility model and scope; Can make possible change and modification, so the protection range of the utility model should be as the criterion with the scope that the utility model claim is defined.
Claims (9)
1. the high-voltage MOS transistor structure in the BCD technology is characterized in that, comprising:
The Semiconductor substrate of first doping type;
The buried regions of second doping type is arranged in Semiconductor substrate;
The semiconductor layer of second doping type covers said Semiconductor substrate and buried regions, and said second doping type is opposite with said first doping type;
The trap of the trap of first doping type and second doping type is arranged in said semiconductor layer side by side;
Field oxide is arranged in the trap of said first doping type;
Gate dielectric layer covers said semiconductor layer;
Gate electrode is positioned on said gate dielectric layer and the field oxide, and said gate electrode has the first relative side and second side, and wherein first side extends on the gate dielectric layer of trap top of said second doping type, and second side extends on the said field oxide;
The source region is arranged in the trap of second doping type of said gate electrode first side;
The drain region is arranged in the trap of first doping type of said gate electrode second side.
2. the high-voltage MOS transistor structure in the BCD technology according to claim 1; It is characterized in that said first doping type is the P type, second doping type is the N type; The length of said field oxide is 2 to 6 μ m, and said length is along the direction in said source region to drain region.
3. the high-voltage MOS transistor structure in the BCD technology according to claim 1; It is characterized in that said first doping type is the P type, second doping type is the N type; Said field oxide has first side and second side; First side of said field oxide is positioned at said gate electrode below, and second side is near said drain region, and the distance that first side of said field oxide and the trap of said second doping type are positioned at the border of gate electrode below is 0 to 6 μ m.
4. the high-voltage MOS transistor structure in the BCD technology according to claim 1; It is characterized in that; Said first doping type is the P type; Second doping type is the N type, and the length that said gate electrode is positioned at the part on the said field oxide is 1 to 4 μ m, and said length is along the direction in said source region to drain region.
5. the high-voltage MOS transistor structure in the BCD technology according to claim 1; It is characterized in that; Said first doping type is the P type; Second doping type is the N type, and the length that said gate electrode is positioned at the part beyond the said field oxide is 3 to 6 μ m, and said length is along the direction in said source region to drain region.
6. the high-voltage MOS transistor structure in the BCD technology according to claim 1 is characterized in that, also comprises being positioned at said gate electrode side wall on every side.
7. the high-voltage MOS transistor structure in the BCD technology according to claim 6; It is characterized in that; The light doping section that also comprises the semiconductor layer that is arranged in said side wall below; The doping type of said light doping section is identical with said source region and drain region, and doping content is less than the doping content in said source region and drain region.
8. the high-voltage MOS transistor structure in the BCD technology according to claim 1; It is characterized in that said gate dielectric layer thickness is optional between 150～
.
9. the high-voltage MOS transistor structure in the BCD technology according to claim 1 is characterized in that, also comprise in the trap of said second doping type and/or the trap of the trap of first doping type and second doping type between form field oxide.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102263034A (en) * | 2011-08-12 | 2011-11-30 | 杭州士兰集成电路有限公司 | High pressure MOS transistor structure in BCD technology and manufacturing method thereof |
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