CN101276788B

CN101276788B - Method for improving electrostatic discharge protection performance of silicon circuit in insulators

Info

Publication number: CN101276788B
Application number: CN2007100648705A
Authority: CN
Inventors: 曾传滨; 李多力; 李晶; 海潮和; 韩郑生
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2007-03-28
Filing date: 2007-03-28
Publication date: 2012-05-23
Anticipated expiration: 2027-03-28
Also published as: CN101276788A

Abstract

The invention relates to the field of semiconductor technology and discloses a method for improving ESD protection performance of SOI circuit, the method carries out ESD injection in body region of the SOI circuit, changes ESD puncture voltage of the SOI circuit and promotes the ESD discharge tubes and each grids within the ESD discharge tubes to simultaneously open when the ESD voltage comes, in the meantime the body region potential is raised by the current generated while puncturing in order to advance BJT parasitized in MOS tube to discharge the current. The invention solves the problem that, as the general injection method below the contact hole is used in SOI circuit, the injection impurities are covered by leakage end impurities or exhaust region formed by the substrate below leakage/leakage end. The invention transfers the injection to the body region, in one hand, the puncture voltage can be reduced better, in other hand, the current is able to be guided into the region body greatly, thus improving the ESD resistance of the device and the entire circuit.

Description

A kind of method of improving electrostatic discharge protection performance of silicon circuit in insulators

Technical field

The present invention relates to technical field of semiconductors, relate in particular to a kind of silicon-on-insulator (SOI) circuit static discharge (Electrostatic Discharge, ESD) method of barrier propterty improved.

Background technology

Because the full dielectric isolation of SOI circuit and thin said current dumping passage, the ESD protection question of SOI circuit becomes more and more important.(complementarymetal oxide semiconductor CMOS) in the circuit, adopts ESD to inject and can obtain good effect at the body complementary metal oxide semiconductor; Its method is under the drain terminal contact hole, to carry out ESD to inject; Reduce the drain terminal puncture voltage,, cooperate silicide baffle plate (Salicide blocking according to " electrostatic discharge protective of CMOS integrated circuit " study course of the M.D.ker of Taiwan university of communications professor; SAB) technology can obtain good effect.

But because the SOI circuit almost completely injects N+ (NMOS, N NMOS N-channel MOS N) or P+ (PMOS, P-channel metal-oxide-semiconductor) at drain terminal, this method for implanting will be no longer suitable.Particularly in thick film technology; Though the impurity consistent possibly occur with the tagma at drain terminal; Near structure after carrying out the ESD injection drain terminal contact of thick film device as shown in Figure 7; But find that through experiment there is such problem in SOI: a kind of N+-N as shown in Figure 8-N+ structure, wherein the transoid under the effect of grizzly bar N type POLY of the P district in the raceway groove becomes high resistance area.

During experiment gate electrode and source electrode are added 0 level, body electrode suspension joint is found Fig. 9 effect through giving the drain electrode making alive.When drain terminal added negative voltage, the source end was a high level, and grid is a high level, be equivalent to a conducting metal-oxide semiconductor (MOS) (Metal Oxide Semiconductor, MOS) pipe, different is that in fact source/drain electrode has become leakage/source electrode.When drain terminal added positive voltage, the source end was a low level, and grid is a low level, was equivalent to the metal-oxide-semiconductor that a channel region turn-offs.At this moment problem has been come out, if the tagma is enough thick, the N district of back of the body gate part will be retained, and still have N+-N-N+ passage.It not be very greatly that square resistance changes, and sharply increases but experimental result shows resistance, explains that the N district of back of the body gate part is being exhausted when drain terminal voltage increases always, and square resistance is very big.

Infer thus;, drain terminal can form the very big depletion region of resistance when adding high level voltage in the P district below the drain terminal; Even under contact hole, produce partial breakdown; Its electric current also is difficult to export to tagma lifting bipolar junction transistor, and (performance is not very desirable for Bipolar Junction Transistor, BJT) bleed off electric current.

Summary of the invention

The technical problem that (one) will solve

In view of this; Main purpose of the present invention is to provide a kind of method of the SOI of improvement circuit ESD barrier propterty; To solve the problem of in the SOI circuit, using the conventional depletion region that is encased by drain terminal impurity or formed at implanted dopant that method for implanting is brought under the contact hole to encase by the substrate below the leakage/drain terminal; Reduce puncture voltage, improve the anti-ESD ability of device and entire circuit.

(2) technical scheme

For achieving the above object, technical scheme of the present invention is achieved in that

A kind of method of improving electrostatic discharge protection performance of silicon circuit in insulators; This method is employed in the tagma of silicon-on-insulator SOI circuit and carries out static discharge ESD injection; Change the ESD puncture voltage of SOI circuit; And when ESD voltage arrives, open simultaneously between the promotion esd discharge pipe and between inner each grizzly bar of esd discharge pipe, the electric current lifting tagma current potential that produces during simultaneously through puncture, promotion colonizes in the bipolar junction transistor BJT bleed off electric current in the metal-oxide semiconductor (MOS) metal-oxide-semiconductor.

In the such scheme; For N NMOS N-channel MOS N NMOS pipe, it is in the tagma of SOI circuit that said tagma at the SOI circuit carries out that ESD injects, particularly near the part of drain terminal; Carrying out ESD injects; Make the part of puncture place in tagma and drain terminal boundary, specifically comprise: when doing the tuned grid injection, revising back of the body grid implantation dosage and injecting energy is 1.0e ¹⁴/ cm ²And 65keV, puncture voltage is adjusted to 6 to 8V by the 12V of proper device; Inject influence in order to reduce ESD to internal circuit; Generally adopt twice grid to inject; Inject for the first time the demanding internal circuit of threshold voltage is injected; Remove photoresist, clean, bake in advance HMDS HMDS, gluing, photoetching, development and check then, and after hard baking, the pipe that is used for esd protection is carried out the second time and inject, implantation dosage and injection energy are 1.0e ¹⁴/ cm ², 65keV.

In the such scheme, said photoetching adopt increase newly one independently ESD inject reticle, this ESD injects the pipe tagma that reticle will be used for esd protection and is designed to printing opacity, the zone design of other pipe is light tight; Said injection adopts the boron ion as implanted dopant.

In the such scheme; For the NMOS pipe, it is to carry out ESD in the place that the drain terminal and the tagma of SOI circuit have a common boundary to inject that the ESD injection is carried out in said tagma at the SOI circuit, and keeping channel region has lower concentration; Help keeping higher BJT gain; Specifically comprise: for first kind of structure, making grizzly bar and making between two processing steps of side wall sidewall spacer and inject, implantation dosage and injection energy are 1.0e ¹⁴/ cm ²And 65keV; For second kind of structure, to make side wall sidewallspacer and making between two processing steps of silicide and inject, implantation dosage and injection energy are 1.5e ¹⁴/ cm ²And 65keV, utilize high impurity concentration district of Impurities Scattering Effect generation when injecting, reduce and leak bulk breakdown voltage.

In the such scheme, for said first kind of structure,, directly adopt the source, leak and inject reticle if requirement is not very high to threshold voltage; If threshold voltage is had relatively high expectations, then adopt special ESD to inject reticle, its way be only to the source of the pipe of the grounded-grid that is used for the ESD protection, leak injection zone and be designed to transparent area, other parts are light tight district; For said second kind of structure,, then making side wall sidewall spacer and making between two processing steps of silicide baffle plate and inject if silicide baffle plate technology is arranged; Said first kind of structure is consistent with the domain that said second kind of structure adopts.

In the such scheme, for NMOS pipe, it is to carry out ESD and inject doing the position of oxygen field oxide that said tagma at the SOI circuit carries out that ESD injects, and directly adopts to revise an implantation dosage and energy is 1.5e ¹⁴/ cm ²And 65keV, the puncture voltage of reduction SOI circuit.

In the such scheme, saidly directly field implant concentration is injected in the field when injecting and improve doing, reach the purpose that ESD injects.

This method further in the source/leakage part area carries out ESD and injects.

This method further changes reticle, only the part of leaning on drain terminal is carried out the mode that ESD injects.

This method is boundary with the mid line of each polysilicon grizzly bar when making ESD and inject reticle, will lean on the domain of drain terminal part to keep, and leans on the layout design of source end parts to become light tight district.

This method further combines to promote the effect that ESD injects with silicide baffle plate SAB technology; After obtaining the ESD injecting structure in realization; Inject between two processing steps of formation silicide in source/leakage and to add silicide baffle plate SAB technology;, reach in the effect of drain terminal contact hole to a small resistor of serial connection between the LDD to forming one section N+ district that does not have silicide between the leakage LDD structure of gently mixing up at the drain terminal contact hole, maximum field squints to drain terminal contact hole direction when making device work.

In the such scheme, said SAB technology specifically comprises:

A, after side wall sidewall spacer technology is accomplished, with on silicon chip, the grow oxide layer of one deck 2000 dusts of the method for thermal decomposition;

B, HMDS are roasting in advance, gluing, photoetching, promptly at the drain terminal contact hole contact of ESD protective device to forming one section photoresistance between the polysilicon grizzly bar POLY, other part all shows out;

C, development, check, roasting firmly after etching; Adopt two-step etching method during etching; Promptly when oxidated layer thickness is also thicker, use etch-rate faster;, oxide layer etch-rate low with corrosion rate when thin: the technology that silicon etch rate ratio is high is carried out etching, guarantees that the damage of silicon is minimum, is unlikely to influence device performance;

D, remove photoresist, the SAB structure fabrication is accomplished.

In the such scheme, said tagma at the SOI circuit carries out adopting the wide-angle method for implanting when ESD injects, and specifically comprises: with silicon chip 45 degree that tilt, because range becomes far away, with implantation dosage and energy is corresponding is adjusted to original 1.4 times; Because the restriction of incline direction; The device drain terminal that requirement is injected into will be in one direction, and the high concentration tagma of device will increase the distance of a silicon film thickness at channel direction, under self-registered technology, obtains bigger ESD and inject area; And the concentration in reservation end tagma, source, obtain higher gain.

In the such scheme; Manage for P-channel metal-oxide-semiconductor PMOS; The manufacture method of ESD method for implanting and NMOS pipe is similar, and the injection phase is injected corresponding to the tagma of PMOS pipe, source, leakage, a position in tagma, source, leakage, field that aforementioned each ESD method for implanting of NMOS pipe adopts; Said tagma at the SOI circuit is carried out ESD and is injected the employing phosphonium ion as implanted dopant, and injecting energy is 2.7 times that NMOS manages each ESD method for implanting, and implantation dosage is 0.7 times of each ESD method for implanting of NMOS pipe.

(3) beneficial effect

Can find out that from technique scheme the present invention has following beneficial effect:

1, utilizes the present invention; Inject through carry out ESD in the tagma; Change the ESD puncture voltage, promote between the esd discharge pipe, and can when ESD voltage arrives, open simultaneously between inner each grizzly bar of esd discharge pipe; The electric current lifting tagma current potential that produces during simultaneously through puncture promotes to colonize in the BJT bleed off electric current in the metal-oxide-semiconductor.In order to overcome the problem that SOI silicon fiml strip comes, the invention solves the problem of in the SOI circuit, using the conventional depletion region that implanted dopant that method for implanting brings is encased by drain terminal impurity or formed by the substrate below the leakage/drain terminal under contact hole to encase; The present invention moves on to the tagma with injection, can reduce puncture voltage well on the one hand, and electric current can import to the tagma well on the other hand, improves the anti-ESD ability of device and entire circuit.

2, utilize the present invention; With the ESD protective device of this ESD injection device as input, efferent duct; Overcome the risk of hundred nanosecond that in 0/1 conversion, the occur electric leakage shown in Figure 14 (b) that gate coupled technology (like Figure 14 (a)) brings; Though this risk can be reduced near the threshold voltage voltage through regulating coupled structure in grid Dynamic Coupling technology; But because near the coupled voltages the threshold voltage can influence the puncture voltage of NMOS tempestuously, adjustable extent is very little, (its threshold voltage is 1V) shown in figure 15.The parasitic BJT of some NMOS in addition, when grid is slightly larger than threshold voltage according, BJT cut-in voltage lower (maybe less than 5V), the false triggering that produces BJT has brought bigger electric leakage risk (like Figure 16).And there is not the voltage coupled problem in this device because grid connects extremely, and the voltage (being BJT cut-in voltage shown in Figure 16) of keeping after also can ESD being punctured after ESD injects simultaneously suitably improves (can reach 5.5V-6.8V), does not also just have these electric leakage risk problem.

3, utilize the present invention, in some little circuit, can directly utilize the facility that grid injects or the field is injected to carry out the ESD injection, practiced thrift the cost that independent making a slice ESD injects reticle.

4, utilize the present invention, combine with present technique in the SAB of the technical exploitation of SOI technology, performance has further obtained raising.

Description of drawings

Fig. 1 is the sketch map that carries out the ESD injection phase provided by the invention;

Fig. 2 (a) is the structural representation that after gate electrode is carved into, carries out the ESD injection provided by the invention;

Fig. 2 (b) is the structural representation that after sidewall spacer is carved into, carries out the ESD injection provided by the invention;

Fig. 3 carries out the sketch map that ESD injects for injection phase on the scene provided by the invention;

Fig. 4 is the sketch map that carries out wide-angle ESD injection provided by the invention;

The sketch map that Fig. 5 only leans on drain terminal partly to inject to the tagma for the method for utilization change domain provided by the invention;

Fig. 6 is the ESD overall situation safeguard structure sketch map that use ESD provided by the invention injects;

Fig. 7 is near the structural representation after carrying out the ESD injection drain terminal contact of thick film device provided by the invention;

Fig. 8 is the sketch map of a kind of N+-N provided by the invention-N+ structure;

Fig. 9 is the Vds-tagma square resistance figure of N+-N provided by the invention-N+ structure;

Figure 10 is used for the sketch map that ESD injects for an injection mode that changes provided by the invention;

Figure 11 is the sketch map that the ESD of structure shown in Figure 2 injects the reticle structure;

Figure 12 is the sketch map that is used for injecting with ESD the SAB structure that is used provided by the invention;

Figure 13 is the sketch map of SOI model configuration provided by the invention;

Figure 14 (a) is for there being the grid Dynamic Coupling structural representation of electric leakage risk;

The sketch map of gate coupled voltage when Figure 14 (b) adds the 7V pulse voltage for Figure 14 (a) structure between drain terminal and source end;

Figure 15 manages the sketch map of puncture voltage under different grid voltages for the SOI NMOS that does not adopt the ESD injection technique;

Figure 16 manages the sketch map of leakage current when grid voltage is 1.1V for the SOI NMOS that does not adopt the ESD injection technique.

Embodiment

For making the object of the invention, technical scheme and advantage clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, to further explain of the present invention.

At first introduce realization principle of the present invention: in SOI technology, drain terminal having occurred almost all is the situation of N+ (NMOS), P+ (PMOS) impurity, like the simulate effect of Figure 13.Even in thick film technology, below the drain terminal lining is low, kept under the situation of a part of tagma impurity, as shown in Figure 7; We also can find out according to experimental result shown in Figure 9, and the charge carrier after drain terminal adds positive voltage below it can be exhausted, and resistance is very high; When producing puncture; Be unfavorable for that breakdown current exports to the tagma,, will have a greatly reduced quality the effect that promotes parasitic BJT though can suitably improve the problem (the body current ratio that promotes unlatching simultaneously to need is less) of opening simultaneously.The present invention directly will puncture position and placed in tagma and the place of leaking the boundary, solve this problem.

The present invention is employed in the tagma of SOI circuit and carries out the ESD injection; Change the ESD puncture voltage of SOI circuit; And, opens simultaneously ESD voltage when arriving between the promotion esd discharge pipe and between inner each grizzly bar of esd discharge pipe; The electric current lifting tagma current potential that produces during simultaneously through puncture promotes to colonize in the BJT bleed off electric current in the metal-oxide-semiconductor.

Particularly; The present invention forms a zone higher with respect to internal circuit tagma concentration, or at internal circuit puncture voltage is required when not being very strict directly all corresponding raising of each device tagma local concentration with entire circuit in the SOI device tagma that is used for ESD protection; Reduce the leakage/bulk breakdown voltage of ESD protective device; Make that protective device can be all breakdown near keeping voltage (hold) point after the electrical break down; Reach between inner each grizzly bar of each protective device and protective device and can open simultaneously, and under big breakdown current effect, leaking body breakdown current (the anti-breakdown current partially of diode) on the one hand can the bleed off one part of current; This electric current can lifting tagma current potential on the other hand, promotes more effectively bleed off electric current of the parasitic BJT of metal-oxide-semiconductor.In practical implementation, be divided into following two types of implementations: one type is the realization of NMOS body region ESD method for implanting, and another kind of is the realization of PMOS body region ESD method for implanting.

For the realization of NMOS body region ESD method for implanting, following several kinds of modes are arranged:

Mode one: structure as shown in Figure 1; It is that the tagma part of drain terminal (particularly near) at the SOI circuit is carried out ESD and injected that said tagma at the SOI circuit carries out that ESD injects; Make the part of puncture place in tagma and drain terminal boundary; Specifically comprise: when doing the tuned grid injection, direct modification back of the body grid implantation dosage and injection energy are 1.0e ¹⁴/ cm ², 65keV (inject boron ion, the ESD implanted dopant of following NMOS all is the boron ion), puncture voltage is adjusted to 6-8V by the 12V of proper device.Inject influence in order to reduce ESD, generally adopt twice grid to inject, for the first time internal circuit etc. is injected earlier the demanding pipe of threshold voltage internal circuit; Clean HMDS (roasting in advance), gluing after removing photoresist; Photoetching (adopt the ESD that increases newly to inject reticle during photoetching, the characteristics of this edition are that the pipe appropriate section that is used for esd protection is designed to printing opacity, and other parts are light tight); Development, check, hard roasting the injection afterwards, implantation dosage and injection energy are 1.0e ¹⁴/ cm ², 65keV.

It is to carry out ESD in the place that the drain terminal and the tagma of SOI circuit have a common boundary to inject that mode two, structure as shown in Figure 2, said tagma at the SOI circuit are carried out the ESD injection, and keeping channel region has lower concentration, helps keeping higher BJT gain.

In alignment precision very high (under the negligible situation of deviation of the alignment); Can adopt the mode of twice grid injection in the similar fashion one; Different is to revise the appearance that reticle becomes Figure 11; Be that the source leakage is transparent area, the grizzly bar zone is light tight district, and the source leakage then is drawn as printing opacity by ESD injection phase shown in Figure 2 near the tagma part and gets final product.Structure implantation dosage shown in Fig. 2 (a) and injection energy are 1.0e ¹⁴/ cm ², 65keV, Fig. 2 (b) structure is 1.5e ¹⁴/ cm ², 65keV.

If alignment precision is poor, can adopt self aligned mode, wherein structure shown in Fig. 2 (a) is being made grizzly bar and is being made between two processing steps of sidewall spacer and do, and implantation dosage and injection energy still are 1.0e ¹⁴/ cm ², 65keV.Structure shown in Fig. 2 (b) is done with making between two processing steps of silicide (if silicide baffle plate technology is arranged then for making the silicide baffle plate) making sidewall spacer, and implantation dosage and injection energy are 1.5e ¹⁴/ cm ², 65keV.Requirement is not very high to Fig. 2 (a) if structure is to threshold voltage; Can directly adopt the source, leak and inject reticle; If require higher; Then can adopt special ESD to inject reticle, its way be only to the source of the pipe that is used for esd protection, leak injection zone and be designed to transparent area, other parts are light tight district.The domain that Fig. 2 (b) structure adopts is consistent with Fig. 2 (a).

Mode three, shown in figure (3) structure because its breakdown area is limited, mainly be used on the little circuit of thick film, can form Fig. 3 (a) structure on the one hand, because circuit is little, it is less relatively leak electricity on the other hand, can directly adopt to revise the field implantation dosage and energy is 1.5e ¹⁴/ cm ², 65keV reaches the whole purpose that reduces puncture voltage, saving the effect that reaches the ESD protection when increasing an ESD reticle.

Mode four, when in implementation one, two, three, making ESD and injecting reticle; Mid line with each polysilicon grizzly bar is boundary; Show and open the part reservation previous designs figure that leans on drain terminal in the district; Lean on the part of source end all to be designed to light tight district, on the technology with implementation one, two, three consistent getting final product.

Mode five, revising ESD, to inject domain shown in figure 10; The pipe that promptly is used for esd protection; The injection reticle local on the scene that will carry out the ESD injection that shows like Fig. 1, Fig. 2 also is drawn as transparent area (if size can be drawn as transparent area with the source/leakage part area of this pipe less than critical size, increasing the transparent area line size).The field implantation dosage and the energy of Fig. 1 and Fig. 2 (a) structure are 1.2e ¹⁴/ cm ², 65keV, field implantation dosage and the energy of Fig. 2 (b) structure are 1.6e ¹⁴/ cm ², 65keV (Fig. 2 (b) structure requires than higher mask aligner in this mode).

Mode six, can be as required make a slice ESD and inject version in the relevant position; The part of source/drain terminal is added that the ESD injection zone that Fig. 1, Fig. 2 show is designed to transparent area (requiring minimum dimension to be not less than the critical size of production technology); Other part is light tight district; Or only consider the structure of drain terminal part according to Fig. 5 mode; Use afterwards than the technology of internal circuit demand technology more than high 2 generations (like 1.2um SOI technology with 0.35um or more senior CMOS technology), each stage that can be chosen in before making the silicide process step (if silicide baffle plate technology is arranged then before making silicide baffle plate processing step) flow is carried out the production of ESD injecting structure of the present invention.Owing to only the device that is used for the ESD protection is injected; This device is in off state when the circuit operate as normal; Lower to technological requirement; And consider the problem of BJT false triggering, its critical size also hanged down for 1～2 generation than internal work circuit usually, so the alignment error that produces can not considered.Injecting energy and dosage gets final product with the puncture voltage that the technology simulation softward combines measured data to obtain about 6～8V (when operating voltage is 5V).

Mode seven, combine further to promote the effect that ESD injects with SAB technology.Adopt a kind of acquisition ESD injecting structure of mode one to mode six in realization; Inject between two processing steps of formation silicide in source/leakage and to add SAB technology; Its objective is at the drain terminal contact hole to forming one section N+ district that does not have silicide between the leakage that gently mixes up (LDD) structure; Reach in the effect of drain terminal contact hole to a small resistor of serial connection between the LDD, maximum field squints to drain terminal contact hole direction when making device work.Said SAB technology specifically comprises:

Step 1, after sidewall spacer technology is accomplished, with on silicon chip, the grow oxide layer on one deck 2000 Izods right side of the method for thermal decomposition.

Step 2, HMDS are roasting in advance, gluing, photoetching, and reticle structure such as Figure 12 promptly form one section photoresistance between drain terminal (the source end also can be done a bit of usually) contact hole (contact) to the polysilicon grizzly bar (POLY) of ESD protective device, and other part all shows out.

Step 3, development, check, roasting firmly after etching; Adopt two-step etching method during etching; Promptly when oxidated layer thickness is also thicker, use etch-rate faster;, oxide layer etch-rate low with corrosion rate when thin: the technology that silicon etch rate ratio is high is carried out etching, guarantees that the damage of silicon is minimum, is unlikely to influence device performance.

Step 4, remove photoresist, the SAB structure fabrication is accomplished.

Mode eight, employing wide-angle are injected and all can be made moderate progress to the application of structure under corresponding demand shown in Fig. 2 (a) and Fig. 2 (b).In the production with the silicon chip angle about 45 degree that tilts, because range becomes far away, with 1.4 times of implantation dosage and the corresponding adjustment of energy.Because the restriction of incline direction, the device drain terminal that requires to be injected into will be in one direction, otherwise will repeatedly inject, and increases production cost.By this way, the high concentration tagma of device will increase the distance of a silicon film thickness at channel direction, under self-registered technology, obtain more ESD injection area, and keep the concentration in end tagma, source, promptly keep higher gain.

Use through on the side circuit of a 1.5mm * 1.5mm of the thick film SOI technology of a 2um obtains experimental data such as following table:

Technology	Implantation dosage	Inject energy	Puncture voltage	Anti-human body discharging model (HBM) static discharge voltage
					Not being ESD injects	0	0	12V	Less than 1500V
ESD injects one	3e ¹³/cm ²	65keV	10V	Less than 2000V
					ESD injects two	1e ¹⁴/cm ²	65keV	7.8V	Greater than 2500V

Table 1, experimental circuit ESD protection effect

In the experiment of another one film; We adopt the SAB technology; Puncture voltage is reduced to 6V; That does not adopt SAB technology can only obtain the HBM protective capacities less than 1500V, and adopt the SAB technology can obtain HBM protective capacities, the effect unique that visible the present invention and SAB technology are used greater than 3250V.

Realization for PMOS body region ESD method for implanting: said tagma at the SOI circuit is carried out ESD and is injected the employing phosphonium ion as implanted dopant; The realization that PMOS body region ESD injects; Except that implanted dopant, dosage and energy, the implementation of injecting with NMOS body region ESD is consistent.The impurity that PMOS body region ESD injects is phosphonium ion, and injecting energy is the injection energy of 2.7 times of aforementioned corresponding NMOS body region ESD injection modes, and implantation dosage is the implantation dosage of 0.7 times of aforementioned corresponding NMOS body region ESD injection mode.

Above-described specific embodiment; The object of the invention, technical scheme and beneficial effect have been carried out further explain, and institute it should be understood that the above is merely specific embodiment of the present invention; Be not limited to the present invention; All within spirit of the present invention and principle, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims

1. method of improving electrostatic discharge protection performance of silicon circuit in insulators; It is characterized in that; This method is employed in silicon-on-insulator SOI circuit and carries out static discharge ESD injection near the tagma of drain terminal or the place of drain terminal and boundary, tagma; Change the ESD puncture voltage of SOI circuit; And when ESD voltage arrives, open simultaneously between the promotion esd discharge pipe and between inner each grizzly bar of esd discharge pipe, the electric current lifting tagma current potential that produces during simultaneously through puncture, promotion colonizes in the bipolar junction transistor BJT bleed off electric current in the metal-oxide semiconductor (MOS) metal-oxide-semiconductor; Wherein, carry out adopting when ESD injects the wide-angle method for implanting at the SOI circuit near the tagma of drain terminal.

2. the method for improving electrostatic discharge protection performance of silicon circuit in insulators according to claim 1; It is characterized in that; Manage for N NMOS N-channel MOS N NMOS; Carry out ESD at the SOI circuit near the tagma of drain terminal and inject, make the part of puncture place, specifically comprise in tagma and drain terminal boundary:

When doing the tuned grid injection, revising back of the body grid implantation dosage and injecting energy is 1.0e ¹⁴/ cm ²And 65keV, puncture voltage is adjusted to 6 to 8V by the 12V of proper device; Inject influence in order to reduce ESD to internal circuit; Adopt twice grid to inject; Inject for the first time the demanding internal circuit of threshold voltage is injected; Remove photoresist then, clean, in advance roasting HMDS HMDS, gluing, employing increase newly one independently ESD inject reticle photoetching, development and check, and the pipe that is used for esd protection is carried out injection second time after roasting hard, implantation dosage and injection energy are 1.0e ¹⁴/ cm ², 65keV.

3. the method for improving electrostatic discharge protection performance of silicon circuit in insulators according to claim 2 is characterized in that,

Said photoetching adopt increase newly one independently ESD inject reticle, this ESD injects the pipe tagma that reticle will be used for esd protection and is designed to printing opacity, the zone design of other pipe is light tight;

Said injection adopts the boron ion as implanted dopant.

4. the method for improving electrostatic discharge protection performance of silicon circuit in insulators according to claim 1; It is characterized in that; For the NMOS pipe, carry out the ESD injection in the place that the drain terminal and the tagma of SOI circuit have a common boundary, keeping channel region has lower concentration; Help keeping higher BJT gain, specifically comprise:

For first kind of structure, to make grizzly bar and making between two processing steps of side wall and inject, implantation dosage and injection energy are 1.0e ¹⁴/ cm ²And 65keV; For second kind of structure, to make side wall and making between two processing steps of silicide and inject, implantation dosage and injection energy are 1.5e ¹⁴/ cm ²And 65keV, utilize high impurity concentration district of Impurities Scattering Effect generation when injecting, reduce and leak bulk breakdown voltage.

5. the method for improving electrostatic discharge protection performance of silicon circuit in insulators according to claim 1; It is characterized in that; For the NMOS pipe, it is to carry out ESD to inject in the position of doing an oxygen that the ESD injection is carried out in said tagma at the SOI circuit, and the field implantation dosage is revised in direct employing and energy is 1.5e ¹⁴/ cm ²And 65keV, the puncture voltage of reduction SOI circuit.

6. the method for improving electrostatic discharge protection performance of silicon circuit in insulators according to claim 5 is characterized in that, saidly directly the field implantation concentration is improved doing when injecting, and reaches the purpose that ESD injects.

7. according to each described method of improving electrostatic discharge protection performance of silicon circuit in insulators in the claim 1 to 6, it is characterized in that, this method further in the source/leakage part area carries out ESD and injects.

8. according to each described method of improving electrostatic discharge protection performance of silicon circuit in insulators in the claim 1 to 6, it is characterized in that this method further changes reticle, only the part of leaning on drain terminal is carried out the mode that ESD injects.

9. according to each described method of improving electrostatic discharge protection performance of silicon circuit in insulators in the claim 1 to 6; It is characterized in that; This method is when making ESD injection reticle; Mid line with each polysilicon grizzly bar is boundary, will lean on the domain of drain terminal part to keep, and leans on the layout design of source end parts to become light tight district.

10. according to each described method of improving electrostatic discharge protection performance of silicon circuit in insulators in the claim 1 to 6; It is characterized in that; This method further combines to promote the effect that ESD injects with silicide baffle plate SAB technology; After obtaining the ESD injecting structure, inject between two processing steps of formation silicide in source/leakages and to add silicide baffle plate SAB technology, at the drain terminal contact hole to one section N+ district that does not have silicide of formation between the leakage LDD structure of gently mixing up; Reach in the effect of drain terminal contact hole to a small resistor of serial connection between the LDD, maximum field squints to drain terminal contact hole direction when making device work.