CN114335182A - Embedded flash memory, semiconductor device structure and preparation method thereof - Google Patents
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Abstract
The invention provides an embedded flash memory, a semiconductor device structure and a preparation method thereof, wherein the device structure comprises: a first conductive type substrate; a second conductivity type well region in the first conductivity type substrate; a first conductivity type well region located within the second conductivity type well region; the grid structure is positioned on the first conductive type well region and comprises a grid dielectric layer and a first conductive type polycrystalline silicon layer positioned on the grid dielectric layer; the second conduction type source regions are positioned in the first conduction type well region and positioned at two sides of the grid structure; a first conductive type contact region located in the first conductive type well region and outside the second conductive type source region; and a second conductive type contact region located in the second conductive type well region. The invention can effectively improve the switching speed of the device, has smaller power consumption, can reduce the power consumption of the embedded flash memory to be below 100 muA/MHZ, and improves the reading speed to be above 30 nS.
Description
Technical Field
The invention belongs to the field of semiconductor integrated circuit design and manufacture, and particularly relates to an embedded flash memory, a semiconductor device structure and a preparation method thereof.
Background
In the current semiconductor industry, integrated circuit products can be divided into three major categories: analog circuits, digital circuits, and digital/analog hybrid circuits, where memory devices are an important type of digital circuit. In recent years, the development of embedded flash memories has been particularly rapid in memory devices. The embedded flash memory is mainly characterized in that the stored information can be kept for a long time under the condition of not powering on; and has the advantages of high integration level, high access speed, easy erasing and rewriting, and the like, thereby being widely applied to the fields of microcomputer, automatic control, and the like.
The read operation voltage of the embedded flash memory is shown in fig. 1, wherein the negative voltage circuit applied to the Select Gate (SG) is implemented by using a high voltage NMOS device having a floating gate structure, and since the device is a high voltage device, the switching process of the Select Gate (SG) from the voltage Vcc at the time of Unselected (SG) to the voltage-0.7 Vcc at the time of Selected (SG) during the read operation has a large power consumption, which is about 200 μ a/MHz, and a slow speed, which is about 50 nS. Therefore, the embedded flash memory has large power consumption and slow speed, which is disadvantageous for its application.
It should be noted that the above background description is only for the convenience of clear and complete description of the technical solutions of the present application and for the understanding of those skilled in the art. Such solutions are not considered to be known to the person skilled in the art merely because they have been set forth in the background section of the present application.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides an embedded flash memory, a semiconductor device structure and a method for manufacturing the same, which are used to solve the problem that the embedded flash memory has large power consumption and slow speed, which is unfavorable for the application of the embedded flash memory in the prior art.
To achieve the above and other related objects, the present invention provides a semiconductor device structure comprising: a first conductive type substrate; a second conductivity type well region in the first conductivity type substrate; a first conductivity type well region located within the second conductivity type well region; the grid structure is positioned on the first conduction type well region and comprises a grid dielectric layer and a first conduction type polycrystalline silicon layer positioned on the grid dielectric layer; the second conductive type source regions are positioned in the first conductive type well region and positioned at two sides of the grid structure; a first conductive type contact region located in the first conductive type well region and located outside the second conductive type source region; and a second conductive type contact region located in the second conductive type well region.
Optionally, the thickness of the gate dielectric layer is not greater than 100 angstroms.
Optionally, the thickness of the gate dielectric layer is 50-70 angstroms.
Optionally, the first conductivity type is P-type conductivity, and the second conductivity type is N-type conductivity.
Optionally, when a negative voltage is applied to the first conductivity type well region through the first conductivity type contact region, a PN junction formed by the first conductivity type well region and the second conductivity type well region is reverse biased to isolate the first conductivity type well region from the first conductivity type substrate.
Optionally, when a positive voltage is applied to the first conductivity type well region through the first conductivity type contact region, a PN junction formed by the first conductivity type well region and the second conductivity type well region is forward biased, and the second conductivity type well region is reverse biased with respect to the first conductivity type substrate, so that the first conductivity type well region is isolated from the first conductivity type substrate.
Optionally, shallow trench isolation structures are disposed between the second conductive type source region and the first conductive type contact region, and between the first conductive type contact region and the second conductive type contact region.
The invention also provides an embedded flash memory, which comprises the semiconductor device structure in any one of the above aspects, wherein the semiconductor device structure is used for applying negative voltage to the selection gate of the embedded flash memory.
Optionally, the power consumption of the embedded flash memory is less than or equal to 100 muA/MHZ, and the reading speed is greater than or equal to 30 nS.
The invention also provides a preparation method of the semiconductor device structure, which comprises the following steps: 1) providing a first conductive type substrate; 2) forming a second conductive type well region in the first conductive type substrate; 3) forming a first conductive type well region in the second conductive type well region; 4) forming a grid structure on the first conductive type well region, wherein the grid structure comprises a grid dielectric layer and a first conductive type polycrystalline silicon layer positioned on the grid dielectric layer; 5) forming a second conductive type source region in the first conductive type well region, wherein the second conductive type source region is positioned at two sides of the gate structure, and forming a second conductive type contact region in the second conductive type well region; 6) and forming a first conductive type contact region in the first conductive type well region, wherein the first conductive type contact region is positioned outside the second conductive type source region.
As described above, the embedded flash memory, the semiconductor device structure and the manufacturing method thereof of the present invention have the following beneficial effects:
the semiconductor device structure of the invention has a substrate of the first conductivity type, the well region of the second conductivity type and the triple-well structure of the well region of the first conductivity type; when the second conduction type well region applies negative voltage, a PN junction formed by the first conduction type well region and the second conduction type well region is reversely biased, so that the first conduction type well region is isolated from the first conduction type substrate; when a positive voltage is applied to the second conduction type well region, a PN junction formed by the first conduction type well region and the second conduction type well region is forward biased, and the second conduction type well region and the first conduction type substrate are reversely biased, so that the first conduction type well region and the first conduction type substrate are isolated. Therefore, the first conductivity type well region and the first conductivity type substrate can be effectively isolated, so that the potential reduction of the first conductivity type well region or the generation of leakage current is avoided, and the power consumption of the device is reduced.
The semiconductor device structure with the triple-well structure adopts the gate dielectric layer with smaller thickness to replace the traditional floating gate structure, can effectively improve the switching speed of the device, has smaller power consumption, can reduce the power consumption of the embedded flash memory to be below 100 muA/MHZ, and improves the reading speed to be above 30 nS.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is to be understood that the drawings in the following description are of some embodiments of the application only.
FIG. 1 is a voltage data diagram illustrating a read operation voltage of an embedded flash memory.
Fig. 2 to 6 are schematic structural diagrams of steps of a method for manufacturing a semiconductor device structure according to an embodiment of the present invention, wherein fig. 6 is a schematic structural diagram of a semiconductor device structure according to an embodiment of the present invention.
Element number description: 101 a first conductive type substrate, 102 a shallow trench isolation structure, 103 a second conductive type well region, 104 a first conductive type well region, 105 a second conductive type source region, 106 a first conductive type contact region, 107 a second conductive type contact region, 108 a gate dielectric layer, 109 a polysilicon layer and 110 a gate side wall.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
It should be emphasized that the term "comprises/comprising" when used herein, is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps or components.
Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments, in combination with or instead of the features of the other embodiments.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
The read operation voltage of the embedded flash memory is shown in fig. 1, wherein the negative voltage circuit applied to the Select Gate (SG) is implemented by using a high voltage NMOS device having a floating gate structure, and since the device is a high voltage device, the switching process of the Select Gate (SG) from the voltage Vcc at the time of Unselected (SG) to the voltage-0.7 Vcc at the time of Selected (SG) during the read operation has a large power consumption, which is about 200 μ a/MHz, and a slow speed, which is about 50 nS. Therefore, the embedded flash memory has large power consumption and slow speed, which is disadvantageous for its application.
In order to solve the above problem, as shown in fig. 5, the present embodiment provides a semiconductor device structure including: a first conductivity type substrate 101; a second conductivity type well region 103 in the first conductivity type substrate 101; a first conductivity type well region 104 located in the second conductivity type well region 103; a gate structure located on the first conductive type well region 104, including a gate dielectric layer 108 and a first conductive type polysilicon layer 109 located on the gate dielectric layer 108; second conductive type source regions 105 located in the first conductive type well region 104 and located at two sides of the gate structure; a first conductive type contact region 106 located in the first conductive type well region 104 and located outside the second conductive type source region 105; a second conductive type contact region 107 is located within the second conductive type well region 103. In this embodiment, the first conductive type is P-type conductive, and the second conductive type is N-type conductive.
In one embodiment, the first conductive type substrate 101 may be a silicon substrate, a germanium substrate, a silicon carbide substrate, a iii-v compound substrate, an insulating substrate (such as silicon dioxide, sapphire), a metal substrate, an organic polymer substrate, or the like, or may be a silicon-on-insulator (SOI), a germanium-on-insulator (ge-on-insulator), a silicon germanium-on-insulator (ge-on-insulator), or the like, or may be a stack of the above substrates formed according to requirements. In this embodiment, the first conductive type substrate 101 may be a P-type conductive silicon substrate, and the doping ions in the silicon substrate may be boron with a doping concentration of 1E15 atom/cm3~9E15 atom/cm3。
In one embodiment, the gate dielectric layer 108 is a silicon dioxide layer having a thickness of no greater than 100 angstroms. Preferably, the thickness of the gate dielectric layer 108 is 50 to 70 angstroms. The semiconductor device structure with the triple-well structure adopts the gate dielectric layer 108 with smaller thickness to replace the traditional floating gate structure, can effectively improve the switching speed of the device, has smaller power consumption, can reduce the power consumption of the embedded flash memory to be below 100 muA/MHZ, and improves the reading speed to be above 30 nS.
In one embodiment, the first conductive type substrate 101 is a P-type substrate, the second conductive type well region 103 is an N-type well region, the first conductive type well region 104 is a P-type well region, and when a negative voltage is applied to the first conductive type well region 104 through the first conductive type contact region 106, a PN junction formed by the first conductive type well region 104 and the second conductive type well region 103 is reverse biased, so that the first conductive type well region 104 is isolated from the first conductive type substrate 101.
In one embodiment, the first conductive type substrate 101 is a P-type substrate, the second conductive type well region 103 is an N-type well region, the first conductive type well region 104 is a P-type well region, when a positive voltage is applied to the first conductive type well region 104 through the first conductive type contact region 106, a PN junction formed by the first conductive type well region 104 and the second conductive type well region 103 is forward biased, and the second conductive type well region 103 is reverse biased from the first conductive type substrate 101, so that the first conductive type well region 104 is isolated from the first conductive type substrate 101.
In one embodiment, the doping ion of the second conductive well 103 may be phosphorus or arsenic, and the doping concentration may be 1E15 atom/cm3~9E16atom/cm3The doping ion of the first conductivity type well 104 may be boron, etc., and the doping concentration may be 1E15 atom/cm3~9E16atom/cm3. The doping ions of the second conductive type source region 105 may be phosphorus, arsenic, or the like, and the doping concentration may be 1E16atom/cm3~1E19atom/cm3The dopant ions of the first conductive type contact region 106 may be boron, etc., and the dopant concentration may be 5E16atom/cm3~9E19atom/cm3The doping ion of the second conductive type contact region 107 may be phosphorus or arsenic, and the doping concentration may be 5E16atom/cm3~9E19atom/cm3。
In one embodiment, shallow trench isolation structures 102 are disposed between the second conductive type source region 105 and the first conductive type contact region 106, and between the first conductive type contact region 106 and the second conductive type contact region 107. The depth of the shallow trench isolation structure 102 may be greater than the depth of the first conductivity-type well region 104, equal to the depth of the first conductivity-type well region 104, or less than the depth of the first conductivity-type well region 104.
In one embodiment, the semiconductor device structure further comprises an insulating layer covering the surface of the device structure, the insulating layer having a source contact window, a gate contact window, a drain contact window, a window of the first conductive type contact region 106 and a window of the second conductive type contact region 107, electrode materials being formed on the insulating layer and in the windows, the electrode materials being patterned in actual electrical connection to form corresponding electrodes.
The present embodiment also provides an embedded flash memory including the semiconductor device structure according to any one of the above aspects, wherein the semiconductor device structure is configured to apply a negative voltage to a select gate of the embedded flash memory.
In one embodiment, the embedded flash memory has a power consumption less than or equal to 100 μ A/MHZ and a read speed greater than or equal to 30 nS.
As shown in fig. 2 to fig. 5, the present embodiment further provides a method for manufacturing a semiconductor device structure, including the steps of:
as shown in fig. 2, step 1) is first performed to provide a first conductivity type substrate 101.
In one embodiment, the first conductive type substrate 101 may be a silicon substrate, a germanium substrate, a silicon carbide substrate, a iii-v compound substrate, an insulating substrate (e.g., silicon dioxide, sapphire), a metal substrate, an organic polymer substrate, or the like, or may be a silicon-on-insulator (SOI), a germanium-on-insulator (ge-on-insulator), or the likeAnd sige-on-insulator, etc., and may be a stack of the above-described various substrates formed as required. In this embodiment, the first conductive type substrate 101 may be a P-type conductive silicon substrate, and the doping ions in the silicon substrate may be boron with a doping concentration of 1E15 atom/cm3~9E15 atom/cm3。
In one embodiment, further comprising forming shallow trench isolation structures 102 in the first conductivity type substrate 101.
As shown in fig. 3, step 2) is then performed to form a second conductive type well region 103 in the first conductive type substrate 101.
In one embodiment, the second conductive well 103 may be formed in the first conductive substrate 101 by an ion implantation process, the second conductive well 103 may be doped with phosphorus or arsenic, and the doping concentration may be 1E15 atom/cm3~9E16atom/cm3。
As shown in fig. 4, step 3) is then performed to form a first conductivity type well region 104 in the second conductivity type well region 103.
In one embodiment, the first conductivity-type well region 104 may be formed in the second conductivity-type well region 103 by an ion implantation process, wherein the first conductivity-type well region 104 may be doped with boron or the like at a doping concentration of 1E15 atom/cm3~9E16atom/cm3。
As shown in fig. 5, step 4) is performed to form a gate structure on the first conductive type well region 104, where the gate structure includes a gate dielectric layer 108 and a first conductive type polysilicon layer 109 on the gate dielectric layer 108.
Specifically, a gate dielectric layer 108 may be formed on the first conductive type well region 104 through a thermal oxidation process, a polysilicon layer 109 may be formed on the gate dielectric layer 108 through a chemical vapor deposition process, and then a required gate structure may be formed through a patterning process through a photolithography process and an etching process. In this embodiment, a step of forming a gate sidewall spacer 110 on the sidewall of the gate structure is further included, and the gate sidewall spacer 110 may be silicon nitride, silicon dioxide, or a combination thereof.
As shown in fig. 6, step 5) and step 6) are then performed to form a second conductive type source region 105 in the first conductive type well region 104, where the second conductive type source region 105 is located at two sides of the gate structure, and a second conductive type contact region 107 is formed in the second conductive type well region 103; a first conductive type contact region 106 is formed in the first conductive type well region 104, and the first conductive type contact region 106 is located outside the second conductive type source region 105.
In one embodiment, the second conductive type source region 105, the first conductive type contact region 106 and the first conductive type contact region 106 may be formed by a pattern mask and an ion implantation process, the doping ions of the second conductive type source region 105 may be phosphorus, arsenic or the like, and the doping concentration may be 1E16atom/cm3~1E19atom/cm3The dopant ions of the first conductive type contact region 106 may be boron, etc., and the dopant concentration may be 5E16atom/cm3~9E19atom/cm3The doping ion of the second conductive type contact region 107 may be phosphorus or arsenic, and the doping concentration may be 5E16atom/cm3~9E19atom/cm3。
As described above, the embedded flash memory, the semiconductor device structure and the manufacturing method thereof of the present invention have the following beneficial effects:
the semiconductor device structure of the invention has a triple well structure of a first conductive type substrate 101, a second conductive type well region 103 and a first conductive type well region 104; when a negative voltage is applied to the second conductivity type well region 103, a PN junction formed between the first conductivity type well region 104 and the second conductivity type well region 103 is reverse biased to isolate the first conductivity type well region 104 from the first conductivity type substrate 101; when a positive voltage is applied to the second conductivity type well region 103, a PN junction formed between the first conductivity type well region 104 and the second conductivity type well region 103 is forward biased, and the second conductivity type well region 103 and the first conductivity type substrate 101 are reverse biased, so that the first conductivity type well region 104 is isolated from the first conductivity type substrate 101. Therefore, the present invention can effectively isolate the first conductivity type well region 104 from the first conductivity type substrate 101 to avoid a decrease in the potential of the first conductivity type well region 104 or generation of a leakage current, thereby reducing power consumption of the device.
The semiconductor device structure with the triple-well structure adopts the gate dielectric layer 108 with smaller thickness to replace the traditional floating gate structure, can effectively improve the switching speed of the device, has smaller power consumption, can reduce the power consumption of the embedded flash memory to be below 100 muA/MHZ, and improves the reading speed to be above 30 nS.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A semiconductor device structure, comprising:
a first conductive type substrate;
a second conductivity type well region in the first conductivity type substrate;
a first conductivity type well region located within the second conductivity type well region;
the grid structure is positioned on the first conduction type well region and comprises a grid dielectric layer and a first conduction type polycrystalline silicon layer positioned on the grid dielectric layer;
the second conductive type source regions are positioned in the first conductive type well region and positioned at two sides of the grid structure;
a first conductive type contact region located in the first conductive type well region and located outside the second conductive type source region;
and a second conductive type contact region located in the second conductive type well region.
2. The semiconductor device structure of claim 1, wherein: the thickness of the gate dielectric layer is not more than 100 angstroms.
3. The semiconductor device structure of claim 2, wherein: the thickness of the gate dielectric layer is 50-70 angstroms.
4. The semiconductor device structure of claim 1, wherein: the first conductivity type is P-type conductivity and the second conductivity type is N-type conductivity.
5. The semiconductor device structure of claim 4, wherein: when a negative voltage is applied to the first conductive type well region through the first conductive type contact region, a PN junction formed by the first conductive type well region and the second conductive type well region is reverse biased to isolate the first conductive type well region from the first conductive type substrate.
6. The semiconductor device structure of claim 4, wherein: when a positive voltage is applied to the first conductive type well region through the first conductive type contact region, a PN junction formed by the first conductive type well region and the second conductive type well region is forward biased, and the second conductive type well region and the first conductive type substrate are reverse biased, so that the first conductive type well region is isolated from the first conductive type substrate.
7. The semiconductor device structure of claim 1, wherein: shallow trench isolation structures are arranged between the second conductive type source region and the first conductive type contact region and between the first conductive type contact region and the second conductive type contact region.
8. An embedded flash memory comprising the semiconductor device structure of any one of claims 1 to 7, wherein the semiconductor device structure is configured to apply a negative voltage to a select gate of the embedded flash memory.
9. The embedded flash memory of claim 8, wherein: the power consumption of the embedded flash memory is less than or equal to 100 muA/MHZ, and the reading speed is greater than or equal to 30 nS.
10. A method for fabricating a semiconductor device structure according to any one of claims 1 to 7, comprising the steps of:
1) providing a first conductive type substrate;
2) forming a second conductive type well region in the first conductive type substrate;
3) forming a first conductive type well region in the second conductive type well region;
4) forming a grid structure on the first conductive type well region, wherein the grid structure comprises a grid dielectric layer and a first conductive type polycrystalline silicon layer positioned on the grid dielectric layer;
5) forming a second conductive type source region in the first conductive type well region, wherein the second conductive type source region is positioned at two sides of the gate structure, and forming a second conductive type contact region in the second conductive type well region;
6) and forming a first conductive type contact region in the first conductive type well region, wherein the first conductive type contact region is positioned outside the second conductive type source region.
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