KR20110071198A - Finfet type flash memory of having blocking dielectric films of various different thickness - Google Patents

Abstract

PURPOSE: An FinFET type flash memory with a blocking dielectric film of a different thickness is provided to change the thickness of a blocking dielectric film arranged between a charge capturing layer and a control gate, thereby reducing the load of a process due to a step between adjacent gate structures. CONSTITUTION: A Fin channel is formed on a substrate(10). A first gate structure(100) and a second gate structure(200) are formed on the upper part and the side of the Fin channel. The first gate structure is composed of a first side gate(110) and a second side gate(120) around the Fin channel. The second gate structure is composed of a third side gate(210) and a fourth side gate(220) around the Fin channel. The third side gate and the fourth side gate are electrically connected through a second connection gate(240) on a second separation insulation film(230).

Description

FinFET Type Flash Memory of having Blocking Dielectric Films of Various Different Thickness}

The present invention relates to a flash memory, and more particularly to a flash memory having a three-dimensional pinpet structure.

Memory devices have been miniaturized and highly integrated with the development of semiconductor manufacturing process technology. In particular, a flash memory representing a nonvolatile memory device uses polycrystalline silicon or the like as a floating gate to store or erase charges. However, even if miniaturization or integration is in progress, the cell transistor should operate normally. As the length of the gate is reduced, the distance between the source and the drain is shortened, and the normal operation is caused by the short channel effect. It becomes difficult to guarantee. In addition, the voltage through which punch-through occurs is reduced, thereby increasing the leakage current of the device. Increasing leakage current is an obstacle to the implementation of low power devices.

When the proportional-reduction process of the above-described memory device is intensified, the transistor does not operate in the saturation region but continuously operates in the linear region despite the increase in the drain voltage. This lowers the operating characteristics of the device.

In order to overcome this problem, the conventional devices have been studied as a multilevel device that distinguishes the amount of trapped electrons and defines each memory state with the aim of increasing memory capacity and storage efficiency per cell. However, in the case of a multilevel device, there is a limit in accurately sensing the amount of electrons, so fabrication of the device in the multilevel method causes an error in a read operation.

An object of the present invention for solving the above problems is to provide a structure of a pin-pet type flash memory that can implement a multi-bit.

The present invention for achieving the above object, the pin channel protruding from the substrate; A first gate structure formed across the fin channel and having a side blocking dielectric layer of a first thickness; And a second gate structure formed across the fin channel and adjacent to the first gate structure and having a side blocking dielectric layer having a second thickness greater than the first thickness.

According to the present invention described above, one unit cell constituting the flash memory may implement four states. Therefore, at least two bits of data storage and reading operations can be performed per unit cell. In addition, since the thickness of the blocking dielectric layer disposed between the charge trapping layer and the control gate is changed without changing the thickness of the tunneling dielectric layer in the manufacturing process, the burden of the process caused by the step between the adjacent gate structures can be reduced. .

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Like reference numerals are used for like elements in describing each drawing.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

Example

1 is a perspective view showing a flash memory according to a preferred embodiment of the present invention.

Referring to FIG. 1, two gate structures 100 and 200 are formed on the top and side surfaces of the fin channel 20 formed on the substrate 10. That is, the first gate structure 100 and the second gate structure 200 are formed along the fin channel 20. The two gate structures 100 and 200 are formed on the field oxide layer 30 and have a shape surrounding the fin channel 20.

The first gate structure 100 includes a first side gate 110 and a second side gate 120 around the fin channel 20. The first side gate 110 and the second side gate 120 are electrically connected to each other through the first connection gate 140 disposed on the first isolation insulating layer 130.

The first side gate 110 includes a first side tunneling dielectric layer 111, a first side charge trapping layer 113, a first side blocking dielectric layer 115, and a first side control gate 117. The second side gate 120 corresponding thereto is formed to face the first side gate 110 around the fin channel 20, and the second side tunneling dielectric layer 121 and the second side charge trap layer 123 are formed. And a second side blocking dielectric layer 125 and a second side control gate 127. The first side tunneling dielectric layer 111 described above has the same material and the same thickness as the second side tunneling dielectric layer 121. This applies equally to other films. That is, the material and the thickness of the components of the first side gate 110 and the second side gate 120 facing each other are the same as the film quality corresponding to each other.

In particular, the film constituting the side gates 110 and 120 of the first gate structure 100 are separated by the first isolation insulating layer 130 except for the side control gates 117 and 127.

The second gate structure 200 formed adjacent to the first gate structure 100 along the fin channel 20 may include the third side gate 210 and the fourth side gate 220 around the fin channel 20. Have The third side gate 210 and the fourth side gate 220 are electrically connected to each other through the second connection gate 240 on the second isolation insulating layer 230.

The third side gate 210 has a third side tunneling dielectric layer 211, a third side charge trapping layer 213, a third side blocking dielectric layer 215, and a third side control gate 217. The fourth side gate 220 corresponding to the third side gate 210 faces the third side gate 210 around the fin channel 20, and the fourth side tunneling dielectric layer 221 and the fourth side gate. The charge trapping layer 223 has a fourth side blocking dielectric layer 225 and a fourth side control gate 227. The third side tunneling dielectric layer 211 corresponds to the fourth side tunneling dielectric layer 221, and the third side charge trapping layer 213 corresponds to the fourth side charge trapping layer 223 and the third side blocking dielectric layer 215 may correspond to the fourth side blocking dielectric layer 225, and the third side control gate 217 may correspond to the fourth side control gate 227. In addition, each film quality has the same thickness and material as the corresponding film quality.

In particular, the third side gate dielectric layer 215 and the fourth side gate dielectric layer 225 have different thicknesses from those of the first side gate dielectric layer 115 and the second side gate dielectric layer 125.

FIG. 2 is a cross-sectional view of the first gate structure of the flash memory illustrated in FIG. 1 taken along the line X-X '.

Referring to FIG. 2, the fin channel 20 is provided to protrude on the substrate 10. In addition, the field oxide layer 30 is provided on the upper surface of the substrate 10 and the side surfaces of the fin channels 20. Both side surfaces of the fin channel 20 are provided with a first side gate 110 and a second side gate 120.

The first side gate 110 has a first side tunneling dielectric layer 111, a first side charge trapping layer 113, a first side blocking dielectric layer 115, and a first side control gate 117, and a second side side. The gate 120 has a second side tunneling dielectric layer 121, a second side charge trapping layer 123, a second side blocking dielectric layer 125, and a second side control gate 127. However, the first isolation insulating layer 130 is formed on the fin channel 20, and the first control gates 140 are provided on the first isolation insulating layer 130, so that side control gates disposed on both sides thereof ( 117, 127 are electrically connected.

The first side blocking dielectric layer 115 and the second side blocking dielectric layer 125 described above have a first thickness. That is, the two side blocking dielectric layers 115 and 125 having the first thickness differ from the side blocking dielectric layers 215 and 225 provided in the second gate structure 200.

FIG. 3 is a cross-sectional view of the second gate structure of the flash memory illustrated in FIG. 1 taken along the line X-X '.

Referring to FIG. 3, a structure similar to the structure shown in FIG. 2 is provided. However, the thicknesses of the two side blocking dielectric layers 215 and 225 are different from those of the side blocking dielectric layers 115 and 125 illustrated in FIG. 2.

In FIG. 3, the second gate structure 200 is formed adjacent to the first gate structure 100 along the fin channel 20 and has a third side gate 210 and a fourth side gate 220. The third side gate 210 faces the fourth side gate 220 about the fin channel 20.

The third side gate 210 has a third side tunneling dielectric layer 211, a third side charge trapping layer 213, a third side blocking dielectric layer 215, and a third side control gate 217. The fourth side gate 220 has a fourth side tunneling dielectric layer 221, a fourth side charge trapping layer 223, a fourth side blocking dielectric layer 225, and a fourth side control gate 227. A second isolation insulating layer 230 is formed on the fin channel 20, and a second connection gate 240 is provided on the second isolation insulating layer 230 to form the third side control gate 217 and the fourth side surface. The control gate 227 is electrically connected.

The third side blocking dielectric layer 215 and the fourth side blocking dielectric layer 225 described above have a second thickness. That is, the side blocking dielectric layers 115 and 125 of the first gate structure 100 may be different from the side blocking dielectric layers 215 and 225 of the second gate structure 200. The second thickness may have a value greater than the first thickness.

4 is a top perspective view of the flash memory illustrated in FIG. 1.

Referring to FIG. 4, it can be seen that the thicknesses of the side blocking dielectric layers 115 and 125 of the first gate structure 100 are smaller than the thicknesses of the side blocking dielectric layers 215 and 225 of the second gate structure 200. have.

In addition, in each gate structure 100 and 200, an isolation insulating layer is provided on an upper portion of the fin channel 20, and connection gates electrically connecting side control gates to each other are provided on an isolation insulating layer. In addition, the side tunneling dielectric layers 111, 121, 211, and 221 and the side charge trapping layers 113, 123, 213, and 223 of the first gate structure 100 and the second gate structure 200 may have the same thickness and material, respectively. It is preferable to have. In addition, the outer edges of the two gate structures 100 and 200 in the fin channel 20 region are defined as a source and a drain.

5 to 8 are perspective views illustrating a method of manufacturing the flash memory shown in FIG. 1 according to a preferred embodiment of the present invention.

Referring to FIG. 5, the surface of the substrate 10 is partially etched to form the fin channel 20 region. This is performed by a conventional lithography process in which photoresist is applied to the surface of the smooth semiconductor substrate 10 and patterned to open the left and right portions of the fin channel 20. When etching is performed using a photoresist pattern in which left and right portions of the fin channel 20 are opened as an etching mask, the fin channel 20 remains in a protruding shape.

Subsequently, field oxide films 30 are formed on the left and right portions of the fin channel 20. Formation of the field oxide film 30 is accomplished by a conventional deposition process and removal of the oxide film on the upper and side surfaces of the fin channel 20.

Referring to FIG. 6, the tunneling dielectric layer 11, the charge trapping layer 13, and the first blocking dielectric layer 14 are sequentially formed on the entire surface of the substrate 10 on which the field oxide layer 30 is formed. In particular, the first blocking dielectric layer 14 is preferably formed only in the second region 22 where the second gate structure is formed. The first blocking dielectric layer 14 formed only in the second region 22 may have an opening of the first region 21 in which the first gate structure is formed by a conventional photolithography process and a blocking dielectric layer formed in the first region 21. Is removed and the first blocking dielectric film 14 is left.

Referring to FIG. 7, a second blocking dielectric layer 16 is formed on the front surface of the structure illustrated in FIG. 6. Therefore, the thickness of the blocking dielectric film of the first region 21 is smaller than the thickness of the blocking dielectric film of the second region 22.

In addition to the method illustrated in FIGS. 6 and 7, there are various methods of varying the thickness of the blocking dielectric layer in the first region and the thickness of the blocking dielectric layer in the second region. For example, a blocking dielectric layer may be applied over the previously formed charge trapping layer, and the blocking dielectric layer of the second region may be partially etched so that the blocking dielectric layer of the second region remains, but has a different thickness than that of the first region. .

Referring to FIG. 8, a separation insulating layer 40 is formed on the structure illustrated in FIG. 7.

First, the blocking dielectric layers 15A and 15B and a buffer layer (not shown) of a different material are coated on the front surface of the structure illustrated in FIG. 7, and then the upper portion of the fin channel 20 is opened by chemical mechanical polishing. After the isolation insulating film 40 is formed on the open fin channel 20, the film quality on the side of the fin channel 20 is etched to expose the blocking dielectric layers 15A and 15B on the fin channel 20 side. Therefore, the isolation insulating film 40 has a shape covering the upper portion of the fin channel 20. The material of the isolation insulating film 40 may be any material as long as it has a non-conductive material.

In addition, the isolation insulating film may be entirely coated on the structure illustrated in FIG. 7, and only the isolation insulating film on the upper fin channel may be left using a conventional photolithography process. When the above process is performed, the tunneling dielectric layer, the charge trapping layer, and the blocking dielectric layer on the fin channel may remain.

Subsequently, the control gate layer 50 is formed on the exposed blocking dielectric films 15A and 15B and the isolation insulating film 40. The control gate layer 50 is formed on the isolation dielectric layer 40 and on the blocking dielectric layers 15A and 15B formed on the left and right sides of the fin channel 20. The control gate layer 50 may be made of polycrystalline silicon, metal, conductive metal nitride, or conductive oxide.

Subsequently, each gate structure is separated by etching the control gate layer 50 to form the first gate structure 100 and the second gate structure 200 in the second region. Through the above-described process, the flash memory of FIG. 1 is formed.

That is, as shown in FIG. 1, an oxide-nitride-oxide (ONO) structure is formed in the first gate structure 100 formed on the side of the fin channel 20, and ONO also in the second gate structure 200. The structure is formed.

9 is a graph showing the amount of charge trapped when performing a program operation according to a preferred embodiment of the present invention.

The program operation is an operation for trapping charge in the channel region at the interface of the charge trapping layer.

As illustrated in FIG. 1, a program operation may be performed by applying an independent program voltage Vpgm to two gate structures provided in one unit cell.

The data of FIG. 9 shows that the lateral tunneling oxide film is made of silicon oxide, and its thickness is equal to 2 nm in the two gate structures. In addition, the charge trapping layer was composed of 4 nm thick silicon nitride. The first and second side blocking dielectric films of the first gate structure were set to have a thickness of 6 nm as silicon oxide, and the third and fourth side blocking dielectric films of the second gate structure were set to 7 nm as silicon oxide. In addition, the side control gates were set to aluminum, which is a conductive metal. 12V was supplied to the control gates at the program voltage Vpgm which traps the charge.

State '11' refers to the erased state. This refers to a state in which no charge is substantially trapped at the interface of the side charge trapping layer. Therefore, the trapped amount of charge also appears as zero on the graph.

State '10' is a state in which the program voltage Vpgm is applied only to the second gate structure. Therefore, the charge amount of the electrons trapped in the side charge trapping layer is about 2 * 10 ^-16 C / um.

In addition, the state '01' is a case where the program voltage Vpgm is applied only to the first gate structure. The amount of electrons trapped in the lateral charge trap layer by the program voltage Vpgm applied only to the first gate structure is about 2.5 * 10 ^-16 C / um.

Then, the state '00' is a case where the program voltage Vpgm is applied to the two gate structures. The side charge trapping layers in the two gate castings trap electrons, and the amount of trapped charge is about 1.2 * 10 ^-15 C / um.

Thus, it can be seen that the unit cell has four states of charge trapping operations. This means that the threshold voltage of four states is implemented by the program operation for the unit cell, and the unit cell can store 2 bits of data.

FIG. 10 is a graph showing drain current for each state disclosed in FIG. 9 according to a preferred embodiment of the present invention.

Referring to FIG. 10, each state illustrated in FIG. 9 is implemented to program predetermined data and then apply a read voltage to side control gates. As the read voltage increases, the drain current increases approximately with the state. However, the drain current can be regarded as the threshold voltage for each state as the inflection point that suddenly increases from zero. In FIG. 10, when the read voltage is set to 4V to 6V, a difference in drain current appears according to each state, and the data programmed in the unit cell can be read using the difference in current.

As described above, the unit cell of the flash memory according to the present invention has two gate structures, and has side blocking dielectric layers having different thicknesses, thereby storing four states, thereby storing two bits of data. Can be. In addition, since the current flowing through the fin channels on both sides of the two gate structures is controlled through the two gate structures, it is possible to solve a grouping effect, which is a problem when the semiconductor element is proportionally reduced. This is due to the distribution of current flowing in the platter type to both sides of the fin channel.

In addition, as can be seen in FIG. 9, when viewing the graph of the transferred electrons, it can be seen that the amount of electrons captured is saturated in about 1 * 10 ⁻⁵ seconds. This means that the change of the threshold voltage according to the trapping of electrons is performed at a very fast time. That is, according to the present invention, it is possible to ensure fast program time.

Even in the manufacturing process, the present invention achieves a change in the thickness of the blocking dielectric film, and thus has many advantages over the manufacturing process inducing a change in the thickness of the tunneling dielectric film. For example, when the thickness of the tunneling dielectric layer varies for each gate structure, it is difficult to secure the characteristics of the tunneling dielectric layer. In addition, in the process of forming the charge trapping layer, the blocking dielectric layer, and the control gate, there is a difficulty in the manufacturing process because the film quality of the adjacent gate structures all have steps. However, in the present invention, since no step occurs between the tunneling dielectric layer and the charge trapping layer in the manufacturing process, reliability of the characteristics of the unit cell can be improved.

1 is a perspective view showing a flash memory according to a preferred embodiment of the present invention.

FIG. 2 is a cross-sectional view of the first gate structure of the flash memory illustrated in FIG. 1 taken along the line X-X '.

FIG. 3 is a cross-sectional view of the second gate structure of the flash memory illustrated in FIG. 1 taken along the line X-X '.

4 is a top perspective view of the flash memory illustrated in FIG. 1.

5 to 8 are perspective views illustrating a method of manufacturing the flash memory shown in FIG. 1 according to a preferred embodiment of the present invention.

9 is a graph showing the amount of charge trapped when performing a program operation according to a preferred embodiment of the present invention.

FIG. 10 is a graph showing drain current for each state disclosed in FIG. 9 according to a preferred embodiment of the present invention.

Claims (7)

A fin channel protruding from the substrate; A first gate structure formed across the fin channel and having a side blocking dielectric layer of a first thickness; And And a second gate structure formed across said fin channel and adjacent said first gate structure, said second gate structure having a side blocking dielectric layer having a second thickness greater than said first thickness. The method of claim 1, wherein the first gate structure, A first side gate disposed at one side of the fin channel; And A second side gate disposed on the other side opposite to the first side gate, And the first side gate and the second side gate are separated by a first isolation insulating layer formed on the fin channel and electrically connected to each other through a first connection gate on the first isolation insulating layer. The method of claim 2, wherein the first side gate, A first side tunneling dielectric layer formed on a side of the fin channel; A first side charge trapping layer formed on a side of the first side tunneling dielectric layer; A first side blocking dielectric layer formed on a side of the first side charge trap layer and having the first thickness; And A first side control gate formed on a side of the first side blocking dielectric layer, The second side gate, A second side tunneling dielectric layer formed on a side of the fin channel; A second side charge trapping layer formed on a side of the second side tunneling dielectric layer; A second side blocking dielectric layer formed on a side of the second side charge trap layer and having the first thickness; And And a second side control gate formed at a side of the second side blocking dielectric layer. The flash memory of claim 3, wherein the first side control gate is electrically connected to the second side control gate through the first connection gate. The method of claim 1, wherein the second gate structure, A third side gate disposed at one side about the fin channel; And A fourth side gate disposed on the other side facing the third side gate, And the third side gate and the fourth side gate are separated by a second isolation insulating layer formed on the fin channel, and electrically connected to each other through a second connection gate on the second isolation insulating layer. The method of claim 5, wherein the third side gate, A third side tunneling dielectric layer formed on a side of the fin channel; A third side charge trap layer formed on a side of the third side tunneling dielectric layer; A third side blocking dielectric layer formed on a side of the third side charge trap layer and having the second thickness; And A third side control gate formed on a side of the third side blocking dielectric layer, The fourth side gate, A fourth side tunneling dielectric layer formed on a side of the fin channel; A fourth side charge trap layer formed on a side of the fourth side tunneling dielectric layer; A fourth side blocking dielectric layer formed on a side of the fourth side charge trap layer and having the second thickness; And And a fourth side control gate formed at a side of the fourth side blocking dielectric layer. The flash memory of claim 6, wherein the third side control gate is electrically connected to the fourth side control gate through the second connection gate.

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