KR100565757B1 - Flash memory device and Fabricating method for the same - Google Patents

Abstract

The present invention relates to a flash memory device for improving the integration of a silicon-oxide-nitride-oxide-silicon (2S) SONOS cell and a method of manufacturing the same. An ONO film on the semiconductor substrate, a threshold voltage control ion implantation layer in the semiconductor substrate surface below the ONO film, a word line and a selection gate formed on the ONO film with a first region interposed therebetween; Insulating film sidewalls formed on both sides of the selection gate, a first impurity region in the surface of the semiconductor substrate of the first region, and a second impurity region in the surface of the semiconductor substrate of the second region having the first region and the word line interposed therebetween. And a third impurity region in the surface of the semiconductor substrate of the third region sandwiching the first region and the selection gate.

2T SONOS Cells, CD, Overlay, Density

Description

Flash memory device and fabrication method thereof {Flash memory device and Fabricating method for the same}

1 is a plan view of a 2-T SONOS cell according to the prior art;

FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG. 1.

3A to 3I are cross-sectional views of a manufacturing process of a 2T SONOS cell according to the prior art

4 is a cross-sectional view of a 2T SONOS cell in accordance with an embodiment of the invention.

5A to 5H are cross-sectional views of a manufacturing process of a 2T SONOS cell according to an embodiment of the present invention.

** Description of the symbols for the main parts of the drawings **

WL: word line SG: select gate

31 semiconductor substrate 32 pad oxide film

33: ONO film 34: oxide film

35, 36, 37: low concentration impurity region

38, 39: insulating film sidewall

40, 41. 42: high concentration impurity region

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device, and more particularly, to a flash memory device and a method of manufacturing the same for improving the integration degree of a 2T (Silicon-Oxide-Nitride-Oxide-Silicon) cell.

The flash memory device is a nonvolatile memory device capable of high-speed electrical erasing while not only maintaining information stored in a memory cell even when power is not supplied, but also being mounted on a circuit board. Flash memory technology has continued to evolve while improving the cell structure in various forms. These various cell types include stacked gate cells, split gate cells, source side injection cells, and many other cells of other structures.

The stack gate cell has a floating gate and a control gate stacked in this order, and electrons are injected into the floating gate using CHEI (Channel Hot Electron Injection) to be programmed and programmed. It is erased by extracting electrons that have been injected into the floating gate using tunneler-nordheim tunneling. The stack gate cell is most commonly used as a unit cell of a flash memory device because of its small size, but has a disadvantage of being vulnerable to an over-erase problem.

The over-erase problem occurs when the floating gate is excessively discharged during the erase operation on the stack gate cell. The threshold voltage of an overcharged cell represents a negative value. Therefore, there is a problem that a current flows even when a cell is not selected, that is, a read voltage is not applied to the control gate.

In order to solve this over erasure problem, two structures of cells have been introduced.

One is a 2-T cell and the other is a split gate cell.

In a 2-T cell, a select gate was employed. That is, when the cell is not selected, leakage current due to the floating gate in which the selection gate is excessively discharged is prevented. In the split gate cell, an over-raise problem has been solved by using a select gate channel under the control gate. That is, the select gate region prevents leakage current from the floating gate channel located under the over discharged floating gate.

Hereinafter, a 2-T SONOS cell according to the prior art will be described with reference to the accompanying drawings.

1 is a plan view of a 2-T SONOS cell according to the prior art, and FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG. 1.

As shown in FIGS. 1 and 2, a 2T SONOS cell according to the related art is arranged side by side with a SONOS gate transistor having a gate of a word line WL arranged in one direction, and the word line WL. And a select gate transistor (B) having a select gate SG as a gate.

The SONOS gate transistor A is formed in a tunnel oxide-trap nitride-block oxide (ONO) film 14 formed on the semiconductor substrate 11 and in the semiconductor substrate 11 under the ONO film 14. Threshold voltage control ion injection layer (B). The trap nitride layer of the ONO film 13 is a means for storing electric charges, and the word line WL on the ONO film 13 is a means for inducing electron traps in the trap nitride film.

The word line WL is positioned on one region of the ONO layer 13, and an oxide layer 16 is formed on a surface of the word line WL, and on both sides of the word line WL. An insulating film sidewall 20 exists with the oxide film 16 interposed therebetween.

A low concentration source / drain region 17/18 of a SONOS gate transistor is formed in the surface of the semiconductor substrate 11 below the insulating film sidewall 20, and the semiconductor substrate 11 on both sides of the insulating film sidewall 16 is formed. The high concentration source / drain regions 22/23 of the SONOS gate transistor A are formed in the surface.

On the other hand, the selection gate transistor (b) uses the low concentration source region 17 and the high concentration source region 22 of the SONOS gate transistor (a) as the low concentration drain region and the high concentration drain region, respectively, and the channel region therebetween. And a low concentration source region 19 and a high concentration source region 24.

A gate oxide film 15 and a select gate SG are present on the channel region, and an oxide film 16 is formed on the surface of the semiconductor substrate 11 on both sides of the select gate SG and the select gate SG. . The insulating film sidewalls 21 are formed on both sides of the selection gate SG with the oxide film 16 interposed therebetween.

The low concentration source / drain regions 19/17 of the selection gate transistor I are located in the surface of the semiconductor substrate 11 under the insulating film sidewall 21, and the high concentration source / drain regions of the selection gate transistor I are selected. The 24/22 is positioned in the surface of the semiconductor substrate 11 on both sides of the insulating film sidewall 21.

In addition, wirings are formed in the high concentration drain region 23 of the word line WL, the selection gate SG, and the SONOS gate transistor A, and the high concentration source region 24 of the selection gate transistor B).

The manufacturing process of the 2T SONOS cell of such a structure is as follows.

3A to 3I are cross-sectional views of a manufacturing process of a 2T SONOS cell according to the prior art.

First, as shown in FIG. 3A, a pad oxide layer 12 is formed on the semiconductor substrate 11.

Although not shown in the drawing, the pad oxide film 12 is selectively removed, the semiconductor substrate 11 is etched using the pad oxide film 12 as a mask to form a trench, and an insulating film is embedded in the trench. A field oxide film having an STI structure is formed.

Subsequently, as shown in FIG. 3B, the photoresist 13 is coated on the semiconductor substrate 11 and the photoresist 13 is exposed and developed to expose the semiconductor substrate 11 at the portion where the SONOS gate transistor is to be formed. Pattern).

The threshold voltage control ion implantation layer B is formed by implanting the threshold voltage Vt ions into the semiconductor substrate 11 using the patterned photoresist 13 as a mask.

Then, the photoresist 13 and the pad oxide film 12 are sequentially removed, and the ONO film 14 is formed on the entire surface as shown in Fig. 3C. Although not shown in the figure, a well is formed by an ion implantation process.

Subsequently, as shown in FIG. 3D, the ONO film 14 is selectively removed to remain only in the portion where the SONOS gate transistor is to be formed by the photolithography and etching processes, and then subjected to surface oxidation as shown in FIG. 3E. The gate oxide film 15 is formed on the semiconductor substrate 11 exposed by the removal of.

In addition, a polysilicon film is deposited on the entire surface, and the polysilicon film and the gate oxide film 15 are selectively removed by a photo and etching process to form a word line WL on one region of the ONO film 14, and a selection transistor. The gate oxide film 15 and the selection gate SG are formed on the semiconductor substrate 11 at the portion where the is to be formed.

Subsequently, an oxide film 16 is formed on the surface of the word line WL, the select gate SG, and the surface of the semiconductor substrate 11 exposed by the removal of the gate oxide film 15 by surface oxidation.

Subsequently, as shown in FIG. 3F, low concentration impurity ions are implanted into the semiconductor substrate 11 using the word line WL and the selection gate SG as masks to form the low concentration impurity regions 17/18/19.

The low concentration impurity region 17 is a low concentration source region of a SONOS gate transistor and a low concentration drain region of a select gate transistor, the low concentration impurity region 18 is a low concentration drain region of a SONOS gate transistor, and the low concentration impurity region 19 is Low concentration source region of the selection gate transistor.

Subsequently, an insulating film is deposited on the entire surface and blanket etched to form insulating film sidewalls 20 and 21 on both sides of the word line WL and the selection gate SG as shown in FIG. 3G.

As shown in FIG. 3H, high concentration impurity ions are implanted using the word line WL, the selection gate SG, and the insulating film sidewalls 20 and 21 as a mask to form high concentration impurity regions 22 and 23 ( 24).

The high concentration impurity region 22 is a high concentration source region of the SONOS gate transistor and the high concentration drain region of the selection gate transistor, the high concentration impurity region 23 is a high concentration drain region of the SONOS gate transistor, and the high concentration impurity region 24 is A high concentration source region of the select gate transistor.

After that, as shown in FIG. 3I, an interlayer insulating film (not shown) is formed on the entire surface, and the high concentration source region 24, the selection gate SG, the word line WL, After forming a contact hole exposing the surface of the high concentration drain region 23 of the SONOS gate transistor, a conductive material is buried in the contact hole, so that the high concentration source region 24, the selection gate SG, and the word line WL) and wirings respectively connected to the high concentration drain region 23 of the SONOS gate transistor.

This completes the 2T SONOS cell according to the prior art.

As technology advances and device integration improves, the distance between the word line WL and the selection gate SG will become smaller.

Accordingly, the 2T SONOS cell is severely restricted by the critical dimension control and the overlay control of the threshold voltage control ion implantation process and the ONO film patterning process which should be performed only in the region where the SONOS gate transistor is formed. There is a problem in that it is difficult to improve the density of transistors.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a flash memory device and a method of manufacturing the same for improving the integration of 2T SONOS cells.

The flash memory device according to the present invention for achieving the above object comprises a semiconductor substrate, an ONO film on the semiconductor substrate, a threshold voltage control ion implantation layer in the surface of the semiconductor substrate below the ONO film, and on the ONO film. A word line and a select gate formed between the first region, insulating film sidewalls formed on both sides of the word line and the select gate, a first impurity region in the semiconductor substrate surface of the first region, and the first region; The unit cell is composed of a second impurity region in the semiconductor substrate surface of the second region with a word line interposed therebetween, and a third impurity region in the semiconductor substrate surface of the third region with the first region and the selection gate interposed therebetween. It is characterized by.

A method of manufacturing a flash memory device having the above structure includes the steps of implanting threshold voltage control ions into a semiconductor substrate, forming an ONO film formed of a tunnel oxide film-trap nitride film-block oxide film on the semiconductor substrate; Forming a selection gate and a word line on the film with a predetermined region interposed therebetween; forming low concentration impurity regions by implanting low concentration impurity ions into the semiconductor substrate using the selection gate and the word line as a mask; And forming insulating film sidewalls on both side surfaces of the word line, and implanting high concentration impurity regions into the semiconductor substrate using the selection gate and the word line and the insulating film sidewalls on both sides to form high concentration impurity regions. It is characterized by.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, with reference to the accompanying drawings illustrating the configuration and operation of the embodiment of the present invention, the configuration and operation of the present invention shown in the drawings and described by it will be described as at least one embodiment, By the technical spirit of the present invention described above and its core configuration and operation is not limited.

4 is a cross-sectional view of a 2T SONOS cell in accordance with an embodiment of the present invention.

As shown in FIG. 4, a 2T SONOS cell according to the present invention has a SONOS gate transistor (C) having a word line WL arranged in one direction as a gate, and a selection gate arranged side by side in the word line WL. And a select transistor D having (SG) as a gate.

The SONOS gate transistor (C) and the select gate transistor (D) share the impurity regions 35 and 40 and have a symmetrical structure with the impurity regions 35 and 40 in the center.

An ONO film 33 is formed on the entire surface of the semiconductor substrate 31 including the SONOS gate transistor (C) and the selection gate transistor (D), and the surface of the semiconductor substrate 31 under the ONO film 33. Threshold voltage control ion implantation layer C is formed in the inside.

The word line WL and the selection gate SG have an ONO film 33 between the semiconductor substrate 31. On the other hand, an oxide film 34 is formed on the surface of the word line WL and the select gate SG, and insulating film sidewalls 38 and 39 are formed on both sides thereof with the oxide film 34 interposed therebetween.

Low concentration source / drain regions 35 and 36 of the SONOS gate transistor (C) are formed in the semiconductor substrate below the insulating film sidewall 38, and the selection gate transistor is formed in the semiconductor substrate below the insulating film sidewall 21. (D) The low concentration source / drain regions 35 and 37 are formed.

The high concentration impurity region 40 is formed in the semiconductor substrate positioned between the insulating film sidewall 38 and the insulating film sidewall 39.

The high concentration impurity region 40 is a high concentration source region of the SONOS gate transistor (C) and a high concentration drain region of the selection gate transistor (D).

 The high concentration impurity region 41, which is referred to as the high concentration impurity region 40 around the word line WL, is a high concentration drain region of a SONOS gate transistor (C), and centers around the selection gate SG. The high concentration impurity region 42 symmetrical to the high concentration impurity region 40 is a high concentration source region of the selection gate transistor (D).

The threshold voltage of the SONOS gate transistor (C) is determined by the threshold voltage control ion implantation layer (C), and the select gate transistor (C) may be used to solve the over erasure problem of the SONOS gate transistor (C). D) is configured to have a threshold voltage higher than that of the SONOS gate transistor (C).

Next, a manufacturing process of the 2T SONOS cell according to the present invention will be described.

5A to 5H are cross-sectional views of a manufacturing process of a 2T SONOS cell according to an embodiment of the present invention.

First, as shown in FIG. 5A, a pad oxide film 32 is formed on the semiconductor substrate 31.

Although not shown in the drawing, the pad oxide film 32 on the field region is selectively removed, the semiconductor substrate 31 is etched using the pad oxide film 32 as a mask to form a trench, and then an insulating film is formed in the trench. Is embedded to form a field oxide film having an STI structure.

Subsequently, as illustrated in FIG. 5B, the threshold voltage adjusting ion is implanted into the entire surface of the semiconductor substrate 31 to form the threshold voltage adjusting ion implanted layer C. FIG.

Then, the pad oxide film 32 is removed and the ONO film 33 is formed on the front surface as shown in Fig. 5C. Although not shown in the figure, a well is formed by an ion implantation process.

Subsequently, a polysilicon film is deposited on the entire surface, and the polysilicon film is selectively removed by a photo and etching process to form a word line WL at a portion where the SONOS gate transistor is to be formed, as shown in FIG. 5D. The selection gate SG is formed in the portion to be formed.

An oxide film 34 is formed on the surface of the word line WL and the selection gate SG by a surface oxidation process.

Subsequently, as shown in FIG. 5E, low concentration impurities are implanted into the surface of the semiconductor substrate 31 using the word line WL and the selection gate SG as masks to form low concentration impurity regions 35 and 36 and 37. do.

The low concentration impurity region 35 formed in the surface of the semiconductor substrate 31 between the word line WL and the selection gate SG is a low concentration source region of the SONOS gate transistor and a low concentration drain region of the selection gate transistor. The region 36 is a low concentration drain region of the SONOS gate transistor, and the low concentration impurity region 37 is a low concentration source region of the selection gate transistor.

Next, an insulating film is formed on the entire surface, and the insulating film is blanket-etched to remain on both sides of the word line WL and the selection gate SG, and as shown in FIG. 5F, an insulating film sidewall ( 38 is formed on both sides of the selection gate SG.

As shown in FIG. 5G, a high concentration impurity region 40 is implanted by implanting high concentration impurity ions into the semiconductor substrate 31 using the word line WL, the selection gate SG, and the insulating film sidewalls 38 and 39 as a mask. 41, 42 is formed.

The high concentration impurity region 40 is a high concentration source region of the SONOS gate transistor and the high concentration drain region of the select gate transistor, the high concentration impurity region 41 is a high concentration drain region of the SONOS gate transistor, and the high concentration impurity region 42 is A high concentration source region of the select gate transistor.

Subsequently, an interlayer insulating film (not shown) is formed on the entire surface as shown in FIG. 5H, and the high concentration source region 42, the selection gate SG, the word line WL, and the SONOS of the selection gate transistor are formed on the interlayer insulating film. After forming a contact hole exposing the surface of the high concentration drain region 41 of the gate transistor, a conductive material is buried in the contact hole so that the high concentration source region 42, the selection gate SG, and the word line WL of the selection gate transistor are formed. ) And wirings respectively connected to the high concentration drain region 41 of the SONOS gate transistor.

In order to solve the over erasure problem of the SONOS gate transistor, the threshold voltage of the selection gate transistor D must be higher than the threshold voltage of the SONOS gate transistor C.

In the case of the 2T SONOS cell that has completed the above-described manufacturing process, the threshold voltage of the SONOS gate transistor (C) and the selection gate transistor (D) is determined by the ion concentration of the threshold voltage control ion implantation layer (C) and has the same value. .

Therefore, it is necessary to make the threshold voltage of the selection gate transistor (D) higher than the threshold voltage of the SONOS gate transistor (C).

To this end, a threshold voltage adjustment voltage is applied to the selection gate SG, and all remaining wirings are grounded. The threshold voltage adjustment voltage is a voltage higher than the 2T SONOS cell operating voltage, for example, a high voltage of 10 [V].

Here, the case where the selection gate transistor D is of the NMOS type has been described. In the case of the PMOS type, the threshold voltage adjusting voltage is set to -10 [V].

Then, FN tunneling occurs due to the high electric field between the selection gate SG and the semiconductor substrate 31, so that the electrons in the semiconductor substrate 31 enter the selection gate SG beyond the ONO layer 33 and some electrons. They are trapped in the trap nitride film of the ONO film 33, and the threshold voltage of the select gate transistor D is raised.

Meanwhile, the threshold voltage of the selection gate transistor D may be arbitrarily adjusted through the control of the threshold voltage adjustment voltage value.

This completes the 2T SONOS cell according to the present invention.

The flash memory device of the present invention and a method of manufacturing the same have the following effects.

First, since the threshold voltage regulation ion must be injected into not only the SONOS gate transistor but also the selection gate transistor, it is not necessary to perform the photomask process that was previously performed to inject the threshold voltage regulation ion only into the SONOS gate transistor. Accordingly, the integration of the flash memory device may be improved since the critical dimension (CD) adjustment and the overlay control between the SONOS gate transistor and the selection transistor are not required.

Second, since the ONO film is formed entirely on the SONOS gate transistor and the selection gate transistor, there is no need to perform a patterning process for leaving the ONO film only in the SONOS gate transistor. Accordingly, the integration of the flash memory device may be improved since the critical dimension (CD) adjustment and the overlay control between the SONOS gate transistor and the selection transistor are not required.

Third, the manufacturing process can be simplified since the mask process, the ONO film patterning process, and the gate oxide film forming process for the selection gate transistor which are required for the threshold voltage regulation ion implantation do not need to be performed as compared with the prior art.

Fourth, since the threshold voltage of the selection gate transistor can be adjusted by applying a program voltage to the selection gate, various devices can be manufactured as needed.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the examples, but should be defined by the claims.

Claims (12)

Semiconductor substrates; An ONO film on the semiconductor substrate; A threshold voltage control ion implantation layer in a surface of a semiconductor substrate under the ONO film; A word line and a selection gate formed on the ONO film with a first region therebetween; Insulating layer sidewalls formed on both sides of the word line and the selection gate; A first impurity region in the surface of the semiconductor substrate of the first region; A second impurity region in the surface of the semiconductor substrate of the second region with the first region and the word line interposed therebetween; And, And a unit cell comprising a third impurity region in a surface of a semiconductor substrate in a third region having the first region and a selection gate interposed therebetween. The method of claim 1, And an oxide film formed between an upper surface of the word line and the selection gate, between the word line and the insulating film sidewall, and between the selection gate and the insulating film sidewall. The method of claim 1, The first impurity region is A first low concentration impurity region in a semiconductor substrate surface below an insulating film sidewall positioned in a first region of the insulating film sidewalls on the side of the word line; A second low concentration impurity region in a lower semiconductor substrate surface of an insulating film sidewall positioned in a first region of the insulating film sidewalls of the selection gate side; And, And a first high concentration impurity region between the first and second low concentration impurity regions. The method of claim 1, The second impurity region is A third low concentration impurity region in the lower semiconductor substrate surface of the insulating film sidewall positioned in the second region of the insulating film sidewalls on the side of the word line; And, And a second high concentration impurity region formed in the semiconductor substrate of the second region on one side of the third low concentration impurity region. The method of claim 1, The third impurity region is A fourth low concentration impurity region in the semiconductor substrate surface below the insulating film sidewalls positioned in the third region of the insulating film sidewalls on the side of the selection gate; And, And a second high concentration impurity region formed in the semiconductor substrate of the third region on one side of the fourth low concentration impurity region. Implanting threshold voltage regulation ions into the semiconductor substrate; Forming an ONO film composed of a tunnel oxide film-trap nitride film-block oxide film on the semiconductor substrate; Forming a selection gate and a word line on the ONO layer with a predetermined region interposed therebetween; Implanting low concentration impurity ions into the semiconductor substrate using the selection gate and the word line as a mask to form low concentration impurity regions; Forming sidewalls of an insulating layer on both sides of the selection gate and the word line; And forming high concentration impurity regions by implanting high concentration impurity ions into the semiconductor substrate using the selection gate and the word line and sidewalls of the insulating layers on both sides thereof as a mask. The method of claim 6, And forming an oxide film on the top and side surfaces of the select gate and the word line by surface oxidation after forming the select gate and the word line. The method of claim 6, Forming the select gate and the word line Forming a polysilicon film on the semiconductor substrate; And, And patterning the polysilicon layer so that the polysilicon layer remains with the predetermined region interposed therebetween. The method of claim 6, Forming sidewalls of an insulating layer on both sides of the selection gate and the word line; Forming an insulating film on the entire surface; And, And blanket etching the insulating film so as to remain on both sides of the selection gate and the word line. The method of claim 6, And adjusting the threshold voltage of the selection gate after forming the high concentration impurity regions. The method of claim 10, Adjusting the selection gate threshold voltage And trapping electrons in the semiconductor substrate in a trap nitride film of the ONO film according to a predetermined bias condition to increase a threshold voltage of a selection gate. The method of claim 11, The bias condition is And applying a positive voltage to the selection gate and grounding the semiconductor substrate, the word line, and the high concentration impurity regions.

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