CN209045554U - Semiconductor structure and memory construction - Google Patents
Semiconductor structure and memory construction Download PDFInfo
- Publication number
- CN209045554U CN209045554U CN201821581728.8U CN201821581728U CN209045554U CN 209045554 U CN209045554 U CN 209045554U CN 201821581728 U CN201821581728 U CN 201821581728U CN 209045554 U CN209045554 U CN 209045554U
- Authority
- CN
- China
- Prior art keywords
- layer
- semiconductor base
- hard mask
- semiconductor
- buried gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Semiconductor Memories (AREA)
Abstract
The utility model provides a kind of semiconductor structure and memory construction, comprising: semiconductor base；Cushion layer structure, positioned at the surface of semiconductor base；Fleet plough groove isolation structure is located in semiconductor base and the cushion layer structure；Hard mask layer, positioned at the surface of cushion layer structure；Bottom antireflective coating, positioned at the surface of hard mask layer；Filled layer is located in bottom antireflective coating, and filled layer defines position and the shape of the bit line contact needed to form；Sidewall structure is located in bottom antireflective coating, and is located at the outside of filled layer, and sidewall structure defines position and the shape of the buried gate wordline needed to form；Under identical etching condition, the removal rate of filled layer is less than the removal rate of bottom anti-reflection layer and the removal rate of sidewall structure.The utility model does not need photoetching process to define bit line contact hole, can deviate to avoid photolithographic exposure, it is ensured that bit line contact precisely aligns.
Description
Technical field
The utility model belongs to ic manufacturing technology field, more particularly to a kind of semiconductor structure and memory knot
Structure.
Background technique
With the development of technique, the integrated level of semiconductor devices is higher and higher, and the size of semiconductor devices is also smaller and smaller,
Making technology becomes increasingly complex, and cost is also higher and higher.Meanwhile in the preparation process of semiconductor devices, if character shape with
Target value has error (i.e. character shape can not precisely align), then can the performance to semiconductor devices will generate significant adverse
It influences.For example, in the preparation process of existing memory construction, entire process flow steps are more, higher cost, and in shape
When at bit line contact hole, existing photolithographic exposure technique is difficult to realize to be precisely aligned, so that the memory knot being prepared
The reliability and stability of structure are lower.
Utility model content
In view of the foregoing deficiencies of prior art, it the purpose of this utility model is to provide a kind of semiconductor structure and deposits
Reservoir structures, preparation process flow step for solving memory construction in the prior art is more, higher cost, bit line contact
Hole is difficult to realize precisely align, so that the problems such as the reliability and poor stability of obtained memory construction.
In order to achieve the above objects and other related objects, the utility model provides a kind of semiconductor structure, the semiconductor
Structure includes:
Semiconductor base；
Cushion layer structure, positioned at the surface of the semiconductor base；
Fleet plough groove isolation structure is located in the semiconductor base and the cushion layer structure, in the semiconductor base
Inside isolate several active areas being intervally arranged；
Hard mask layer, positioned at the surface of the cushion layer structure；
Bottom antireflective coating, positioned at the surface of the hard mask layer；
Filled layer is located in the bottom antireflective coating, and the filled layer defines the bit line contact needed to form
Position and shape；And
Sidewall structure is located in the bottom antireflective coating, and is located at the outside of the filled layer, the sidewall structure
Define position and the shape of the buried gate wordline needed to form；Wherein,
Under identical etching condition, the removal rate of the filled layer is less than the removal rate of the bottom anti-reflection layer
And the removal rate of the sidewall structure.
As a kind of preferred embodiment of the utility model, deep trap region is also formed in the active area.
As a kind of preferred embodiment of the utility model, the cushion layer structure includes:
Pad oxide, positioned at the surface of the semiconductor base；
Nitration case is padded, positioned at the surface of the pad oxide.
As a kind of preferred embodiment of the utility model, the hard mask layer includes:
First hard mask layer, positioned at the surface of the cushion layer structure；And
Second hard mask layer, positioned at the surface of first hard mask layer.
The utility model also provides a kind of memory construction, and the memory construction includes:
Semiconductor base is formed with fleet plough groove isolation structure in the semiconductor base, and the fleet plough groove isolation structure exists
Several active areas being intervally arranged are isolated in the semiconductor base；
Several buried gate wordline being intervally arranged are located in the active area, and the buried gate wordline
Upper surface be lower than the semiconductor base upper surface；
Bit line contact is located on the semiconductor base；And
Dielectric layer positioned at the surface of the buried gate wordline, and fills up the gap between institute's bitline contact.
As a kind of preferred embodiment of the utility model, deep trap region is also formed in the active area.
As a kind of preferred embodiment of the utility model, the memory construction further includes cushion layer structure, the bed course knot
The surface of the semiconductor base of the structure between the buried gate wordline and institute's bitline contact.
As a kind of preferred embodiment of the utility model, the cushion layer structure includes:
Pad oxide, positioned at the surface of the semiconductor base；And
Nitration case is padded, positioned at the surface of the pad oxide.
As a kind of preferred embodiment of the utility model, the bottom of institute's bitline contact is trapped in the semiconductor base
It is interior.
As a kind of preferred embodiment of the utility model, the buried gate wordline includes:
Grid conducting layer is located in the active area, and the upper surface of the grid conducting layer is lower than the semiconductor base
Upper surface；And
Grid oxic horizon is located in the active area, and between the grid conducting layer and the semiconductor base.
As described above, the semiconductor structure and memory construction of the utility model, have the advantages that
The semiconductor structure of the utility model defines buried gate wordline when forming sidewall structure and filled layer
And position and the shape of bit line contact, when preparing buried gate wordline and bit line contact based on the semiconductor structure, no
Additional photoetching process is needed to define bit line contact hole, so as to avoid photolithographic exposure from deviating, it is ensured that the essence of bit line contact
Really alignment；Meanwhile the preparation method of semiconductor structure is simple, processing step is succinct, saves material cost and process costs；
The memory construction of the utility model defines buried gate word by forming sidewall structure and filled layer respectively
The position and shape of line and bit line contact do not need additional photoetching process when forming bit line contact hole to define bit line contact
Hole, so as to avoid photolithographic exposure from deviating, it is ensured that bit line contact precisely aligns；Meanwhile the preparation method of memory construction
Simply, processing step is succinct, saves material cost and process costs.
Detailed description of the invention
Fig. 1 is shown as the flow chart of the preparation method of the semiconductor structure provided in the utility model embodiment one.
Fig. 2 to Fig. 8 is shown as step 1) in the preparation method of the semiconductor structure provided in the utility model embodiment one
The structural schematic diagram of resulting structures；Wherein, Fig. 5 is that resulting structures are bowed after forming fleet plough groove isolation structure in semiconductor base
Depending on structural schematic diagram, Fig. 6 is the cross section structure schematic diagram in the direction AA along Fig. 5.
What Fig. 9 was shown as providing in the utility model embodiment one deposits in the preparation method of semiconductor structure obtained by step 2)
The overlooking structure diagram of structure.
Figure 10 is shown as the cross section structure schematic diagram in the direction AA along Fig. 9.
Figure 11 is shown as in the preparation method of the semiconductor structure provided in the utility model embodiment one obtained by step 3)
The cross section structure schematic diagram of structure.
Figure 12 is shown as in the preparation method of the semiconductor structure provided in the utility model embodiment one obtained by step 4)
The overlooking structure diagram of structure.
Figure 13 is shown as the cross section structure schematic diagram in the direction AA along Figure 12.
Figure 14 is shown as in the preparation method of the semiconductor structure provided in the utility model embodiment one obtained by step 5)
The schematic diagram of structure.
Figure 15 is the cross section structure schematic diagram in the direction AA along Figure 14.
Figure 16 is shown as the flow chart of the preparation method of the memory construction provided in the utility model embodiment three.
Figure 17 to Figure 23 is shown as step in the preparation method of the memory construction provided in the utility model embodiment three
1) structural schematic diagram of resulting structures；Wherein, Figure 19 is the resulting structures after forming fleet plough groove isolation structure in semiconductor base
Overlooking structure diagram, Figure 20 be along Figure 19 the direction AA cross section structure schematic diagram.
Figure 24 is shown as in the preparation method of the memory construction provided in the utility model embodiment three obtained by step 2)
The overlooking structure diagram of structure.
Figure 25 is shown as the cross section structure schematic diagram in the direction AA along Figure 24.
Figure 26 is shown as in the preparation method of the memory construction provided in the utility model embodiment three obtained by step 3)
The cross section structure schematic diagram of structure.
Figure 27 is shown as in the preparation method of the memory construction provided in the utility model embodiment three obtained by step 4)
The overlooking structure diagram of structure.
Figure 28 is shown as the cross section structure schematic diagram in the direction AA along Figure 27.
Figure 29 is shown as in the preparation method of the memory construction provided in the utility model embodiment three obtained by step 5)
The schematic top plan view of structure.
Figure 30 is the cross section structure schematic diagram in the direction AA along Figure 29.
Figure 31 is shown as in the preparation method of the memory construction provided in the utility model embodiment three obtained by step 6)
The cross section structure schematic diagram of structure.
Figure 32 to Figure 33 is shown as step in the preparation method of the memory construction provided in the utility model embodiment three
7) cross section structure schematic diagram of resulting structures.
Figure 34 to Figure 36 is shown as step in the preparation method of the memory construction provided in the utility model embodiment three
8) cross section structure schematic diagram of resulting structures.
Figure 37 is shown as in the preparation method of the memory construction provided in the utility model embodiment three obtained by step 9)
The schematic top plan view of structure.
Figure 38 is the cross section structure schematic diagram in the direction AA along Figure 37.
Figure 39 to Figure 41 is shown as step in the preparation method of the memory construction provided in the utility model embodiment three
10) cross section structure schematic diagram of resulting structures.
Figure 42 is shown as in the preparation method of the memory construction provided in the utility model embodiment three obtained by step 11)
The cross section structure schematic diagram of structure.
Figure 43 is shown as in the preparation method of the memory construction provided in the utility model embodiment three obtained by step 12)
The schematic top plan view of structure.
Figure 44 is the cross section structure schematic diagram in the direction AA along Figure 43.
Figure 45 is shown as in the preparation method of the memory construction provided in the utility model embodiment three obtained by step 13)
The schematic top plan view of structure.
Figure 46 is the cross section structure schematic diagram in the direction AA along Figure 44.
Component label instructions
10 semiconductor bases
11 cushion layer structures
111 pad oxides
112 pad nitration cases
12 fleet plough groove isolation structures
13 active areas
131 deep trap regions
14 hard mask layers
141 first hard mask layers
142 second hard mask layers
15 bottom anti-reflection layers
151 second opening figures
16 photoresist layers
161 first opening figures
162 bitline contact regions
163 buried gate word line regions
17 sidewall structures
18 filled layers
19 figure channels
20 buried gate wordline grooves
21 buried gate wordline
211 grid oxic horizons
212 grid conducting layers
22 dielectric layers
23 bit line contact holes
24 bit line contacts
Specific embodiment
Illustrate the embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different specific embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints and answer
With carrying out various modifications or alterations under the spirit without departing from the utility model.
Please refer to Fig.1 to Fig.4 6.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model, though it is only shown with related component in the utility model rather than when according to actual implementation in diagram
Component count, shape and size are drawn, when actual implementation form, quantity and the ratio of each component can arbitrarily change for one kind
Become, and its assembly layout form may also be increasingly complex.
Embodiment one
As shown in Figure 1, the utility model provides a kind of preparation method of semiconductor structure, the preparation of the semiconductor structure
Method the following steps are included:
1) semiconductor substrate is provided, the surface of Yu Suoshu semiconductor base forms cushion layer structure；And in the semiconductor
Form fleet plough groove isolation structure in substrate and the cushion layer structure, the fleet plough groove isolation structure in the semiconductor base every
Separate out several active areas being intervally arranged；
2) hard mask layer, bottom anti-reflection layer and photoresist layer are sequentially formed in the surface of cushion layer structure, wherein described hard
Mask layer, the bottom anti-reflection layer and the photoresist layer are sequentially stacked from the bottom to top, and are formed in the photoresist layer
First opening figure, first opening figure, which exposes the bitline contact region for needing to form bit line contact and needs to form, buries
Enter the buried gate word line regions of formula grid wordline；
3) bottom anti-reflection layer is etched according to the photoresist layer, first opening figure is transferred to the bottom
In portion's anti-reflecting layer, in forming the second opening figure in the bottom anti-reflection layer；
4) Yu Suoshu the second opening figure side wall forms sidewall structure, and the sidewall structure defines the buried gate
The position of word line regions and shape, second opening figure except the sidewall structure define the bitline contact region
Position and shape；And
5) filled layer is formed in second opening figure except Yu Suoshu sidewall structure, wherein in identical etching
Under the conditions of, the removal rate of the filled layer is less than the removal rate of the bottom anti-reflection layer and the removal of the sidewall structure
Rate.
In step 1), the S11 step and Fig. 2 to Fig. 5 of Fig. 1 are please referred to, semiconductor substrate 10 is provided, is partly led in described
The surface of body substrate 10 forms cushion layer structure 11；And in forming shallow trench in the semiconductor base 10 and the cushion layer structure 11
Isolation structure 12, the fleet plough groove isolation structure 12 in isolated in the semiconductor base 10 several be intervally arranged it is active
Area 13.
As an example, the semiconductor substrate 10 can include but is not limited to monocrystalline substrate, multicrystalline silicon substrate, gallium nitride
Substrate or Sapphire Substrate, in addition, can also be that intrinsic silicon serves as a contrast when the semiconductor substrate 10 is single crystalline substrate or polycrystalline substrates
The silicon substrate of bottom either light dope, further, it is possible to be N-type polycrystalline silicon substrate or p-type polysilicon substrate.
As an example, the cushion layer structure can be formed using physical gas-phase deposition or chemical vapor deposition process
11, specifically, the cushion layer structure 11 may include pad oxide 111 and pad nitration case 112, wherein the pad oxide position
In the surface of the semiconductor base 10, the pad nitration case 112 is located at the surface of the pad oxide 111, as shown in Figure 3.
As an example, the fleet plough groove isolation structure 12 can be by forming isolated groove in the semiconductor substrate 10
Afterwards, then using chemical vapor deposition or other deposition technique in the isolated groove depositing insulating layer and formed.It is described shallow
The material of groove isolation construction 12 may include silicon nitride or silica etc..The cross sectional shape of the fleet plough groove isolation structure 12
It can be set according to actual needs, wherein terraced including falling with the cross sectional shape of the fleet plough groove isolation structure 12 in Fig. 5
Shape in actual example as an example, but be not limited thereto.It should be noted that being deposited in the isolated groove described exhausted
When edge layer, if the insulating layer fills up the surface of the isolated groove and the covering cushion layer structure 11, needed at this time using change
Learn the insulating layer that mechanical milling tech removes 11 surface of cushion layer structure.
As an example, the fleet plough groove isolation structure 12 can isolate in the semiconductor substrate 10 several described in
Active area 13 can be but be not limited only to as shown in Figure 4 be arranged in array.
As an example, being formed with MOS device (not shown) in the active area 13, the MOS device includes grid, source electrode
And drain electrode, wherein the source electrode and the two sides that be located at the grid opposite that drain.
As an example, further including following steps after step 1):
The cushion layer structure 11 is removed, as shown in Figure 6；Specifically, can be gone with dry etch process or wet-etching technology
Except the cushion layer structure 11；
In carrying out ion implanting in the active area 13, in forming deep trap region 131 in the active area 13, such as Fig. 7
It is shown；Specifically, the type in the deep trap region 131 formed can be selected according to actual needs, it can be according to reality
Need to be selected as P-doped zone domain or n-type doping region；And
10 surface of the semiconductor base after ion implanting forms cushion layer structure 11 again, as shown in Figure 8.
The first removal cushion layer structure 11, Ke Yiyou for being located at 10 surface of semiconductor base before ion implantation
Effect reduces requirement of the ion implanting to energy and dosage, reduces the difficulty of ion implanting；At the same time it can also reduce it is subsequent can be with work
The accumulation of sequence edge effect.
The etch stop layer for the hard mask layer that the cushion layer structure 11 is subsequently formed as removal, can be effectively prevented removal
Plasma damage of the plasma to the semiconductor base 10 when the hard mask layer；Meanwhile the cushion layer structure 11 may be used also
Using the stop layer as the grid conducting layer planarization process being subsequently formed.
In step 2), the S12 step and Fig. 9 to Figure 10 in Fig. 1 are please referred to, is sequentially formed in the surface of cushion layer structure 11
Hard mask layer 14, bottom anti-reflection layer 15 and photoresist layer 16, wherein the hard mask layer 14, the bottom anti-reflection layer
(BARC) 15 and the photoresist layer 16 be sequentially stacked from the bottom to top, and the first opening figure is formed in the photoresist layer 16
161, first opening figure 161 exposes the bitline contact region 162 for needing to form bit line contact and needs to form embedment
The buried gate word line regions 163 of formula grid wordline.
As an example, forming the hard mask layer 14 in the surface of the cushion layer structure 11 may include steps of:
The first hard mask layer 141 is formed in 11 surface of cushion layer structure；And
The second hard mask layer 142 is formed in 141 surface of the first hard mask layer.
As an example, first hard mask layer 141 may include non-type carbon (α-C) layer, unformed silicon (α-Si) layer
Or silicon oxynitride layer (SiON)；Second hard mask layer 142 equally may include include non-type carbon-coating, unformed silicon layer or
Silicon oxynitride layer；The material of first hard mask layer 141 can be identical as the material of second hard mask layer 142, can also
With different from the material of second hard mask layer 142；Preferably, in the present embodiment, the material of first hard mask layer 141
It is different from the material of second hard mask layer 142.
In step 3), S13 step and Figure 11 in Fig. 1 are please referred to, etches the bottom according to the photoresist layer 16
First opening figure 161 is transferred in the bottom anti-reflection layer 15, in the bottom anti-reflective by anti-reflecting layer 15
The second opening figure 151 is formed in layer 15.
The bottom is etched as an example, can use according to the photoresist layer 16 but be not limited only to dry etch process
Anti-reflecting layer 15 is opened with being formed in the bottom anti-reflection layer 15 with first opening figure 161 consistent described second
Mouth figure 151.
As an example, further including removal after forming second opening figure 151 in the bottom anti-reflection layer 15
The step of photoresist layer 16.
In step 4), 151 side wall of S14 step and the second opening figure of Figure 12 to Figure 13, Yu Suoshu in Fig. 1 is please referred to
Sidewall structure 17 is formed, the sidewall structure 17 defines position and the shape of the buried gate word line regions 163, described
Second opening figure 151 except sidewall structure 17 defines position and the shape of the bitline contact region 162.
As an example, forming the sidewall structure 17 in 151 side wall of the second opening figure may include steps of:
It is 4-1) anti-in the bottom using atom layer deposition process, physical gas-phase deposition or chemical vapor deposition process
Spacer material layer is formed on the surface in reflecting layer 15, the side wall of second opening figure 151 and bottom；And
15 surface of bottom anti-reflection layer and second opening figure 4-2) are located at using dry etch process removal
The spacer material layer of 151 bottoms, the spacer material layer for remaining in 151 side wall of the second opening figure constitute institute
State sidewall structure 17.
As an example, the sidewall structure 17 may include oxide side wall structure, i.e., the material of the described sidewall structure 17
It may include oxide, for example, silica etc..
It should be noted that " second opening figure 151 except the sidewall structure 17 " refers to that described second opens
The region retained after the sidewall structure 17 is formed in mouth figure 151.
In step 5), the S15 step and Figure 14 to Figure 15 in Fig. 1, the institute except Yu Suoshu sidewall structure 17 are please referred to
It states in the second opening figure 151 and forms filled layer 18, wherein under identical etching condition, the removal speed of the filled layer 18
Rate is less than the removal rate of the bottom anti-reflection layer 15 and the removal rate of the sidewall structure 17.
As an example, forming filled layer 18 in second opening figure 151 except the sidewall structure 17 and including
Following steps:
5-1) in the opening figure 151 except the Yu Suoshu sidewall structure 17 and surface of the bottom anti-reflection layer 15
Form filled layer 18；And
The filled layer 18 carved removal and be located at 15 surface of bottom anti-reflection layer 5-2) is returned using dry etch process.
As an example, the material of the filled layer 18 should be with the material and the sidewall structure of the bottom anti-reflection layer 15
17 material is all different, so that the filled layer 18 has with the bottom anti-reflection layer 15 and the sidewall structure 17 not
Same etching selection ratio；Preferably, under identical etching condition, the removal rate of the filled layer 18 is anti-less than the bottom
The removal rate of the removal rate in reflecting layer 15 and the sidewall structure 17, i.e., under identical etching condition, the filled layer
18 with the bottom anti-reflection layer 15 and the selection ratio with higher of the sidewall structure 17.It is further preferable that in the present embodiment,
The filled layer 18 can with but be not limited only to include nitride layer, i.e., the material of the described filled layer 18 may include but be not limited only to
Nitride, for example, silicon nitride.The selection of the material of the filled layer 18 is than higher than the bottom anti-reflection layer 15 and the side wall
The selection ratio of structure 17 can make described fill out when etching removes the bottom anti-reflection layer 15 and the sidewall structure 17
It fills layer 18 to be retained, so as to realize autoregistration when needing to form bit line contact hole.
The semiconductor structure of the preparation method preparation of the semiconductor structure of the utility model can form the side wall knot
Autoregistration simultaneously defines the buried gate wordline for needing to form buried gate wordline when structure 17 and the filled layer 18
Region 163 and need to form bit line contact the bitline contact region 162 position and shape, be based on the semiconductor junction
When being configured standby buried gate wordline and bit line contact, additional photoetching process is not needed to define bit line contact hole, to open
It avoids being lithographically formed existing exposure offset when bit line contact hole, and then ensures precisely aligning for bit line contact；Meanwhile this is practical
The preparation method processing step of novel semiconductor structure is succinct, can be with effectively save material cost and process costs.
Embodiment two
Please continue to refer to Fig. 2 to Figure 15, the utility model also provides a kind of semiconductor structure, the semiconductor structure packet
It includes: semiconductor base 10；Cushion layer structure 11, the cushion layer structure 11 are located at the surface of the semiconductor base 10；Shallow trench every
From structure 12, the fleet plough groove isolation structure 12 is located in the semiconductor base 10 and the cushion layer structure 11, in described
Several active areas 13 being intervally arranged are isolated in semiconductor base 10；Hard mask layer 14, hard mask layer 14 are located at the pad
The surface of layer structure 11；Bottom antireflective coating 15, the bottom antireflective coating 15 are located at the surface of the hard mask layer 14；
Filled layer 18, the filled layer 18 be located in the bottom antireflective coating 15, and the filled layer 18, which defines, to be needed to form
The position of bit line contact and shape；And sidewall structure 17, the sidewall structure 17 are located in the bottom antireflective coating 15, and
Positioned at the outside of the filled layer 18, the sidewall structure 17 defines position and the shape of the buried gate wordline needed to form
Shape；Wherein, under identical etching condition, the removal rate of the filled layer 18 is less than the removal of the bottom anti-reflection layer 15
The removal rate of rate and the sidewall structure 17.
As an example, the semiconductor substrate 10 can include but is not limited to monocrystalline substrate, multicrystalline silicon substrate, gallium nitride
Substrate or Sapphire Substrate, in addition, can also be that intrinsic silicon serves as a contrast when the semiconductor substrate 10 is single crystalline substrate or polycrystalline substrates
The silicon substrate of bottom either light dope, further, it is possible to be N-type polycrystalline silicon substrate or p-type polysilicon substrate.
As an example, the cushion layer structure 11 includes pad oxide 111 and pad nitration case 112, wherein the pad oxide
Positioned at the surface of the semiconductor base 10, the pad nitration case 112 is located at the surface of the pad oxide 111, such as Fig. 3 institute
Show.
As an example, the fleet plough groove isolation structure 12 can be by forming isolated groove in the semiconductor substrate 10
Afterwards, then using chemical vapor deposition or other deposition technique in the isolated groove depositing insulating layer and formed.It is described shallow
The material of groove isolation construction 12 may include silicon nitride or silica etc..The cross sectional shape of the fleet plough groove isolation structure 12
It can be set according to actual needs, wherein terraced including falling with the cross sectional shape of the fleet plough groove isolation structure 12 in Fig. 5
Shape in actual example as an example, but be not limited thereto.It should be noted that being deposited in the isolated groove described exhausted
When edge layer, if the insulating layer fills up the surface of the isolated groove and the covering cushion layer structure 11, needed at this time using change
Learn the insulating layer that mechanical milling tech removes 11 surface of cushion layer structure.
As an example, the fleet plough groove isolation structure 12 can isolate in the semiconductor substrate 10 several described in
Active area 13 can be but be not limited only to as shown in Figure 4 be arranged in array.
As an example, being formed with MOS device (not shown) in the active area 13, the MOS device includes grid, source electrode
And drain electrode, wherein the source electrode and the two sides that be located at the grid opposite that drain.
As an example, being also formed with deep trap region 131 in the active area 13, as shown in Figure 7；Specifically, the institute formed
The type for stating deep trap region 131 can be selected according to actual needs, can be selected as P-doped zone domain according to actual needs
Or n-type doping region.
The etch stop layer for the hard mask layer that the cushion layer structure 11 is subsequently formed as removal, can be effectively prevented removal
Plasma damage of the plasma to the semiconductor base 10 when the hard mask layer；Meanwhile the cushion layer structure 11 may be used also
Using the stop layer as the grid conducting layer planarization process being subsequently formed.
As an example, the hard mask layer 14 includes: the first hard mask layer 141, first hard mask layer 141 is located at institute
State the surface of cushion layer structure 11；And second hard mask layer 142, second hard mask layer 142 are located at first hard mask layer
141 surface.
As an example, first hard mask layer 141 may include non-type carbon (α-C) layer, unformed silicon (α-Si) layer
Or silicon oxynitride layer (SiON)；Second hard mask layer 142 equally may include include non-type carbon-coating, unformed silicon layer or
Silicon oxynitride layer；The material of first hard mask layer 141 can be identical as the material of second hard mask layer 142, can also
With different from the material of second hard mask layer 142；Preferably, in the present embodiment, the material of first hard mask layer 141
It is different from the material of second hard mask layer 142.
As an example, the sidewall structure 17 defines the flush type grid for needing to form the buried gate wordline
The position of pole word line regions 163 and shape, the sidewall structure 17 may include oxide side wall structure, i.e., the described sidewall structure
17 material may include oxide, for example, silica etc..
As an example, the filled layer 18 defines the bitline contact region 162 of the institute's bitline contact needed to form
The material of position and shape, the filled layer 18 should be with the material of the bottom anti-reflection layer 15 and the material of the sidewall structure 17
Material is all different, so that the filled layer 18 has the quarter different from the bottom anti-reflection layer 15 and the sidewall structure 17
Erosion selection ratio；Preferably, under identical etching condition, the removal rate of the filled layer 18 is less than the bottom anti-reflection layer
The removal rate of 15 removal rate and the sidewall structure 17, i.e., under identical etching condition, the filled layer 18 and institute
State bottom anti-reflection layer 15 and the selection ratio with higher of the sidewall structure 17.It is further preferable that in the present embodiment, it is described to fill out
Fill layer 18 can with but be not limited only to include nitride layer, i.e., the material of the described filled layer 18 may include but be not limited only to nitrogenize
Object, for example, silicon nitride.The selection of the material of the filled layer 18 is than higher than the bottom anti-reflection layer 15 and the sidewall structure
17 selection ratio can make the filled layer when etching removes the bottom anti-reflection layer 15 and the sidewall structure 17
18 are retained, so as to realize autoregistration when needing to form bit line contact hole.
The semiconductor structure of the preparation method preparation of the semiconductor structure of the utility model can form the side wall knot
Autoregistration simultaneously defines the buried gate wordline for needing to form buried gate wordline when structure 17 and the filled layer 18
Region 163 and need to form bit line contact the bitline contact region 162 position and shape, be based on the semiconductor junction
When being configured standby buried gate wordline and bit line contact, additional photoetching process is not needed to define bit line contact hole, to open
It avoids being lithographically formed existing exposure offset when bit line contact hole, and then ensures precisely aligning for bit line contact；Meanwhile this is practical
The preparation method processing step of novel semiconductor structure is succinct, can be with effectively save material cost and process costs.
Embodiment three
Figure 16 is please referred to, the utility model also provides a kind of preparation method of memory construction, the memory construction
Preparation method the following steps are included:
1) semiconductor substrate is provided, the surface of Yu Suoshu semiconductor base forms cushion layer structure；And in the semiconductor
Form fleet plough groove isolation structure in substrate and the cushion layer structure, the fleet plough groove isolation structure in the semiconductor base every
Separate out several active areas being intervally arranged；
2) hard mask layer, bottom anti-reflection layer and photoresist layer are sequentially formed in the surface of cushion layer structure, wherein described hard
Mask layer, the bottom anti-reflection layer and the photoresist layer are sequentially stacked from the bottom to top, and are formed in the photoresist layer
First opening figure, first opening figure, which exposes the bitline contact region for needing to form bit line contact and needs to form, buries
Enter the buried gate word line regions of formula grid wordline；
3) bottom anti-reflection layer is etched according to the photoresist layer, first opening figure is transferred to the bottom
In portion's anti-reflecting layer, in forming the second opening figure in the bottom anti-reflection layer；
4) Yu Suoshu the second opening figure side wall forms sidewall structure, and the sidewall structure defines the buried gate
The position of word line regions and shape, second opening figure except the sidewall structure define the bitline contact region
Position and shape；
5) filled layer is formed in second opening figure except Yu Suoshu sidewall structure, wherein in identical etching
Under the conditions of, the removal rate of the filled layer is less than the removal rate of the bottom anti-reflection layer and the removal of the sidewall structure
Rate；
6) etching removes the sidewall structure, positioned at the hard mask layer of the buried gate word line regions, in
Figure channel is formed in the bottom anti-reflection layer and the hard mask layer, the figure channel defines the buried gate
The position of wordline and shape；
7) filled layer and the bottom anti-reflection layer are removed；
8) cushion layer structure of the figure trench bottom is removed, and is removed described except the bitline contact region
Hard mask layer；
9) according to semiconductor base described in the figure channel etching, in formation flush type grid in the semiconductor base
Pole wordline groove；
10) buried gate wordline is formed in Yu Suoshu buried gate wordline groove, the buried gate wordline
Upper surface is lower than the upper surface of the semiconductor base；
11) in the Yu Suoshu buried gate wordline groove and cushion layer structure surface forms dielectric layer；The dielectric layer
It fills up the buried gate wordline groove and covers the surface of the cushion layer structure；
12) it removes the hard mask layer of the bitline contact region and etches the semiconductor base, in being given an account of
Bit line contact hole is formed in matter layer and the semiconductor base, the bottom in institute's bitline contact hole, institute's bitline contact hole is fallen into
In in the semiconductor base；And
13) in filling contact material in institute's bitline contact hole, to form bit line contact.
In step 1), the S21 step and Figure 17 to Figure 20 in Figure 16 are please referred to, semiconductor substrate 10 is provided, in institute
The surface for stating semiconductor base 10 forms cushion layer structure 11；And it is formed in the semiconductor base 10 and the cushion layer structure 11
Fleet plough groove isolation structure 12, the fleet plough groove isolation structure 12 are intervally arranged in isolating several in the semiconductor base 10
Active area 13.
As an example, the semiconductor substrate 10 can include but is not limited to monocrystalline substrate, multicrystalline silicon substrate, gallium nitride
Substrate or Sapphire Substrate, in addition, can also be that intrinsic silicon serves as a contrast when the semiconductor substrate 10 is single crystalline substrate or polycrystalline substrates
The silicon substrate of bottom either light dope, further, it is possible to be N-type polycrystalline silicon substrate or p-type polysilicon substrate.
As an example, the cushion layer structure can be formed using physical gas-phase deposition or chemical vapor deposition process
11, specifically, the cushion layer structure 11 may include pad oxide 111 and pad nitration case 112, wherein the pad oxide position
In the surface of the semiconductor base 10, the pad nitration case 112 is located at the surface of the pad oxide 111, as shown in figure 20.
As an example, the fleet plough groove isolation structure 12 can be by forming isolated groove in the semiconductor substrate 10
Afterwards, then using chemical vapor deposition or other deposition technique in the isolated groove depositing insulating layer and formed.It is described shallow
The material of groove isolation construction 12 may include silicon nitride or silica etc..The cross sectional shape of the fleet plough groove isolation structure 12
It can be set according to actual needs, wherein with the cross sectional shape of the fleet plough groove isolation structure 12 including falling in Figure 20
It is trapezoidal as an example, but being not limited thereto in actual example.It should be noted that in the isolated groove described in deposition
When insulating layer, if the insulating layer fills up the surface of the isolated groove and the covering cushion layer structure 11, need to use at this time
Chemical mechanical milling tech removes the insulating layer on 11 surface of cushion layer structure.
As an example, the fleet plough groove isolation structure 12 can isolate in the semiconductor substrate 10 several described in
Active area 13 can be but be not limited only to as shown in figure 19 be arranged in array.
As an example, being formed with MOS device (not shown) in the active area 13, the MOS device includes grid, source electrode
And drain electrode, wherein the source electrode and the two sides that be located at the grid opposite that drain.
As an example, further including following steps after step 1):
The cushion layer structure 11 is removed, as shown in figure 21；Specifically, can be gone with dry etch process or wet-etching technology
Except the cushion layer structure 11；
In carrying out ion implanting in the active area 13, in forming deep trap region 131 in the active area 13, such as Figure 22
It is shown；Specifically, the type in the deep trap region 131 formed can be selected according to actual needs, it can be according to reality
Need to be selected as P-doped zone domain or n-type doping region；And
10 surface of the semiconductor base after ion implanting forms cushion layer structure 11 again, as shown in figure 23.
The first removal cushion layer structure 11, Ke Yiyou for being located at 10 surface of semiconductor base before ion implantation
Effect reduces requirement of the ion implanting to energy and dosage, reduces the difficulty of ion implanting；At the same time it can also reduce it is subsequent can be with work
The accumulation of sequence edge effect.
The etch stop layer for the hard mask layer that the cushion layer structure 11 is subsequently formed as removal, can be effectively prevented removal
Plasma damage of the plasma to the semiconductor base 10 when the hard mask layer；Meanwhile the cushion layer structure 11 may be used also
Using the stop layer as the grid conducting layer planarization process being subsequently formed.
In step 2), the S22 step and Figure 24 to Figure 25 in Figure 16 are please referred to, in the surface of cushion layer structure 11 successively shape
At hard mask layer 14, bottom anti-reflection layer 15 and photoresist layer 16, wherein the hard mask layer 14, the bottom anti-reflection layer
(BARC) 15 and the photoresist layer 16 be sequentially stacked from the bottom to top, and the first opening figure is formed in the photoresist layer 16
161, first opening figure 161 exposes the bitline contact region 162 for needing to form bit line contact and needs to form embedment
The buried gate word line regions 163 of formula grid wordline.
As an example, forming the hard mask layer 14 in the surface of the cushion layer structure 11 may include steps of:
The first hard mask layer 141 is formed in 11 surface of cushion layer structure；And
The second hard mask layer 142 is formed in 141 surface of the first hard mask layer.
As an example, first hard mask layer 141 may include non-type carbon (α-C) layer, unformed silicon (α-Si) layer
Or silicon oxynitride layer (SiON)；Second hard mask layer 142 equally may include include non-type carbon-coating, unformed silicon layer or
Silicon oxynitride layer；The material of first hard mask layer 141 can be identical as the material of second hard mask layer 142, can also
With different from the material of second hard mask layer 142；Preferably, in the present embodiment, the material of first hard mask layer 141
It is different from the material of second hard mask layer 142.
In step 3), S23 step and Figure 26 in Figure 16 are please referred to, etches the bottom according to the photoresist layer 16
First opening figure 161 is transferred in the bottom anti-reflection layer 15, in the bottom anti-reflective by anti-reflecting layer 15
The second opening figure 151 is formed in layer 15.
The bottom is etched as an example, can use according to the photoresist layer 16 but be not limited only to dry etch process
Anti-reflecting layer 15 is opened with being formed in the bottom anti-reflection layer 15 with first opening figure 161 consistent described second
Mouth figure 151.
As an example, further including removal after forming second opening figure 151 in the bottom anti-reflection layer 15
The step of photoresist layer 16.
In step 4), 151 side of S24 step and the second opening figure of Figure 27 to Figure 28, Yu Suoshu in Figure 16 is please referred to
Wall forms sidewall structure 17, and the sidewall structure 17 defines position and the shape of the buried gate word line regions 163, institute
State position and shape that second opening figure 151 except sidewall structure 17 defines the bitline contact region 162.
As an example, forming the sidewall structure 17 in 151 side wall of the second opening figure may include steps of:
It is 4-1) anti-in the bottom using atom layer deposition process, physical gas-phase deposition or chemical vapor deposition process
Spacer material layer is formed on the surface in reflecting layer 15, the side wall of second opening figure 151 and bottom；And
15 surface of bottom anti-reflection layer and second opening figure 4-2) are located at using dry etch process removal
The spacer material layer of 151 bottoms, the spacer material layer for remaining in 151 side wall of the second opening figure constitute institute
State sidewall structure 17.
As an example, the sidewall structure 17 may include oxide side wall structure, i.e., the material of the described sidewall structure 17
It may include oxide, for example, silica etc..
It should be noted that " second opening figure 151 except the sidewall structure 17 " refers to that described second opens
The region retained after the sidewall structure 17 is formed in mouth figure 151.
In step 5), the S25 step and Figure 29 to Figure 30 in Figure 16, the institute except Yu Suoshu sidewall structure 17 are please referred to
It states in the second opening figure 151 and forms filled layer 18, wherein under identical etching condition, the removal speed of the filled layer 18
Rate is less than the removal rate of the bottom anti-reflection layer 15 and the removal rate of the sidewall structure 17.
As an example, forming filled layer 18 in second opening figure 151 except the sidewall structure 17 and including
Following steps:
5-1) in the opening figure 151 except the Yu Suoshu sidewall structure 17 and surface of the bottom anti-reflection layer 15
Form filled layer 18；And
The filled layer 18 carved removal and be located at 15 surface of bottom anti-reflection layer 5-2) is returned using dry etch process.
As an example, the material of the filled layer 18 should be with the material and the sidewall structure of the bottom anti-reflection layer 15
17 material is all different, so that the filled layer 18 has with the bottom anti-reflection layer 15 and the sidewall structure 17 not
Same etching selection ratio；Preferably, under identical etching condition, the removal rate of the filled layer 18 is anti-less than the bottom
The removal rate of the removal rate in reflecting layer 15 and the sidewall structure 17, i.e., under identical etching condition, the filled layer
18 with the bottom anti-reflection layer 15 and the selection ratio with higher of the sidewall structure 17.It is further preferable that in the present embodiment,
The filled layer 18 can with but be not limited only to include nitride layer, i.e., the material of the described filled layer 18 may include but be not limited only to
Nitride, for example, silicon nitride.The selection of the material of the filled layer 18 is than higher than the bottom anti-reflection layer 15 and the side wall
The selection ratio of structure 17 can make described fill out when etching removes the bottom anti-reflection layer 15 and the sidewall structure 17
It fills layer 18 to be retained, so as to realize autoregistration when needing to form bit line contact hole.
In step 6), S26 step and Figure 31 in Figure 16 are please referred to, etching removes the sidewall structure 17, is located at institute
The hard mask layer 14 of buried gate word line regions 163 is stated, in the bottom anti-reflection layer 15 and the hard mask layer
Figure channel 19 is formed in 14, the figure channel 19 defines position and the shape of the buried gate wordline.
It removes the sidewall structure 17 as an example, can use but be not limited only to dry etch process etching, be located at institute
The hard mask layer 14 stated immediately below sidewall structure 17 and (be located at the buried gate word line regions 163), etching process
The cushion layer structure 11 is stopped at, i.e., the described cushion layer structure 11 is used as etching barrier layer.
In step 7), the S27 step and Figure 32 to Figure 33 in Figure 16 are please referred to, the filled layer 18 and the bottom are removed
Portion's anti-reflecting layer 15.
As an example, removing the filled layer 18 and the bottom anti-reflection layer 15 includes the following steps:
7-1) etching removes the bottom anti-reflection layer 15, as shown in figure 32；Specifically, dry etch process can be used
Etching removes the bottom anti-reflection layer 15；
7-2) etching removes second hard mask layer 142 except the bitline contact region 162, i.e., removal is in addition to institute
Second hard mask layer 142 except stating immediately below filled layer 18；Specifically, exposure mask can be used as according to the filled layer 18
Layer, using but be not limited only to dry etch process etching and remove the described second hard exposure mask except the bitline contact region 162
Layer 142；And
The filled layer 18 7-3) is removed, as shown in figure 33；Specifically, can use but be not limited only to dry etch process
Remove the filled layer 18.
In step 8), the S28 step and Figure 34 to Figure 36 in Figure 16 are please referred to, removes 19 bottom of figure channel
The cushion layer structure 11, and remove the hard mask layer 14 except the bitline contact region 162.
As an example, removing the cushion layer structure 11 of 19 bottom of figure channel, and remove bitline contact area, institute
The hard mask layer 14 except domain 162 includes the following steps:
The cushion layer structure 11 of 19 bottom of figure channel 8-1) is removed, as shown in figure 34；Specifically, according to described
Hard mask layer 14 etches the cushion layer structure 11, to remove the exposed cushion layer structure positioned at 19 bottom of figure channel
11；More specifically, it can use but be not limited only to dry etch process etching and be located at the described of 19 bottom of figure channel
Cushion layer structure 11；
First hard mask layer 141 except the bitline contact region 162 8-2) is removed, as shown in figure 35；Specifically
, can according to second hard mask layer 142 of reservation be used as exposure mask, using but be not limited only to dry etch process etching go
First hard mask layer 141 in addition to the bitline contact region 162；It should be noted that removal described first is covered firmly
During film layer 141, etching terminates at the cushion layer structure 11, i.e., using the cushion layer structure 11 as etching barrier layer；And
Second hard mask layer 142 of the bitline contact region 162 8-3) is removed, as shown in figure 36；Specifically, can
To use but be not limited only to second hard mask layer 142 that dry etch process removal is located at the bitline contact region 162；
Specifically, when removing second hard mask layer 142, will not to the cushion layer structure 11, be located at the bitline contact region
162 first hard mask layer 141 and the semiconductor base 10 causes to etch, and etching off removes the described second hard exposure mask at once
Etching of the etching gas of layer 142 to the cushion layer structure 11, first hard mask layer 141 and the semiconductor base 10
Removal rate is very small, almost can be ignored；It is can ensure that in this way when removing second hard mask layer 142, position
It can be retained in first hard mask layer 141 that the bit line releases region 162.
In step 9), the S29 step and Figure 37 to Figure 38 in Figure 16 are please referred to, etches institute according to the figure channel 19
Semiconductor base 10 is stated, in formation buried gate wordline groove 20 in the semiconductor base 10.
The semiconductor base 10 is etched in described half as an example, can use but be not limited only to dry etch process
The buried gate wordline groove 20 is formed in conductor substrate 10.It should be noted that in etching process, it can be according to guarantor
First hard mask layer 141 and the cushion layer structure 11 stayed is as semiconductor base 10 described in mask etching.
In step 10), the S210 and Figure 39 to Figure 41 in Figure 16, Yu Suoshu buried gate wordline groove 20 are please referred to
Interior formation buried gate wordline 21, the upper surface of the buried gate wordline 21 are lower than the upper table of the semiconductor base 10
Face.
As an example, including following step in forming buried gate wordline 21 in the buried gate wordline groove 20
It is rapid:
10-1) grid oxic horizon 211 is formed on the side wall of Yu Suoshu buried gate wordline groove 20 and bottom, such as Figure 39 institute
Show；Specifically, can use but be not limited only to side wall and bottom of the thermal oxidation technology in the buried gate wordline groove 20
Form the grid oxic horizon 211；
10-2) in Yu Suoshu buried gate wordline groove 20 and 11 surface of cushion layer structure forms grid conducting layer
212, the grid conducting layer 212 fills up between the buried gate wordline groove 20 and the bitline contact region 162
Gap (gap between first hard mask layer 141 retained), and cover reservation the hard mask layer 14 (at this point,
The hard mask layer 14 retained is first hard mask layer 141)；
The part grid conducting layer 212 10-3) is removed using chemical grinding (CMP) technique, so that the grid retained
The upper surface of pole conductive layer 212 and the hard mask layer 14 (i.e. such as first hard mask layer 141 in Figure 40) of reservation
Upper surface flush, as shown in figure 40；And
It 10-4) returns and carves the grid conducting layer 212, to remove the Gate Electrode Conductive for being located at 11 surface of cushion layer structure
Layer 212, and the grid conducting layer 212 that part is located in the buried gate wordline groove 20 is removed, described in being formed
Buried gate wordline 21, as shown in figure 41.It should be noted that " the buried gate wordline 21 described in this example
Upper surface be lower than the upper surface of the semiconductor base 10 " refer to Soviet Union in the buried gate wordline 21 on stricti jurise
The upper surface for searching grid conducting layer 212 is lower than the upper surface of the semiconductor base 10.
As an example, the material of the grid conducting layer 212 in the buried gate wordline 21 includes titanium nitride, nitrogen
Change at least one of tantalum and tungsten, i.e., the material of the described grid conducting layer 212 may include the low electricity such as titanium nitride, tantalum nitride or tungsten
Resistance rate metal also may include at least two in titanium nitride, tantalum nitride and tungsten, i.e., at this point, the grid conducting layer 212 can be with
For the conductive layer of the composite material of titanium nitride, tantalum nitride and at least two material of tungsten composition, or including titanium nitride layer, nitrogen
Change at least two layers of the conductive layer in tantalum layer and tungsten layer.
In step 11), the step S211 and Figure 42 in Figure 16 are please referred to, in Yu Suoshu buried gate wordline groove 20
And 11 surface of cushion layer structure forms dielectric layer 22；The dielectric layer 22 fills up the buried gate wordline groove 20 and covers
Cover the surface of the cushion layer structure 11.
As an example, can use but be not limited only to physical gas-phase deposition or chemical vapor deposition process formed it is described
Dielectric layer 22, the dielectric layer 22 may include but be not limited only to oxide skin(coating) or nitride layer, i.e., the material of the described dielectric layer 22
Material may include but be not limited only to oxide or nitride.Specifically, the oxide may include silica, the nitride
It may include silicon nitride.In the step, first hard mask layer 141 of reservation, after first hard mask layer 141 defines
Continue the position in bit line contact hole 23 to be formed, can realize autoregistration in bitline contact hole 23 being subsequently formed.
In step 12), the step S212 and Figure 43 to Figure 44 in Figure 16 is please referred to, the bitline contact region is removed
162 hard mask layer 14 simultaneously etches the semiconductor base 10, in the dielectric layer 22 and the semiconductor base 10
Interior formation bit line contact hole 23, the bottom in institute's bitline contact hole 23 are trapped in the semiconductor base 10.
As an example, dry etch process can be used to etch the hard mask layer 14 and the semiconductor base 10 with shape
At institute's bitline contact hole 23, since first hard mask layer 141 of reservation has pre-defined out institute's bitline contact hole
23 position and shape, formation can be etched according to first hard mask layer 141 of reservation by not needing photoetching process at this time
Institute's bitline contact hole 23, to realize the accurate autoregistration in bit line contact hole 23.
It should be noted that due to having cushion layer structure 11, etching removal below first hard mask layer 141 of reservation
When first hard mask layer 141, the cushion layer structure 11 immediately below first hard mask layer 141 is also gone together
It removes.
Institute's bitline contact hole 23 also extends to the semiconductor base 10 other than being located in the dielectric layer 22
It is interior, the contact area for the bit line contact and active area 13 being subsequently formed can be increased in this way, that is, increase the position being subsequently formed
The contact area of line and the active area 13, to reduce contact resistance.
It should be noted that the size that institute's bitline contact hole 23 extends to the active area 13 can connect with the bit line
The size that contact hole 23 is located at the part in the dielectric layer 22 is identical, and institute's bitline contact hole 23 extends to the active area 13
Size can also be greater than the size that institute's bitline contact hole 23 is located at the part in the dielectric layer 22.
In step 13), the step S213 and Figure 45 to Figure 46 in Figure 16 is please referred to, is filled out in institute's bitline contact hole 23
Contact material is filled, to form bit line contact 24.
As an example, in filling contact material in institute's bitline contact hole 23, with formed bit line contact 24 may include as
Lower step:
13-1) using physical gas-phase deposition or chemical vapor deposition process in institute's bitline contact hole 23 and described
22 surface of dielectric layer forms contact material；
13-2) it is located at the contact material on 22 surface of dielectric layer using chemical mechanical milling tech removal, retains
Institute's bitline contact 24 is constituted in the contact material in institute's bitline contact hole 23.
As an example, the material of institute's bitline contact 24 includes but are not limited to polysilicon.Specifically, institute's bitline contact
24 material may include DOPOS doped polycrystalline silicon, so that institute's bitline contact 24 is conductive.Institute's bitline contact 24 is used as subsequent shape
At the structure that is connected with the active area 13 of bit line.
Example IV
Incorporated by reference to Figure 17 to Figure 46, the utility model also provides a kind of memory construction, and semiconductor base 10 is described partly to lead
Fleet plough groove isolation structure 12 is formed in body substrate 10, the fleet plough groove isolation structure 12 is isolated in the semiconductor base 10
Several active areas 13 being intervally arranged out；Several buried gate wordline 21 being intervally arranged are located at the active area 13
It is interior, and the upper surface of the buried gate wordline 21 is lower than the upper surface of the semiconductor base 10；Bit line contact 24, it is described
Bit line contact 24 is located on the semiconductor base 10；And dielectric layer 22, the dielectric layer 22 are located at the buried gate word
The surface of line 21, and fill up the gap between institute's bitline contact 24.
As an example, the semiconductor substrate 10 can include but is not limited to monocrystalline substrate, multicrystalline silicon substrate, gallium nitride
Substrate or Sapphire Substrate, in addition, can also be that intrinsic silicon serves as a contrast when the semiconductor substrate 10 is single crystalline substrate or polycrystalline substrates
The silicon substrate of bottom either light dope, further, it is possible to be N-type polycrystalline silicon substrate or p-type polysilicon substrate.
As an example, the fleet plough groove isolation structure 12 can be by forming isolated groove in the semiconductor substrate 10
Afterwards, then using chemical vapor deposition or other deposition technique in the isolated groove depositing insulating layer and formed.It is described shallow
The material of groove isolation construction 12 may include silicon nitride or silica etc..The cross sectional shape of the fleet plough groove isolation structure 12
It can be set according to actual needs, wherein include in figures 4-6 can falling with the cross sectional shape of the fleet plough groove isolation structure 12
It is trapezoidal as an example, but being not limited thereto in actual example.It should be noted that in the isolated groove described in deposition
When insulating layer, if the insulating layer fills up the surface of the isolated groove and the covering cushion layer structure 11, need to use at this time
Chemical mechanical milling tech removes the insulating layer on 11 surface of cushion layer structure.
As an example, the fleet plough groove isolation structure 12 can isolate in the semiconductor substrate 10 several described in
Active area 13 can be but be not limited only to as shown in figure 45 be arranged in array.
As an example, being formed with MOS device (not shown) in the active area 13, the MOS device includes grid, source electrode
And drain electrode, wherein the source electrode and the two sides that be located at the grid opposite that drain.
As an example, being also formed with deep trap region 131 in the active area 13, as shown in figure 46；Specifically, the institute formed
The type for stating deep trap region 131 can be selected according to actual needs, can be selected as P-doped zone domain according to actual needs
Or n-type doping region.
As an example, the memory construction further includes cushion layer structure 11, the cushion layer structure 11 is located at the flush type
The surface of the semiconductor base 10 between grid wordline 21 and institute's bitline contact 24.
As an example, the cushion layer structure 11 includes pad oxide 111 and pad nitration case 112, wherein the pad oxide
Positioned at the surface of the semiconductor base 10, the pad nitration case 112 is located at the surface of the pad oxide 111, such as Figure 46 institute
Show.The etch stop layer for the hard mask layer that the cushion layer structure 11 is subsequently formed as removal, can be effectively prevented described in removal
Plasma damage of the plasma to the semiconductor base 10 when hard mask layer；Meanwhile the cushion layer structure 11 can also be made
For the stop layer for the grid conducting layer planarization process being subsequently formed.
As an example, the buried gate wordline 21 includes grid oxic horizon 211 and grid conducting layer 212, the grid
Pole conductive layer 212 is located in the active area 13, and the upper surface of the grid conducting layer 212 is lower than the semiconductor base 10
Upper surface；The gate oxide 211 is located in the active area 13, and is located at the grid conducting layer 212 and the semiconductor
Between substrate 10.
As an example, the material of the grid conducting layer 212 in the buried gate wordline 21 includes titanium nitride, nitrogen
Change at least one of tantalum and tungsten, i.e., the material of the described grid conducting layer 212 may include the low electricity such as titanium nitride, tantalum nitride or tungsten
Resistance rate metal also may include at least two in titanium nitride, tantalum nitride and tungsten, i.e., at this point, the grid conducting layer 212 can be with
For the conductive layer of the composite material of titanium nitride, tantalum nitride and at least two material of tungsten composition, or including titanium nitride layer, nitrogen
Change at least two layers of the conductive layer in tantalum layer and tungsten layer.
As an example, the bottom of institute's bitline contact 24 is trapped in the semiconductor base 10.Institute's bitline contact 24
Bottom fall into the semiconductor base 10, the contact area of institute's bitline contact 24 Yu the active area 13 can be increased,
To increase the contact area of the bit line 25 and the active area 13, contact resistance is reduced.
As an example, the material of institute's bitline contact 24 includes but are not limited to polysilicon.Specifically, institute's bitline contact
24 material may include DOPOS doped polycrystalline silicon, so that institute's bitline contact 24 is conductive.Institute's bitline contact 24 is used as subsequent shape
At the structure that is connected with the active area 13 of bit line.
In conclusion the utility model provides a kind of semiconductor structure and memory construction, the system of the semiconductor structure
Preparation Method includes the following steps: 1) offer semiconductor substrate, and the surface of Yu Suoshu semiconductor base forms cushion layer structure；And in
Fleet plough groove isolation structure is formed in the semiconductor base and the cushion layer structure, the fleet plough groove isolation structure is partly led in described
Several active areas being intervally arranged are isolated in body substrate；2) hard mask layer, bottom are sequentially formed in the surface of cushion layer structure
Anti-reflecting layer and photoresist layer, wherein the hard mask layer, the bottom anti-reflection layer and the photoresist layer from the bottom to top according to
It is secondary stacked, and the first opening figure is formed in the photoresist layer, first opening figure, which exposes, needs to form bit line
The bitline contact region of contact and the buried gate word line regions for needing to form buried gate wordline；3) according to the photoetching
Glue-line etches the bottom anti-reflection layer, first opening figure is transferred in the bottom anti-reflection layer, in described
The second opening figure is formed in bottom anti-reflection layer；4) Yu Suoshu the second opening figure side wall forms sidewall structure, the side wall
Structure defines position and the shape of the buried gate word line regions, the second opening figure except the sidewall structure
Shape definition goes out position and the shape of the bitline contact region；And 5) second opening figure except Yu Suoshu sidewall structure
Interior formation filled layer, wherein under identical etching condition, the removal rate of the filled layer is less than the bottom anti-reflection layer
Removal rate and the sidewall structure removal rate.Semiconductor structure of the utility model and preparation method thereof is being formed
Position and the shape that buried gate wordline and bit line contact are defined when sidewall structure and filled layer are partly led based on described
When body structure prepares buried gate wordline and bit line contact, additional photoetching process is not needed to define bit line contact hole, from
And it can be deviated to avoid photolithographic exposure, it is ensured that bit line contact precisely aligns；Meanwhile the preparation method of semiconductor structure is simple,
Processing step is succinct, saves material cost and process costs；Memory construction of the utility model and preparation method thereof passes through shape
Position and the shape for defining buried gate wordline and bit line contact respectively at sidewall structure and filled layer connect forming bit line
Additional photoetching process is not needed when contact hole to define bit line contact hole, so as to avoid photolithographic exposure from deviating, it is ensured that bit line
Contact precisely aligns；Meanwhile the preparation method of memory construction is simple, processing step is succinct, saves material cost and technique
Cost.
The above embodiments are only illustrative of the principle and efficacy of the utility model, and not for limitation, this is practical new
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
All equivalent modifications or change completed under mind and technical idea, should be covered by the claim of the utility model.
Claims (10)
1. a kind of semiconductor structure characterized by comprising
Semiconductor base；
Cushion layer structure, positioned at the surface of the semiconductor base；
Fleet plough groove isolation structure is located in the semiconductor base and the cushion layer structure, in the semiconductor base every
Separate out several active areas being intervally arranged；
Hard mask layer, positioned at the surface of the cushion layer structure；
Bottom antireflective coating, positioned at the surface of the hard mask layer；
Filled layer is located in the bottom antireflective coating, and the filled layer defines the position of the bit line contact needed to form
And shape；And
Sidewall structure is located in the bottom antireflective coating, and is located at the outside of the filled layer, the sidewall structure definition
The position of the buried gate wordline needed to form out and shape；Wherein,
Under identical etching condition, the removal rate of the filled layer is less than removal rate and the institute of the bottom anti-reflection layer
State the removal rate of sidewall structure.
2. semiconductor structure according to claim 1, which is characterized in that be also formed with deep trap region in the active area.
3. semiconductor structure according to claim 1, which is characterized in that the cushion layer structure includes:
Pad oxide, positioned at the surface of the semiconductor base；
Nitration case is padded, positioned at the surface of the pad oxide.
4. semiconductor structure according to claim 1, which is characterized in that the hard mask layer includes:
First hard mask layer, positioned at the surface of the cushion layer structure；And
Second hard mask layer, positioned at the surface of first hard mask layer.
5. a kind of memory construction characterized by comprising
Semiconductor base is formed with fleet plough groove isolation structure in the semiconductor base, and the fleet plough groove isolation structure is described
Several active areas being intervally arranged are isolated in semiconductor base；
Several buried gate wordline being intervally arranged are located in the active area, and the buried gate wordline is upper
Surface is lower than the upper surface of the semiconductor base；
Bit line contact is located on the semiconductor base；And
Dielectric layer positioned at the surface of the buried gate wordline, and fills up the gap between institute's bitline contact.
6. memory construction according to claim 5, which is characterized in that be also formed with deep trap region in the active area.
7. memory construction according to claim 5, which is characterized in that the memory construction further includes cushion layer structure,
The surface of the semiconductor base of the cushion layer structure between the buried gate wordline and institute's bitline contact.
8. memory construction according to claim 7, which is characterized in that the cushion layer structure includes:
Pad oxide, positioned at the surface of the semiconductor base；And
Nitration case is padded, positioned at the surface of the pad oxide.
9. memory construction according to claim 5, which is characterized in that the bottom of institute's bitline contact is trapped in described half
In conductor substrate.
10. memory construction according to claim 5, which is characterized in that the buried gate wordline includes:
Grid conducting layer is located in the active area, and the upper surface of the grid conducting layer is upper lower than the semiconductor base
Surface；And
Grid oxic horizon is located in the active area, and between the grid conducting layer and the semiconductor base.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821581728.8U CN209045554U (en) | 2018-09-27 | 2018-09-27 | Semiconductor structure and memory construction |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821581728.8U CN209045554U (en) | 2018-09-27 | 2018-09-27 | Semiconductor structure and memory construction |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209045554U true CN209045554U (en) | 2019-06-28 |
Family
ID=67034436
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821581728.8U Active CN209045554U (en) | 2018-09-27 | 2018-09-27 | Semiconductor structure and memory construction |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209045554U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110957320A (en) * | 2018-09-27 | 2020-04-03 | 长鑫存储技术有限公司 | Semiconductor structure, memory structure and preparation method thereof |
-
2018
- 2018-09-27 CN CN201821581728.8U patent/CN209045554U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110957320A (en) * | 2018-09-27 | 2020-04-03 | 长鑫存储技术有限公司 | Semiconductor structure, memory structure and preparation method thereof |
| CN110957320B (en) * | 2018-09-27 | 2024-05-21 | 长鑫存储技术有限公司 | Semiconductor structure, memory structure and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10600800B2 (en) | Three-dimensional memory device containing multilevel drain select gate isolation and methods of making the same | |
| US10475804B1 (en) | Three-dimensional memory device containing multilevel drain select gate isolation and methods of making the same | |
| US7285812B2 (en) | Vertical transistors | |
| US9331171B2 (en) | Manufacturing method for forming semiconductor structure | |
| EP1794791B1 (en) | Dram cells with vertical u-shaped transistors | |
| CN108257919B (en) | Method for forming random dynamic processing memory element | |
| US10256167B1 (en) | Hydrogen diffusion barrier structures for CMOS devices and method of making the same | |
| CN110957320B (en) | Semiconductor structure, memory structure and preparation method thereof | |
| US9343114B2 (en) | Memory arrays and methods of forming electrical contacts | |
| TWI708369B (en) | Semiconductor device with conductive cap layer over conductive plug and method for forming the same | |
| CN208706648U (en) | A kind of semiconductor memory | |
| US10177154B2 (en) | Structure and method to prevent EPI short between trenches in FinFET eDRAM | |
| US11508735B2 (en) | Cell manufacturing | |
| KR20130068698A (en) | Semiconductor device and method for manufacturing the same | |
| US20210159169A1 (en) | Three-dimensional memory device containing structures for enhancing gate-induced drain leakage current and methods of forming the same | |
| WO2021194538A1 (en) | Three-dimensional memory device with depletion region position control and method of erasing same using gate induced leakage | |
| TW202025261A (en) | Method for forming semiconductor device | |
| CN209045554U (en) | Semiconductor structure and memory construction | |
| KR20140019705A (en) | Semiconductor device and method for fabricating the same | |
| US11935920B2 (en) | Semiconductor device and method | |
| WO2023024012A1 (en) | Three-dimensional nand memory and fabrication method thereof | |
| CN114361111A (en) | Semiconductor structure and preparation method thereof | |
| CN208923087U (en) | Semiconductor devices | |
| CN101996930A (en) | Method for making contact joint gasket and semiconductor device | |
| KR20130022957A (en) | Bit line in semiconductor device and method for fabricating the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |