TW202025261A - Method for forming semiconductor device - Google Patents

Abstract

A method includes forming a first fin extending from a substrate, forming a first gate stack over and along sidewalls of the first fin, forming a first spacer along a sidewall of the first gate stack, the first spacer including a first composition of silicon oxycarbide, forming a second spacer along a sidewall of the first spacer, the second spacer including a second composition of silicon oxycarbide, forming a third spacer along a sidewall of the second spacer, the third spacer including silicon nitride, and forming a first epitaxial source/drain region in the first fin and adjacent the third spacer.

Description

Manufacturing method of semiconductor device

The embodiments of the present invention are related to semiconductor manufacturing technology, in particular to manufacturing methods of semiconductor devices.

Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic equipment. Generally, a semiconductor is manufactured by sequentially depositing materials for an insulating or dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate, and patterning various material layers using lithography to form circuit components and components on the semiconductor substrate. Device.

The semiconductor industry continues to improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the size of the smallest components (feature), which allows more components to be integrated To within the specified area. However, as the size of the smallest component shrinks, additional problems arise from it that need to be resolved.

According to some of the embodiments of the present invention, a method of manufacturing a semiconductor device is provided. The method includes forming a first fin and a second fin above a substrate; forming a first dummy gate structure above the first fin and forming a second dummy gate structure above the second fin; on the first fin , Deposit a first layer of silicon oxycarbide on the second fin, on the first dummy gate structure and on the second dummy gate structure; implant impurities to the first fin through the first layer of silicon oxycarbide material In the chip and in the second fin; after implanting, deposit a second layer of silicon oxycarbide material over the first layer of silicon oxycarbide material; after depositing the second layer of silicon oxycarbide material, pair the first fin The second fin and the second fin are subjected to a wet cleaning process; a first mask is formed over the second fin and the second dummy gate structure; the first fin adjacent to the first dummy gate structure is etched to etch the first fin A plurality of first grooves are formed in the sheet; after the first fin is etched, a wet cleaning process is performed on the first fin and the second fin; a second fin is formed above the first fin and the first dummy gate structure Two masks; etching the second fin adjacent to the second dummy gate structure to form a plurality of second grooves in the second fin; and performing an epitaxial process to simultaneously form the plurality of first grooves A plurality of first epitaxial source/drain regions in a plurality of and a plurality of second epitaxial source/drain regions in the plurality of second grooves.

According to other embodiments of the embodiments of the present invention, methods for manufacturing semiconductor devices are provided. This method includes patterning a substrate to form a plurality of first fins and a plurality of second fins; forming a plurality of first dummy gate structures on the plurality of first fins; and forming a plurality of first dummy gate structures on the plurality of second fins A plurality of second dummy gate structures are formed on the chip; a plurality of first spacer structures are formed on the plurality of first dummy gate structures; a plurality of second spacer structures are formed on the plurality of second dummy gate structures , Wherein the plurality of first spacing structures and the plurality of second spacing structures comprise a low-k dielectric material; forming a plurality of first grooves in the plurality of first fins includes: performing a first A wet deslagging process; and performing a first anisotropic etching process to form the plurality of first grooves in the plurality of first fins; forming all the first grooves in the plurality of first fins After the plurality of first grooves, forming a plurality of second grooves in the plurality of second fins includes: performing a second wet deslagging process; and performing a second anisotropic etching process to Forming the plurality of second grooves in the plurality of second fins; and epitaxially growing a plurality of first source/drain structures in the plurality of first grooves, and in the plurality of first grooves A plurality of second source/drain structures are epitaxially grown in the two grooves.

According to still other embodiments of the embodiments of the present invention, methods for manufacturing semiconductor devices are provided. The method includes forming a first fin extending from a substrate; forming a first gate stack above and along the sidewall of the first fin; forming a first gap along the sidewall of the first gate stack The first spacer includes a first composition of silicon oxycarbide; a second spacer is formed along the sidewall of the first spacer, and the second spacer includes a second composition of silicon oxycarbide; along the sidewall of the second spacer Forming a third spacer, the third spacer including silicon nitride; and forming a first epitaxial source/drain region in the first fin and adjacent to the third spacer.

The following content provides many different embodiments or examples for implementing different components of the embodiments of the present invention. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are only examples and are not used to limit the embodiments of the present invention. For example, if the description mentions that the first part is formed on or above the second part, it may include an embodiment in which the first part and the second part are in direct contact, or may include additional parts formed on the first part and the second part. Between the two parts, the first part and the second part are not in direct contact. In addition, the embodiments of the present invention may reuse reference numbers and/or letters in different examples. This repetition is for the purpose of simplification and clarity, and does not represent a specific relationship between the different embodiments and/or configurations discussed.

In addition, this article may use spatial relative terms, such as "below...", "below...", "below", "above...", "above" and similar terms, which are relative to each other. The terminology is used to facilitate the description of the relationship between one element(s) or component(s) and another element(s) or component(s) as shown in the figure. These spatial relative terms include the different orientations of the devices in use or operation, as well as the orientations described in the diagrams. When the device is turned in different directions (rotated by 90 degrees or other directions), the spatially relative adjectives used here will also be interpreted according to the turned position.

Various embodiments provide processes for forming gate spacers and forming epitaxial source/drain regions in a fin-type field effect transistor device. In some embodiments, low dielectric constant materials such as silicon oxycarbide may be used for some or all of the gate spacers. Using silicon oxycarbide as the gate spacer can reduce the parasitic capacitance in the fin-type field effect transistor device. In addition, by selectively shielding the device regions and separately etching grooves for the epitaxial source/drain regions in each device region, the same epitaxial formation process can be used in each device region to simultaneously form different epitaxial wafers Source/drain region. Therefore, it is possible to simultaneously form epitaxial source/drain regions for different types of devices with characteristics of different types of devices. By using a wet chemical process of heated sulfuric acid and hydrogen peroxide to clean and prepare the surface before each multiple patterning step, damage to the silicon oxycarbide layer can be reduced. Therefore, the benefits of silicon oxycarbide and the benefits of multiple patterning can be achieved in the process flow, and the occurrence of processing defects can be reduced.

FIG. 1 illustrates an example of a fin-type field effect transistor in a three-dimensional schematic diagram according to some embodiments. The fin-type field effect transistor includes a fin 52 on a substrate 50 (for example, a semiconductor substrate). An isolation region 56 is provided in the substrate 50, and the fin 52 protrudes from between adjacent isolation regions 56 and protrudes above the isolation region 56. Although the isolation region 56 is described/illustrated as being separated from the substrate 50, as used herein, the term "substrate" may only refer to a semiconductor substrate or a semiconductor substrate including the isolation region. In addition, although the fin 52 is shown as the same single, continuous material as the base 50, the fin 52 and/or the base 50 may comprise a single material or multiple materials. The gate dielectric layer 92 is located along the sidewall of the fin 52 and above the top surface of the fin 52, and the gate electrode 94 is above the gate dielectric layer 92. The source/drain regions 82 are provided in both sides of the fin 52 with respect to the gate dielectric layer 92 and the gate electrode 94.

Figure 1 further illustrates the reference section used in subsequent drawings. The cross section A-A is along the longitudinal axis of the gate electrode 94 and in a direction, for example, perpendicular to the direction of current flow between the source/drain regions 82 of the fin-type field effect transistor. The cross-section B-B is perpendicular to the cross-section A-A, and is along the longitudinal axis of the fin 52 and along the direction of current flow between the source/drain regions 82 of, for example, the fin field effect transistor. The section C-C is parallel to the section A-A and extends through the source/drain regions of the fin-type field effect transistor. For clarity, the subsequent drawings refer to these reference profiles.

Some of the embodiments discussed here are discussed in the context of fin-type field-effect transistors formed using a gate-last process. In other embodiments, a gate-first process can be used. In addition, some embodiments take into account the orientation used in planar devices such as planar field effect transistors.

FIGS. 2-9B and 11A-26B are schematic cross-sectional diagrams at an intermediate stage of the manufacturing process of the fin field effect transistor according to some embodiments. Figures 2-7 show the reference cross-sections A-A shown in Figure 1, except for a plurality of fins/fin field effect transistors. In Figures 8A to 9B, 11A to B, and 20A to 26B, the drawings ending with "A" are drawn along the reference section AA shown in Figure 1, and the drawings ending with "B" are drawn along the first The similar section BB shown in Figure 1 is shown except for multiple fins/fin field effect transistors. In Figures 12A to 19B, the drawings ending with "A" are drawn along the reference section CC shown in Figure 1, and the drawings ending with "B" are drawn along the similar section BB shown in Figure 1. Shown, except for multiple fins/fin field effect transistors. Figure 24 is drawn along the reference section B-B shown in Figure 1, except for multiple fins/fin field effect transistors.

In Figure 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (for example, with p-type or n-type dopants) Or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally speaking, the semiconductor substrate over insulator is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or a similar film layer. An insulating layer is provided on a substrate which is usually a silicon substrate or a glass substrate. Other substrates can also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP; or a combination of the foregoing.

The substrate 50 has a region 50N and a region 50P. The region 50N can be used to form an n-type device, such as an N-type metal oxide semiconductor (NMOS) transistor, such as an n-type fin field effect transistor. The region 50P can be used to form a p-type device, such as a p-type metal oxide semiconductor (PMOS) transistor, such as a p-type fin field effect transistor. The region 50N can be physically separated from the region 50P (as shown by the partition 51), and any number of device components (such as other active devices, doped regions, isolation structures, etc.) can be arranged between the region 50N and the region 50P. In some embodiments, both regions 50N and 50P are used to form the same type of device, for example, both regions are used for n-type devices or p-type devices.

In some embodiments, more than one n-type device may be formed in the region 50N, or more than one p-type device may be formed in the region 50P. For example, in some embodiments, the region 50P may include a sub-region 50P-1 in which a first p-type device (such as a p-type fin field effect transistor of the first design) is formed and a second p-type device formed therein. The sub-region 50P-2 of the device (for example, the p-type fin field effect transistor of the second design). (For example, the embodiments described below with reference to FIGS. 12A to 19B.) In some embodiments, multiple patterning processes (such as "2P2E" processes or other types of multiple patterning processes) may be used to form different sub-regions. Device. The region 50N may similarly include sub-regions in which different n-type devices are formed. In some embodiments, the area 50N or the area 50P may include only one area or may include two or more sub-areas. Sub-regions can be physically separated from other sub-regions, and any number of device components can be placed between sub-regions.

In FIG. 3, fins 52 are formed in the base 50. The fin 52 is a semiconductor strip. In some embodiments, the fins 52 may be formed in the substrate 50 by etching trenches in the substrate 50. The etching can be any suitable etching process, such as reactive ion etch (RIE), neutral beam etch (NBE), similar etching processes, or a combination of the foregoing. Etching can be anisotropic.

The fins can be patterned by any suitable method. For example, the patterning of the fins may use one or more photolithography processes, including double patterning or multiple patterning processes. Generally speaking, double patterning or multiple patterning processes are combined with optical lithography and self-alignment processes, thereby allowing patterns such as pitches to be produced to be smaller than those of patterns obtainable using a single, direct optical lithography process. distance. For example, in one embodiment, a sacrificial layer is formed on the substrate, and an optical lithography process is used to pattern the sacrificial layer. A self-aligned process is used to form spacers beside the patterned sacrificial layer. The sacrificial layer is then removed, and then the remaining spacers can be used to pattern the fins.

In FIG. 4, an insulating material 54 is formed on the base 50 and is located between adjacent fins 52. The insulating material 54 can be an oxide, such as silicon oxide, nitride, similar materials, or a combination of the foregoing, and the insulating material 54 can be formed by high density plasma chemical vapor deposition (HDP- CVD), flowable chemical vapor deposition (flowable CVD, FCVD) (such as the deposition of chemical vapor deposition-based materials in remote plasma systems, and post-curing to convert them into another material, such as Oxide), similar methods or a combination of the foregoing. Other insulating materials formed by any suitable method can be used. In the illustrated embodiment, the insulating material 54 is silicon oxide formed by a flowable chemical vapor deposition process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material 54 is formed so that the excess insulating material 54 covers the fin 52. Although the insulating material 54 is shown as a single layer, some embodiments may utilize a multilayer structure. For example, in some embodiments, a liner (not shown) may be formed along the surface of the substrate 50 and the fin 52 first. Thereafter, filler materials, such as those described above, may be formed over the liner layer.

In FIG. 5, a removal process is applied to the insulating material 54 to remove the excess insulating material 54 above the fin 52. In some embodiments, a planarization process may be used, such as a chemical mechanical polish (CMP), an etch back process, a combination of the foregoing, or a similar process. The planarization process exposes the fin 52 so that after the planarization process is completed, the insulating material 54 and the top surface of the fin 52 are flush.

In FIG. 6, the insulating material 54 is etched back to form a shallow trench isolation (STI) region (also referred to as an isolation region) 56. The insulating material 54 is etched back so that the upper portion of the fin 52 in the area 50N and the area 50P protrudes from between adjacent shallow trench isolation regions 56. In addition, the top surface of the shallow trench isolation region 56 may have a flat surface, a convex surface, a concave surface (for example, dishing) as shown in the figure, or a combination thereof. The top surface of the shallow trench isolation region 56 can be formed flat, convex, and/or concave by suitable etching. The etchback of the shallow trench isolation region 56 may use a suitable etching process, for example, an etching process selective to the material of the insulating material 54 (for example, the material of the insulating material 54 is etched at a faster rate than the material of the fin 52). For example, a suitable etching process is used to remove chemical oxides. For example, the etching process may use dilute hydrofluoric (dHF).

The process described with reference to FIGS. 2 to 6 is only an example of how the fin 52 can be formed. In some embodiments, the fins can be formed by an epitaxial growth process. For example, a dielectric layer may be formed over the top surface of the substrate 50, and trenches through the dielectric layer may be etched to expose the substrate 50 below. A homoepitaxial structure can be epitaxially grown in the trench, and the dielectric layer can be etched so that the homoepitaxial structure protrudes from the dielectric layer to form a fin. In addition, in some embodiments, a heteroepitaxial structure may be used for the fin 52. For example, the fin 52 in FIG. 5 can be etched, and a material different from the fin 52 can be epitaxially grown on the etched fin 52. In such an embodiment, the fin 52 includes an etched material and an epitaxial growth material disposed on the etched material. In another embodiment, a dielectric layer may be formed over the top surface of the substrate 50, and trenches through the dielectric layer may be etched. Then, a material different from the substrate 50 can be used to epitaxially grow the heteroepitaxial structure in the trench, and the dielectric layer can be etched so that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. In some embodiments, the epitaxy grows a homoepitaxial or heteroepitaxial structure. The material for epitaxial growth can be doped in situ during the growth period, which can eliminate the previous and subsequent implantation, although in situ and implant doping can be used together.

Furthermore, it may be advantageous that the material of the epitaxial growth in the region 50N (eg, the NMOS region) is different from the material in the region 50P (eg, the PMOS region). In various embodiments, the upper portion of the fin 52 may be made of silicon germanium (Si _x Ge _1-x , where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V group compound Semiconductors, II-VI compound semiconductors or similar materials. For example, available materials for forming III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and similar materials.

Further in Figure 6, suitable wells (not shown) can be formed in the fin 52 and/or the base 50. In some embodiments, a P-well may be formed in the area 50N, and an N-well may be formed in the area 50P. In some embodiments, a P-well or N-well is formed in both the region 50N and the region 50P.

In embodiments with different well types, photoresist or other masks (not shown) can be used to implement different implantation steps for the area 50N and the area 50P. For example, a photoresist may be formed above the shallow trench isolation region 56 and the fin 52 in the region 50N. The photoresist is patterned to expose an area 50P of the substrate 50, such as a PMOS area. The photoresist can be formed by using spin-on technology, and the photoresist can be patterned using a suitable photolithography technology. Once the photoresist is patterned, n-type impurity implantation is performed in the region 50P, and the photoresist can be used as a mask to substantially prevent n-type impurities from implanting in the region 50N such as the NMOS region. The n-type impurities may be phosphorus, arsenic or similar impurities, and the concentration implanted in the region is equal to or less than 10 ¹⁸ cm ^{− 3} , for example, about 10 ¹⁷ cm ^{− 3} to about 10 ¹⁸ cm ^{− 3} . After implantation, the photoresist is removed, for example, by a suitable ashing process.

After implanting the region 50P, a photoresist is formed over the shallow trench isolation region 56 and the fin 52 in the region 50P. The photoresist is patterned to expose the area 50N of the substrate 50, such as the NMOS area. The photoresist can be formed by using spin coating technology, and the photoresist can be patterned using a suitable photolithography technology. Once the photoresist is patterned, p-type impurities can be implanted in the region 50N, and the photoresist can be used as a mask to substantially prevent p-type impurities from being implanted in the region 50P, such as the PMOS region. The p-type impurity may be boron, BF ₂ or the like, and the concentration implanted in the region is equal to or less than 10 ¹⁸ cm ^{− 3} , for example, about 10 ¹⁷ cm ^{− 3} to about 10 ¹⁸ cm ^{− 3} . After implanting, the photoresist can be removed by a suitable ashing process, for example.

After the implanted regions 50N and 50P, annealing may be performed to activate the implanted p-type and/or n-type impurities. In some embodiments, the growth material of the epitaxial fin can be doped in-situ during the growth period, which can avoid implantation, although in-situ and implant doping can be used together.

In FIG. 7, a dummy dielectric layer 60 is formed on the fin 52. The dummy dielectric layer 60 may be, for example, silicon oxide, silicon nitride, a combination of the foregoing, or similar materials, and may be deposited or thermally grown according to a suitable technique. A dummy gate layer 62 is formed above the dummy dielectric layer 60 and a mask layer 64 is formed above the dummy gate layer 62. A dummy gate layer 62 may be deposited on the dummy dielectric layer 60, and then the dummy gate layer 62 may be planarized by, for example, chemical mechanical polishing. A mask layer 64 may be deposited on the dummy gate layer 62. The dummy gate layer 62 may be a conductive material, and may be selected from a group including polysilicon, poly-SiGe, metal nitride, metal silicide, metal oxide, and metal. In one embodiment, amorphous silicon is deposited and recrystallized to produce polysilicon. The deposition of the dummy gate layer 62 may be by physical vapor deposition (PVD), chemical vapor deposition, sputter deposition or other techniques known in the art for depositing conductive materials. The dummy gate layer 62 may be formed of other materials having high etching selectivity to the etching of the isolation region. The mask layer 64 may include, for example, silicon nitride, silicon oxynitride, or similar materials. In one example, a single dummy gate layer 62 and a single mask layer 64 are formed across the region 50N and the region 50P. In some embodiments, separate dummy gate layers may be formed in the area 50N and the area 50P, and separate mask layers may be formed in the area 50N and the area 50P. It should be noted that the illustrated dummy dielectric layer 60 only covers the fins 52 for illustrative purposes only. In some embodiments, the dummy dielectric layer 60 may be deposited such that the dummy dielectric layer 60 covers the shallow trench isolation region 56 and extends between the dummy gate layer 62 and the shallow trench isolation region 56.

Figures 8A to 9B and 11A to 11B illustrate various additional steps in the manufacture of the embodiment device. Figures 8A-9B and 11A-B show components in any one of the area 50N and the area 50P. For example, the illustrated structure can be applied to both the area 50N and the area 50P. The structural differences (if any) of the area 50N and the area 50P are described in the text accompanying each drawing.

In FIGS. 8A and 8B, suitable optical lithography and etching techniques may be used to pattern the mask layer 64 to form the mask 74. The pattern of the mask 74 can then be transferred to the dummy gate layer 62. It is also possible to transfer the pattern of the mask 74 to the dummy dielectric layer 60 by a suitable etching technique, thereby forming a dummy gate 72 on the remaining part of the dummy dielectric layer 60. In some embodiments (not separately shown), the dummy dielectric layer 60 may not be patterned. The dummy gate 72 covers each channel region 58 of the fin 52. The pattern of the mask 74 can be used to physically separate each dummy gate 72 from adjacent dummy gates. The length direction of the dummy gate 72 may also be substantially perpendicular to the length direction of the corresponding epitaxial fin 52.

Further in FIGS. 8A and 8B, a first spacer material 78 is formed on the exposed surfaces of the dummy gate 72, the mask 74, and/or the fin 52. The first spacer material 78 is used to form the first spacer 80 (see FIGS. 11A-B). In some embodiments, the material of the first spacer material 78 may be, for example, oxide, nitride, such as silicon oxynitride, silicon oxycarbonitride, silicon oxycarbide, similar materials, or a combination of the foregoing. In some embodiments, the formation of the first spacer material 78 may use, for example, thermal oxidation, chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, physical vapor deposition, sputtering, or similar processes. In FIG. 8B, the first spacer material 78 is shown as extending vertically above the dummy gate 72 and the mask 74 and extending laterally above the fin 52. In some embodiments, the first spacer material 78 may include a multilayer structure of one or more materials. In some embodiments, the first spacer material 78 may be formed to have a thickness of about 3 nm to about 5 nm.

In some cases, the parasitic capacitance of the device (for example, a fin-type field effect transistor device) can be reduced by using a material with a smaller dielectric constant (k). For example, using the first spacer material 78 with a smaller dielectric constant to form the first spacer 80 can reduce the size of the fin-type field effect transistor device (for example, between the gate electrode 94 and the source/drain contact 112). (See Figure 26A ~ B)) parasitic capacitance. In some embodiments, the first spacer material 78 may include a material having a dielectric constant of less than about k=3.9 (for example, about k=3.5 or less). For example, in some embodiments, a silicon oxycarbide material may be used for the first spacer material 78. Silicon oxycarbide has a dielectric constant of approximately k=3.5 or less. Therefore, using silicon oxycarbide for the first spacer material 78 can reduce the parasitic capacitance in the fin-type field effect transistor device. In some embodiments, the deposition technique of the silicon oxycarbide material may use, for example, atomic layer deposition or similar techniques. In some embodiments, the deposition of the silicon oxycarbide material may use a process temperature of about 50° C. to about 80° C. and a process pressure of about 5 Torr to about 10 Torr. In some embodiments, silicon oxycarbide having about 40 atomic% to about 46 atomic% of silicon, about 45 atomic% to about 50 atomic% of oxygen, or about 5 atomic% to about 18 atomic% of silicon can be formed. In some embodiments, different regions or different layers of the first spacer material 78 may include different compositions of silicon oxycarbide.

After forming the first spacer material 78, a lightly doped source/drain (LDD) region (not explicitly shown) can be implanted. In embodiments with different device types, similar to the implantation discussed above in Fig. 6, a mask such as a photoresist can be formed over the area 50N while exposing the area 50P, and the area 50P can be exposed via the first spacer material 78 Impurities of an appropriate type (for example, n-type or p-type) are implanted in the fin 52 in the region 50P. The mask can then be removed. Subsequently, a mask such as a photoresist may be formed over the area 50P while exposing the area 50N, and appropriate types of impurities may be implanted into the fin 52 in the area 50N via the first spacer material 78. The n-type impurity can be any n-type impurity or other n-type impurities discussed above in Figure 6, and the p-type impurity can be any p-type impurity or other p-type impurities discussed above in Figure 6. The lightly doped source/drain regions may have an impurity concentration of about 10 ¹⁵ cm ^{− 3} to about 10 ¹⁶ cm ^{− 3} . Annealing can be used to activate implanted impurities. Because the lightly doped source/drain region dopants are implanted via the first spacer material 78, the part of the first spacer material 78 (and therefore the part of the first spacer 80) may also be implanted by impurities Doped. In this way, in some embodiments, the first spacer material 78 may have a higher impurity concentration than the second spacer material 79 (see FIGS. 9A to B), and the second spacer material 79 is formed after the impurity is implanted. .

In FIGS. 9A and 9B, a second spacer material 79 is formed on the first spacer material 78. The second spacer material 79 is used to form the second spacer 81 (see FIGS. 11A to B). In some embodiments, the material of the second spacer material 79 may be, for example, oxide, nitride, such as silicon oxynitride, silicon oxycarbonitride, silicon oxycarbide, similar materials, or a combination of the foregoing. In some embodiments, the formation of the second spacer material 79 may use, for example, chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, physical vapor deposition, sputtering, or similar processes. In some embodiments, the second spacer material 79 may include a multilayer structure of one or more materials. In some embodiments, the second spacer material 79 may be formed to have a thickness of about 3 nm to about 5 nm. Because the second spacer material 79 is formed after impurity is implanted, the second spacer material 79 may have a lower impurity concentration than the first spacer material 78. In some embodiments, the second spacer material 79 and the second spacer 81 are omitted (not shown separately).

Similar to the above-mentioned first spacer material 78 (see Fig. 8B), by forming the second spacer 81 (see Fig. 11B) with a second spacer material 79 having a lower dielectric constant, the device (for example, fin field Parasitic capacitance within the effective transistor device. In some embodiments, the second spacer material 79 may include silicon oxycarbide, and thus may have a dielectric constant less than about k=3.9 (for example, about k=3.5 or less). The silicon oxycarbide material of the second spacer material 79 may be formed in a manner similar to the manner previously described for forming the silicon oxycarbide of the first spacer material 78, but in other embodiments, the second spacer material 79 may be formed differently. form. The composition of the silicon oxycarbide of the second spacer material 79 may be similar to the composition of the silicon oxycarbide for the first spacer material 78 previously.

In some embodiments, both the first spacer material 78 of the first spacer 80 and the second spacer material 79 of the second spacer 81 may be formed of silicon oxycarbide. The first spacer material 78 and the second spacer material 79 may have substantially the same silicon oxycarbide composition or have different compositions. For example, the first spacer material 78 may have a composition of about 45 atomic% to about 48 atomic% of oxygen and/or about 12 atomic% to about 15 atomic% of carbon. The second spacer material 79 may have a composition of about 47 atomic% to about 50 atomic% of oxygen and/or about 10 atomic% to about 13 atomic% of carbon. The first spacer material 78 or the second spacer material 79 may have other compositions than these examples. In some cases, the first spacer material 78 of the first spacer 80 and the second spacer material 79 of the second spacer 81 formed of silicon oxycarbide can reduce the parasitic capacitance, compared to the first spacer 80 formed of different materials. Or one or two of the second spacers 81, for example, a material with a higher dielectric constant.

Turning to Figure 10, the graph shows simulated data of the percentage change of the parasitic capacitance (on the Y axis) of the fin-type field effect transistor device with respect to the dielectric constant (k) of the second spacer 81 (on the X axis). The change of the parasitic capacitance is relative to the point 121, and the point 121 represents the first spacer material 78 of the first spacer 80 and the second spacer material 79 of the second spacer 81 each having a dielectric constant of about k=5. Point 122 represents the capacitance change caused by the first spacer material 78 with a dielectric constant of about k=5 and the second spacer material 79 with a dielectric constant of about k=4. As shown in the figure, the smaller dielectric constant of the second spacer material 79 reduces the parasitic capacitance by about 2%.

Continuing to refer to FIG. 10, point 123 indicates that the dielectric constant of the first spacer material 78 of the first spacer 80 is about k=5 and the second spacer is formed of silicon oxycarbide with a dielectric constant of about k=3.5. 81 of the second spacer material 79 caused by the change in capacitance. As shown in the figure, the small dielectric constant of silicon oxycarbide reduces parasitic capacitance by approximately 3.5%. Point 124 represents the capacitance change caused by the formation of both the first spacer material 78 and the second spacer material 79 of silicon oxycarbide with a dielectric constant of approximately k=3.5. As shown in the figure, by forming the first spacer material 78 and the second spacer material 79 with silicon oxycarbide, the parasitic capacitance can be reduced by about 6.5%. Therefore, as shown in the graph of FIG. 10, both the first spacer material 78 of the first spacer 80 and the second spacer material 79 of the second spacer 81 formed of silicon oxycarbide can reduce the device (such as fin field effect). Transistor device) parasitic capacitance. The graph and simulation data shown in Figure 10 are for illustrative purposes, and in other cases, the dielectric constant of the first spacer material 78 or the second spacer material 79 may be different, or in other cases, the first spacer material The capacitance changes of the various materials of 78 or the second insulating material 79 may be different.

Turning to FIGS. 11A and 11B, the first spacer 80, the second spacer 81, and the sidewall spacer 86 are formed. The formation of the sidewall spacers 86 may be, for example, by conformally depositing an insulating material on the second spacer material 79, and then etching the insulating material anisotropically. In some embodiments, the anisotropic etching of the insulating material also etches the first spacer material 78 to form the first spacer 80 and etches the second spacer material 79 to form the second spacer 81. The concentration of implant impurities of the second spacer 81 may be lower than that of the first spacer 80, as described above with reference to the second spacer material 79 and the first spacer material 78. In some embodiments, the insulating material of the sidewall spacer 86 may be a low-k dielectric material, such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorine Fluorinated silicate glass (FSG), silicon nitride, silicon oxycarbide, silicon carbide, silicon carbide nitride, similar materials or a combination of the foregoing. The material of the sidewall spacer 86 can be formed by any suitable method, such as chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition or similar methods. In some embodiments, the sidewall spacer 86 may have a thickness of about 3 nm to about 5 nm.

Turning to FIGS. 12A to 19B, according to some embodiments, epitaxial source/drain regions 82A-B are formed in the fin 52. FIGS. 12A to 19B illustrate the formation of an epitaxial source/drain region 82A in the sub-region 50P-1 and the formation of an epitaxial source/drain region 82B in the sub-region 50P-2. The sub-region 50P-1 and the sub-region 50P-2 may be sub-regions of the region 50P of the substrate 50. The epitaxial source/drain regions (including the epitaxial source/drain regions 82A-B) in the region 50N and the region 50P may be collectively referred to as the epitaxial source/drain regions 82 herein. Figures 12A, 13A, 14A, 15A, 16A, 17A, 18A, and 19A are drawn along the reference section CC shown in Figure 1, and Figures 12B, 13B, 14B, 15B, 16B, 17B, 18B, and 19B are drawn Draw along the reference section BB shown in Figure 1. An epitaxial source/drain region 82 is formed in the fin 52 such that each dummy gate 72 is disposed between respective adjacent pairs of the epitaxial source/drain region 82. In some embodiments, the source/drain region 82 may extend into the fin 52. In some embodiments, the sidewall spacers 86 are used to separate the epitaxial source/drain region 82 and the dummy gate 72 by an appropriate lateral distance, so that the epitaxial source/drain region 82 will not cause The subsequent gate of the fin-type field effect transistor is short-circuited.

Turn to Figures 12A-B to perform the first wet cleaning process 95A. The first wet cleaning process 95A may be a wet chemical cleaning process for removing residues from the surface (for example, a “descum” process). The first wet cleaning process 95A may also include surface treatment. The surface treatment allows oxygen atoms to bond to the surface of the sidewall spacer 86, which reduces outgassing of substances such as nitrogen or hydrogen in subsequent process steps. . In some cases, outgassing (such as NH _x outgassing) can cause defects during the photoresist development process (sometimes called "photoresist poison"). The first wet cleaning process 95A can be performed to prepare the structure for forming the mask 91A (see FIGS. 13A-B).

In some embodiments, the first wet cleaning process 95A may include a mixture of heated sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ). The mixture may be, for example, sulfuric acid and hydrogen peroxide mixed in a molar ratio of about 2:1 to about 5:1. The mixture can be heated to a temperature of about 80°C to about 180°C. For example, during the first wet cleaning process 95A, the structure can be immersed in the heated mixture. The mixtures described herein can remove residues and also reduce the chance of defects related to optical lithography during the photoresist patterning process, such as defects caused by "photoresist poisoning".

In addition, compared to other cleaning technologies, such as plasma-based technologies (such as the use of hydrogen plasma, oxygen plasma, etc.), the heated sulfuric acid and hydrogen peroxide mixture used in the first wet cleaning process 95A The damage of the first spacer 80 and the second spacer 81 is small. For example, some oxygen plasma cleaning technologies will deplete the carbon silicon oxycarbide layer, causing damage to the film, and thus may also cause possible process problems or defects. Therefore, the use of the mixture described herein can reduce the defects related to optical lithography (such as "photoresist poisoning"), and when using silicon oxycarbide materials, it also leads to fewer damage-related defects. For example, by using the mixture described herein in the first wet cleaning process 95A, both the first spacer 80 and the second spacer 81 can be formed of silicon oxycarbide material, thereby reducing process problems or defects Overall opportunity. In this way, the benefits of using a cleaning process (such as improved photolithography) and using silicon oxycarbide materials (such as reduced parasitic capacitance) can be realized.

Turning to FIGS. 13A to B, a mask 91A is formed above the sub-region 50P-2. The mask 91A may include a single layer, or may have a multi-layer structure (for example, a two-layer structure, a three-layer structure, or a structure having more than three layers). The material of the mask 91A may include, for example, photoresist materials, oxide materials, nitride materials, other dielectric materials, similar materials, or a combination of the foregoing. In some embodiments, the mask 91A includes a bottom anti-reflective coating (BARC). The formation of the mask 91A can use one or more suitable techniques, such as spin coating, chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, physical vapor deposition, sputtering, similar techniques or the foregoing combination. A suitable photolithography and etching process can be used to pattern the mask 91A to expose a part of the sub-region 50P-1. For example, one or more wet etching processes or anisotropic dry etching processes can be used to etch the mask 91A.

Turning to FIGS. 14A-B, according to some embodiments, a groove 84A is formed in the fin 52 of the sub-region 50P-1. For example, an anisotropic dry etching process may be used to form the groove 84A. In some cases, part of the first spacer 80, the second spacer 81, or the sidewall spacer 86 may also be etched by an anisotropic dry etching process. The example etching of spacers (also called first spacers) 80, (also called second spacers), and (also called sidewall spacers) 86 shown in FIG. 14A is illustrative, and in other In an embodiment, the anisotropic dry etching process can etch the spacers 80, 81, or 86 differently. For example, in other embodiments, the anisotropic dry etching process may etch a portion of the spacers 80, 81, and 86 in different amounts, so that one or more of the spacers 80, 81, or 86 are in the shallow trench The isolation region 56 extends above the other one of the spacers 80, 81, or 86. These and other changes should be included within the scope of the embodiments of the present invention. In some embodiments, the process parameters of the anisotropic dry etching process can be controlled to etch the groove 84A or the spacer 80, 81, or 86 to have desired characteristics. The process parameters may include, for example, process gas mixture, voltage bias, radio frequency (RF) power, process temperature, process pressure, other parameters, or a combination of the foregoing. In some cases, the epitaxial source/drain region 82A formed in the groove 84A can be controlled by controlling the etching of the groove 84A or the spacer 80, 81 or 86 in this way (see Sections 18A to B Figure) shape, volume, size or other characteristics.

Turn to Figure 15A-B, remove the mask 91A, and perform the second wet cleaning process 95B. The mask 91A can be removed using a suitable process, such as a wet chemical process or a dry process. After the mask 91A is removed, a second wet cleaning process 95B is performed to remove residues and prepare the surface for forming the structure of the mask 91B (see FIGS. 16A-B). In some embodiments, removing the mask 91A is part of performing the second wet cleaning process 95B. The second wet cleaning process 95B may be similar to the first wet cleaning process 95A (see Figures 12A to B). For example, the second wet cleaning process 95B can use a mixture of heated sulfuric acid and hydrogen peroxide. The mixture may have a composition similar to those described for the first wet cleaning process 95A, and the mixture may be heated to a similar temperature. In other cases, the second wet cleaning process 95B may be a different mixture of sulfuric acid and hydrogen peroxide used in the first wet cleaning process 95A, and may be heated to a different temperature. Similar to the first wet cleaning process 95A, the use of a mixture of heated sulfuric acid and hydrogen peroxide can reduce damage to the silicon oxycarbide layer. For example, the first spacer 80 and/or the second spacer 81 are made of silicon oxycarbide. Example of formation.

Turning to Figures 16A to B, a mask 91B is formed above the sub-region 50P-1. The mask 91B may include a single layer or may have a multi-layer structure (for example, a two-layer structure, a three-layer structure, or a structure having more than three layers). The material of the mask 91A may include, for example, photoresist materials, oxide materials, nitride materials, other dielectric materials, similar materials, or a combination of the foregoing. In some embodiments, the mask 91B includes a bottom anti-reflective coating (BARC). The formation of the mask 91B may use one or more suitable techniques, such as spin coating, chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, physical vapor deposition, sputtering, similar techniques or the foregoing combination. The mask 91B can be patterned to expose a portion of the area 50P-2 using a suitable photolithography and etching process. For example, one or more wet etching processes or anisotropic dry etching processes can be used to etch the mask 91B. The mask 91B may be similar to the mask 91A (see Figures 13A to B) or different from the mask 91A.

Turning to FIGS. 17A-B, according to some embodiments, a groove 84B is formed in the fin 52 of the sub-region 50P-2. For example, an anisotropic dry etching process may be used to form the groove 84B. In some cases, part of the first spacer 80, the second spacer 81, or the sidewall spacer 86 may also be etched by an anisotropic dry etching process. In some embodiments, the process parameters of the anisotropic dry etching process can be controlled to etch the groove 84B or the spacer 80, 81, or 86 to have desired characteristics. The process parameters used for the etching of the sub-region 50P-2 may be different from the process parameters used for the etching of the sub-region 50P-1. The process parameters may include, for example, process gas mixture, bias voltage, RF power, process temperature, process pressure, other parameters, or a combination of the foregoing. In some embodiments, the process parameters can be controlled so that the groove 84B in the sub-region 50P-2 is different from (for example, has a different depth, width, shape, etc.) the groove 84A in the sub-region 50P-1. The process parameters can also be controlled so that the spacers 80, 81, or 86 in the sub-region 50P-2 are different from (for example, have different heights, widths, shapes, etc.) the spacers 80, 81, or 86 in the sub-region 50P. These are examples, and these and other changes should be included within the scope of the embodiments of the present invention. In some cases, the epitaxial source/drain region 82B formed in the groove 84B can be controlled by controlling the etching of the groove 84B or the spacer 80, 81, or 86 in this manner (see 18A~ B) shape, volume, size or other characteristics. By using separate and different etching processes in the sub-region 50P-1 and the sub-region 50P-2, the epitaxial source/drain regions in each sub-region can be formed to have different characteristics.

Turn to Figures 18A-B, and remove the mask 91B. The mask 91B can be removed by a suitable process, such as a wet chemical process or a dry process. In this way, the source/drain regions for forming the sub-regions 50P-1 and 50P-2 of the epitaxial source/drain regions 82A-B (see FIGS. 19A-B) can be prepared. As described in FIGS. 12A to 18B, multiple patterning processes can be used to etch different sub-regions differently. In some embodiments, the multiple patterning process can be, for example, the "2P2E" process described in Figures 12A-18B, in which the first sub-region (for example, sub-region 50P-2) is shielded and the second sub-region (for example, sub-region is etched) 50P-1), then mask the second sub-region and etch the first sub-region. In other embodiments, before masking the sub-region 50P-2 and etching the sub-region 50P-1, the sub-region 50P-1 may be first masked and the sub-region 50P-2 may be etched first. By sequentially masking and etching appropriate sub-regions, different etching processes can be used in this way to etch more than two sub-regions. In addition, by using a wet cleaning process similar to the wet cleaning process 95A-B, a wet cleaning process can be performed before each masking step, and there is less chance of damage to the film layer formed of silicon oxycarbide.

Turning to FIGS. 19A-B, according to some embodiments, an epitaxial source/drain region 82 is formed in the region 50P. In some embodiments, a pre-cleaning process may be performed first to remove oxides (such as native oxides) from the grooves 84A-B. The pre-cleaning process may include a wet chemical process (such as diluted HF), a plasma process, or a combination of the foregoing. Using the same epitaxial process, an epitaxial source/drain region 82A is formed in the groove 84A of the sub-region 50P-1, and an epitaxial source/drain region is formed in the groove 84B of the sub-region 50P-2 82B. In some embodiments, the same epitaxial process as the epitaxial source/drain regions 82A-B may be used to form additional epitaxial source/drain regions in other sub-regions (if any). The epitaxial source/drain regions 82A-B can comprise any suitable material, for example, suitable for p-type fin field effect transistors. For example, if the fin 52 is silicon or SiGe, the epitaxial source/drain regions 82A-B may include SiGe, SiGeB, Ge, GeSn, other materials, similar materials, or a combination of the foregoing.

In some embodiments, a single epitaxial process can form different epitaxial source/drain regions in different sub-regions. The difference in the grooves (for example, grooves 84A-B) formed in the sub-area due to the different etching processes performed in the sub-area or the difference in the spacers (for example, the spacer 80, 81 or 86) in the sub-area , So the epitaxy source/drain regions may be different. For example, as shown in FIG. 19A, the epitaxial source/drain regions 82A formed in the groove 84A of the sub-region 50P-1 are merged together during the epitaxial process to form a single epitaxial source/drain region. Region 82A, and the epitaxial source/drain region 82B formed in the groove 84B of the sub-region 50P-2 remains unmerged. In this way, the volume of the epitaxial source/drain region 82A is formed larger than the volume of the epitaxial source/drain region 82B.

The combined epitaxial source/drain region 82A and the uncombined epitaxial source/drain region 82B shown in Figs. 19A to B are different epitaxial cells formed in different sub-regions using the same epitaxial process Illustrative examples of source/drain regions, and other changes should also be included within the scope of the embodiments of the present invention. In other embodiments, the epitaxial source/drain regions formed in different sub-regions may be different in other ways, such as height, width, shape, volume, profile, etc. In this way, fin-type field effect transistor devices with different epitaxial source/drain regions can be formed in different sub-regions and using the same epitaxial process. For example, a logic device may be formed in a first sub-area (for example, sub-area 50P-1), and a static random access memory (SRAM) device may be formed in a second sub-area (for example, sub-area 50P-2) . These are just examples, and other types of devices are also possible.

The epitaxial source/drain region 82 in the region 50N (for example, NMOS region) can be formed by shielding the region 50P (for example, PMOS region) and etching the source/drain region of the fin 52 in the region 50N to A groove is formed in the fin 52. Then, the epitaxial source/drain region 82 in the epitaxial growth region 50N can be epitaxially grown in the groove. The region 50N may be formed before or after the epitaxial source/drain regions 82 are formed in the region 50P (for example, before or after the formation of the epitaxial source/drain regions 82A-B shown in Figures 19A-B) In the epitaxial source/drain region 82. The epitaxial source/drain region 82 of the region 50N may include any suitable material, for example, suitable for n-type fin field effect transistors. For example, if the fin 52 is silicon, the epitaxial source/drain region 82 in the region 50N may include silicon, SiC, SiCP, SiP, or similar materials. The epitaxial source/drain region 82 in the region 50N may have a surface raised from each surface of the fin 52, may or may not be merged, or may have facets.

In some embodiments, the region 50N may include sub-regions, and a multiple patterning process of masking and etching the sub-regions may be used before forming the epitaxial source/drain regions 82 in the region 50N. The multiple patterning process may be similar to the multiple patterning process performed on the sub-regions 50P-1 and 50P-2 of the region 50P as described in FIGS. 12A-18B. In this way, the same epitaxial process can be used to form different epitaxial source/drain regions in different sub-regions. Therefore, different fin-type field effect transistor devices (such as SRAM) can be formed in different sub-regions. , Logic devices, etc.). In some embodiments, the multiple patterning process may include one or more wet cleaning processes similar to the aforementioned wet cleaning processes 95A-B. In this way, silicon oxycarbide can be used for the first spacer 80 and the second spacer 81 in the region 50N, and there is less chance of damage during the multiple patterning process. In some embodiments, the sidewall spacers 86 may be removed after the epitaxial source/drain regions are formed in the regions 50N or 50P or sub-regions thereof. The sidewall spacers 86 may be removed using, for example, anisotropic dry etching.

The epitaxial source/drain regions 82 and/or fins 52 can be implanted with dopants to form source/drain regions, similar to the aforementioned process for forming lightly doped source/drain regions, and then Perform annealing. The impurity concentration of the source/drain regions may be about 10 ¹⁹ cm ⁻³ to about 10 ²¹ cm ⁻³ . The n-type and/or p-type impurities used in the source/drain regions may be any of the aforementioned impurities. In some embodiments, the epitaxial source/drain region 82 may be doped in-situ during growth.

Turning to Figures 20A and 20B, an interlayer dielectric (ILD) 88 is deposited over regions 50N and 50P. The structures shown in FIGS. 20A-B are exemplary structures after forming the epitaxial source/drain regions 82, and the process steps described above can be applied to any of the aforementioned structures, embodiments, or devices. The interlayer dielectric 88 can be formed of a dielectric material or a semiconductor material, and the interlayer dielectric 88 can be deposited by any suitable method, such as chemical vapor deposition, plasma-assisted chemical vapor deposition or flowable chemical vapor. Facies deposition. The dielectric material can include phosphosilicate glass (PSG), borosilicate glass (Boro-Silicate Glass, BSG), boron-doped phosphosilicate glass (Boron-Doped Phospho-Silicate Glass, BPSG), Doped silicate glass (undoped Silicate Glass, USG) or similar materials. The semiconductor material may include amorphous silicon, silicon germanium (Si _x Ge _1-x , where x may be about 0 to 1), pure germanium, or similar materials. Other insulating or semiconductor materials formed by any suitable process can be used. In some embodiments, a contact etch stop layer (CESL) 87 is provided between the interlayer dielectric 88 and the epitaxial source/drain region 82, the hard mask 74 and the sidewall spacers 86. The contact etch stop layer 87 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, similar materials, or a combination of the foregoing.

In FIGS. 21A and 21B, a planarization process such as chemical mechanical polishing may be performed to make the top surface of the interlayer dielectric 88 and the top surface of the dummy gate 72 flush. The planarization process can also remove the mask 74 on the dummy gate 72, and can also remove part of the first spacer 80, the second spacer 81 and the sidewall spacer 86 along the sidewall of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, the first spacer 80, the second spacer 81, the sidewall spacer 86, and the interlayer dielectric 88 are flush. Therefore, the top surface of the dummy gate 72 is exposed through the interlayer dielectric 88.

In FIGS. 22A and 22B, the dummy gate 72 and a portion of the dummy dielectric layer 60 directly under the exposed dummy gate 72 are removed in one or more etching steps, thereby forming the groove 90. In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more process gases. The process gases selectively etch the dummy gate 72 without etching the interlayer dielectric 88 or the gate spacer 86. Each groove 90 exposes the channel area of the corresponding fin 52. The channel region 58 is disposed between adjacent pairs of epitaxial source/drain regions 82. During the removal, when the dummy gate 72 is etched, the dummy dielectric layer 60 may serve as an etch stop layer. Then, the dummy dielectric layer 60 may be optionally removed after the dummy gate 72 is removed.

In FIGS. 23A and 23B, according to some embodiments, a gate dielectric layer 92 and a gate electrode 94 are formed to replace the gate. Figure 24 is a detailed schematic diagram of Figure 23B, as shown. The gate dielectric layer 92 is compliantly deposited in the groove 90, for example, on the top surface and sidewalls of the fin 52 and on the sidewalls of the first spacer 80. The gate dielectric layer 92 may also be formed on the top surface of the interlayer dielectric 88. According to some embodiments, the gate dielectric layer 92 includes silicon oxide, silicon nitride, or the aforementioned multilayer structure. In some embodiments, the gate dielectric layer 92 is a high dielectric constant dielectric material, and in these embodiments, the gate dielectric layer 92 may have a dielectric constant value greater than about 7.0, and may include metal oxide Or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb and combinations of the foregoing. The formation method of the gate dielectric layer 92 may include molecular-beam deposition (MBD), atomic layer deposition, plasma-assisted chemical vapor deposition, and similar methods. In the embodiment where part of the dummy gate dielectric (also called dummy dielectric) 60 is left in the groove 90, the gate dielectric layer 92 includes the material of the dummy gate dielectric 60 (such as silicon oxide) ).

The gate electrodes 94 are respectively deposited on the gate dielectric layer 92 and fill the remaining part of the groove 90. The gate electrode 94 may be a metal-containing material, such as TiN, TiO, TaN, TaC, Co, Ru, Al, W, a combination of the foregoing, or the foregoing multilayer structure. For example, although a single-layer gate electrode 94 is shown in FIG. 23B, the gate electrode 94 may include any number of liner layers 94A, any number of work function adjustment layers 94B, and filling materials 94C, as shown in FIG. 24 Shown. After the gate electrode 94 is filled, a planarization process such as a chemical mechanical polishing process can be performed to remove the material of the gate electrode 94 and the excess part of the gate dielectric layer 92, which are located on the interlayer dielectric 88 Above the top surface. The remaining part of the material of the gate electrode 94 and the gate dielectric layer 92 thus forms a replacement gate for the resulting fin field effect transistor. The gate electrode 94 and the gate dielectric layer 92 can be collectively referred to as a "gate stack". The gate and gate stack may extend along the sidewalls of the channel region 58 of the fin 52.

The formation of the gate dielectric layer 92 in the region 50N and the region 50P can occur simultaneously, so that the gate dielectric layer 92 in each region is formed of the same material, and the formation of the gate electrode 94 can occur simultaneously, so that The gate electrode 94 in each region is formed of the same material. In some embodiments, the gate dielectric layer 92 in each region can be formed by a different process, so that the gate dielectric layer 92 can be a different material, and/or the gate electrode 94 in each region can be It is formed by different processes, so that the gate electrode 94 can be made of different materials. When using different processes, various masking steps can be used to cover and expose the appropriate area.

In FIGS. 25A and 25B, an interlayer dielectric 108 is deposited on the interlayer dielectric 88. In one embodiment, the interlayer dielectric 108 is a flowable film formed by a flowable chemical vapor deposition method. In some embodiments, the interlayer dielectric 108 is formed of a dielectric material, such as phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, undoped silicate glass or Similar materials, and the interlayer dielectric 108 can be deposited by any suitable method, such as chemical vapor deposition, plasma-assisted chemical vapor deposition or similar methods.

In FIGS. 26A and 26B, according to some embodiments, the contacts 110 and (also referred to as source/drain contacts) 112 are formed through the interlayer dielectric 108 and the interlayer dielectric 88. In some embodiments, an annealing process may be performed before forming the contact 112 to form a silicide at the interface between the epitaxial source/drain region 82 and the contact 112. The contact 110 is physically and electrically connected to the gate electrode 94, and the contact 112 is physically and electrically connected to the epitaxial source/drain region 82. 26A-B show the contact members 110 and 112 in the same cross-section; however, in other embodiments, the contact members 110 and 112 may be arranged in different cross-sections. In addition, the positions of the contacts 110 and 112 in Figures 26A-B are only illustrative, and are not intended to limit the embodiment of the present invention in any way. For example, the contact 110 may be vertically aligned with the fin 52 as shown, or may be arranged at a different position on the gate electrode 94. In addition, the contact 112 may be formed before, at the same time, or after the contact 110 is formed.

Turning to FIG. 27, the graph shows experimental data for measuring the carbon concentration in the first spacer 80 and the second spacer 81 made of silicon oxycarbide material. Figure 27 shows the carbon concentration measured after the different process steps (designated as steps A, B, C, and D). In Figure 27, points 125A to D show the carbon concentration of the first sample, points 126A to D show the carbon concentration of the second sample, and points 127A to D show the carbon concentration of the third sample. As described in more detail below, the first wet cleaning process 95A and the second wet cleaning process 95B are used to clean the first sample (points 125A to D) and the second sample (points 126A to D), but the oxygen plasma The process is used to clean the third sample (points 127A to D). The process step A corresponds to the step after the first spacer 80 and the second spacer 81 are formed, so points 125A, 126A, and 127A show the initial carbon concentration of the sample (for example, as shown in Figures 11A to B).

Process step B corresponds to the step after the 2P2E multiple patterning process described in Figures 12A to 18B has been performed. However, the first sample (points 125A to D) and the second sample (points 126A to D) use the aforementioned first wet cleaning process 95A and second wet cleaning 95B, but the third sample (points 127A to D) The oxygen plasma process is used alone instead of the first wet cleaning process 95A and the second wet cleaning process 95B. As indicated by points 125B and 126B, the wet cleaning processes 95A-B performed on the first sample and the second sample remove the carbon of the first spacer 80 and the second spacer 81 of the first sample and the second sample. The concentration is reduced to about 50% of the initial carbon concentration (points 125A and 126A). As shown at point 127B, the oxygen plasma process performed on the third sample reduces the carbon concentration of the first spacer 80 and the second spacer 81 to less than about 10% of the initial carbon concentration (point 127A). The decrease in the carbon concentration indicates that the first spacer 80 and the second spacer 81 are damaged by the oxygen plasma process. Therefore, Figure 27 shows that the use of wet cleaning processes 95A-B can reduce the carbon concentration of the silicon oxycarbide material less than other types of cleaning processes. The data shown in Figure 27 is an illustrative example, and in other cases, the use of wet cleaning processes 95A-B may reduce the carbon concentration by more or less.

Process step C corresponds to the step before the pre-cleaning process as described in Figures 19A-B has been performed. As shown in the figure, the first sample (point 125C), the second sample (point 126C), and the third sample (point 127C) maintain approximately the same carbon concentration as in process step B. The process step D corresponds to the steps before the epitaxial source/drain regions 82A-B are formed as described in FIGS. 19A-B. As shown in the figure, the first sample (point 125D), the second sample (point 126D), and the third sample (point 127D) maintain approximately the same carbon concentration as process step B and process step C. Therefore, in some cases, after performing the wet cleaning processes 95A-B, additional processes will not further reduce the carbon concentration.

The embodiments described herein can achieve some advantages. By using a wet cleaning process that includes a mixture of heated sulfuric acid and hydrogen peroxide, the silicon oxycarbide material can be used as a part of the fin-type field-effect transistor device, and the risk of damaging the silicon oxycarbide material is small. For example, a silicon oxycarbide material can be used for one, two or more spacers formed on the sidewall of the dummy gate during the process. Because silicon oxycarbide has a relatively low dielectric constant, the use of silicon oxycarbide (for example, as a spacer material) in the fin field effect transistor device can reduce the parasitic capacitance of the fin field effect transistor device. For example, the parasitic capacitance between the metal gate and the source/drain contacts can be reduced. By reducing the parasitic capacitance, the performance of the fin-type field-effect transistor device can be improved, especially under higher frequency operation. In addition, the use of the wet cleaning process mixture described herein may allow more reliable use of silicon oxycarbide in addition to multiple patterning techniques. For example, by using selective masking and different etching processes for different devices, multiple patterning can be used with the same epitaxial step to form devices with different epitaxial regions. This can reduce overall process steps, improve process efficiency, and reduce manufacturing costs, while also providing the benefits of using silicon oxycarbide.

In one embodiment, a method includes forming a first fin and a second fin above a substrate, forming a first dummy gate structure above the first fin, and forming a second dummy gate structure above the second fin , Deposit a first layer of silicon oxycarbide on the first fin, on the second fin, on the first dummy gate structure, and on the second dummy gate structure, and remove impurities through the first layer of silicon oxycarbide material Planted in the first and second fins. After planting, deposit a second layer of silicon oxycarbide material on top of the first layer of silicon oxycarbide material, and deposit the second layer of silicon oxycarbide material Afterwards, a wet cleaning process is performed on the first fin and the second fin, a first mask is formed on the second fin and the second dummy gate structure, and the first fin adjacent to the first dummy gate structure is etched To form a first groove in the first fin. After the first fin is etched, a wet cleaning process is performed on the first fin and the second fin, and the first fin and the first dummy gate A second mask is formed above the structure, the second fin adjacent to the second dummy gate structure is etched back to form a second groove in the second fin, and an epitaxial process is performed to simultaneously form the first groove in the first groove An epitaxial source/drain region and a second epitaxial source/drain region in the second groove. In one embodiment, the method includes performing an anisotropic etching process on the first layer of silicon oxycarbide material to form a first spacer on the first dummy gate structure, and applying the second layer of silicon oxycarbide material An anisotropic etching process is performed to form a second spacer on the second dummy gate. In one embodiment, the impurity concentration of the first layer of silicon oxycarbide material is higher than that of the second layer of silicon oxycarbide material. In one embodiment, the wet cleaning process includes using a heated mixture of sulfuric acid and hydrogen peroxide. In one embodiment, the mixture of sulfuric acid and hydrogen peroxide is mixed at a molar ratio of 2:1 to 5:1. In one embodiment, the temperature of the heated mixture is 80°C to 180°C. In one embodiment, the method includes forming sidewall spacers over the second layer of silicon oxycarbide material, the sidewall spacers including a dielectric material different from the silicon oxycarbide material. In one embodiment, at least two first epitaxial source/drain regions are merged together. In an embodiment, the first groove has a first depth and the second groove has a second depth different from the first depth.

In one embodiment, a method includes patterning a substrate to form a plurality of first fins and a plurality of second fins, forming a plurality of first dummy gate structures on the plurality of first fins, and forming a plurality of first dummy gate structures on the plurality of first fins. A plurality of second dummy gate structures are formed on the two fins, a plurality of first spacer structures are formed on the plurality of first dummy gate structures, and a plurality of second spacer structures are formed on the plurality of second dummy gate structures, wherein The plurality of first spacing structures and the plurality of second spacing structures include a low-k dielectric material, forming first grooves in the plurality of first fins, including performing a first wet deslagging process and performing a first non-slag removal process. The isotropic etching process is used to form first grooves in the plurality of first fins, after forming the first grooves in the plurality of first fins, forming second grooves in the plurality of second fins, including Perform a second wet deslagging process and perform a second anisotropic etching process to form second grooves in the plurality of second fins, and epitaxially grow first source/drain electrodes in the first grooves Structure and epitaxially grow a second source/drain structure in the second groove. In one embodiment, the first source/drain structure and the second source/drain structure are simultaneously formed by the same epitaxial growth process. In one embodiment, the first anisotropic etching process is different from the second anisotropic etching process. In one embodiment, the low-k dielectric material is silicon oxycarbide. In one embodiment, forming a plurality of first spacer structures includes using a first deposition process to deposit a first layer of a low-k dielectric material, and performing a planting process on the first layer of a low-k dielectric material. And after the implantation process, a second deposition process is used to deposit a second layer of low-k dielectric material. In one embodiment, performing the first wet deslagging process includes heating a mixture of sulfuric acid and hydrogen peroxide to a temperature of 80°C to 180°C. In an embodiment, the volume of the first source/drain structure is larger than that of the second source/drain structure. In one embodiment, the first anisotropic etching process etches a plurality of first spacer structures more than the second anisotropic etching process etches a plurality of second spacer structures.

In one embodiment, a method includes forming a first fin extending from a substrate, forming a first gate stack above and along the sidewall of the first fin, and along the first gate stack The sidewalls of the first spacers form a first spacer, the first spacers include the first composition of silicon oxycarbide, and the second spacers are formed along the sidewalls of the first spacers. The second spacers include the second composition of silicon oxycarbide. The sidewall of the second spacer forms a third spacer, the third spacer includes silicon nitride, and a first epitaxial source/drain region is formed in the first fin and adjacent to the third spacer. In one embodiment, the method includes forming a second fin extending from the substrate, forming a second gate stack above and along the sidewall of the second fin, and along the second gate stack The sidewall of the fourth spacer includes the first composition of silicon oxycarbide, and the fifth spacer is formed along the sidewall of the fourth spacer. The fifth spacer includes the second composition of silicon oxycarbide. The sidewall of the fifth spacer forms a sixth spacer, the sixth spacer includes silicon nitride, and a second epitaxy source/drain region is formed in the second fin and adjacent to the sixth spacer, wherein the second epitaxy The volume of the source/drain region is different from the volume of the first epitaxial source/drain region. In one embodiment, the first fin includes silicon germanium.

The components of several embodiments are summarized above, so that those with ordinary knowledge in the technical field to which the invention belongs can better understand the aspects of the embodiments of the invention. Those with ordinary knowledge in the technical field to which the invention pertains should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and/or advantages as the embodiments described herein. Those with ordinary knowledge in the technical field to which the invention pertains should also understand that such equivalent structures do not depart from the spirit and scope of the embodiments of the present invention, and they can do everything without departing from the spirit and scope of the embodiments of the present invention. Various changes, substitutions or modifications.

50: Base 50N, 50P: area 50P-1, 50P-2: sub-area 51: divider 52: Fins 54: insulating material 56: Quarantine 60: dummy dielectric layer 62: dummy gate layer 64: Mask layer 72: dummy gate 74, 91A, 91B: mask 78: first spacer material 79: second spacer material 80: first spacer 81: second spacer 82: source/drain region 84A, 84B, 90: groove 86: Sidewall spacer 87: contact etch stop layer 88, 108: Interlayer dielectric 92: gate dielectric layer 94: gate electrode 94A: Lining 94B: Work function adjustment layer 94C: Filling material 95A: The first wet cleaning process 95B: The second wet cleaning process 110: Contact 112: source/drain contacts 121,122,123,124,125A,125B,125C,125D,126A,126B,126C,126D,127A,127B,127C,127D: point A, B, C, D: steps A-A, B-B, C-C: section

The content of the embodiments of the present invention can be better understood through the following detailed description in conjunction with the accompanying drawings. It should be emphasized that according to industry standard practice, many parts are not drawn to scale. In fact, in order to be able to discuss clearly, the size of various components may be arbitrarily increased or decreased. FIG. 1 illustrates an example of a fin-type field effect transistor in a three-dimensional schematic diagram according to some embodiments. Figures 2, 3, 4, 5, 6, 7, 8A, 8B, 9A, and 9B are schematic cross-sectional views of intermediate stages of the manufacturing process of the fin-type field effect transistor according to some embodiments. FIG. 10 is a graph showing simulation data of the variation of the parasitic capacitance of the fin-type field effect transistor device with respect to the dielectric constant of the spacer of the fin-type field effect transistor device according to some embodiments. 11A and 11B are schematic cross-sectional views of an intermediate stage of the manufacturing process of the fin-type field effect transistor according to some embodiments. 12A and 12B are schematic cross-sectional views of the first wet cleaning process in the middle stage of the manufacturing process of the fin field effect transistor according to some embodiments. FIGS. 13A, 13B, 14A, and 14B are schematic cross-sectional views at an intermediate stage of the manufacturing process of the fin field effect transistor according to some embodiments. 15A and 15B are schematic cross-sectional views of the second wet cleaning process in the middle stage of the manufacturing process of the fin field effect transistor according to some embodiments. FIGS. 16A, 16B, 17A, 17B, 18A, and 18B are schematic cross-sectional views of an intermediate stage of the manufacturing process of the fin field effect transistor according to some embodiments. FIGS. 19A and 19B are schematic cross-sectional views of forming epitaxial source/drain regions in the middle stage of the manufacturing process of the fin field effect transistor according to some embodiments. Figures 20A, 20B, 21A, 21B, 22A, 22B, 23A, 23B, 24, 25A, 25B, 26A, and 26B are schematic cross-sectional views of an intermediate stage of the fin field effect transistor manufacturing process according to some embodiments. FIG. 27 is a graph of experimental data showing changes in the carbon concentration of the spacer layer of the fin-type field effect transistor device according to some embodiments.

50: Base

52: Fins

82: source/drain region

88, 108: Interlayer dielectric

94: gate electrode

110: Contact

112: source/drain contacts

Claims (20)

A method for manufacturing a semiconductor device includes: Forming a first fin and a second fin above a base; Forming a first dummy gate structure above the first fin and forming a second dummy gate structure above the second fin; Depositing a first layer of silicon oxycarbide on the first fin, on the second fin, on the first dummy gate structure, and on the second dummy gate structure; Implanting impurities into the first fin and the second fin through the first layer of the silicon oxycarbide material; After the implantation, deposit a second layer of the silicon oxycarbide material on the first layer of the silicon oxycarbide material; After depositing the second layer of the silicon oxycarbide material, performing a wet cleaning process on the first fin and the second fin; Forming a first mask over the second fin and the second dummy gate structure; Etching the first fin adjacent to the first dummy gate structure to form a plurality of first grooves in the first fin; Performing the wet cleaning process on the first fin and the second fin after etching the first fin; Forming a second mask over the first fin and the first dummy gate structure; Etching the second fin adjacent to the second dummy gate structure to form a plurality of second grooves in the second fin; and An epitaxial process is performed to simultaneously form a plurality of first epitaxial source/drain regions in the first grooves and a plurality of second epitaxial source/drain regions in the second grooves. For example, the manufacturing method of the semiconductor device of claim 1, further including: Perform an anisotropic etching process on the first layer of the silicon oxycarbide material to form a plurality of first spacers on the first dummy gate structure, and perform the second layer of the silicon oxycarbide material The anisotropic etching process forms a plurality of second spacers on the second dummy gate. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity concentration of the first layer of the silicon oxycarbide material is higher than that of the second layer of the silicon oxycarbide material. The method for manufacturing a semiconductor device according to claim 1, wherein the wet cleaning process includes using a heated mixture of sulfuric acid and hydrogen peroxide. The method for manufacturing a semiconductor device according to claim 4, wherein the mixture of sulfuric acid and hydrogen peroxide is mixed at a molar ratio of 2:1 to 5:1. The method for manufacturing a semiconductor device according to claim 4, wherein the temperature of the heated mixture is 80°C to 180°C. According to claim 1, the method of manufacturing a semiconductor device further includes forming a plurality of sidewall spacers on the second layer of the silicon oxycarbide material, the sidewall spacers including a dielectric material different from the silicon oxycarbide material. The method for manufacturing a semiconductor device according to claim 1, wherein at least two first epitaxial source/drain regions are merged together. The method for manufacturing a semiconductor device according to claim 1, wherein the first grooves have a first depth and the second grooves have a second depth different from the first depth. A method for manufacturing a semiconductor device includes: Patterning a substrate to form a plurality of first fins and a plurality of second fins; Forming a plurality of first dummy gate structures on the first fins; Forming a plurality of second dummy gate structures on the second fins; Forming a plurality of first spacer structures on the first dummy gate structures; Forming a plurality of second spacer structures on the second dummy gate structures, wherein the first spacer structures and the second spacer structures include a low-k dielectric material; A plurality of first grooves are formed in the first fins, including: Performing a first wet deslagging process; and Performing a first anisotropic etching process to form the first grooves in the first fins; After forming the first grooves in the first fins, forming a plurality of second grooves in the second fins includes: Performing a second wet deslagging process; and Performing a second anisotropic etching process to form the second grooves in the second fins; and A plurality of first source/drain structures are epitaxially grown in the first grooves and a plurality of second source/drain structures are epitaxially grown in the second grooves. The method for manufacturing a semiconductor device according to claim 10, wherein the first source/drain structures and the second source/drain structures are simultaneously formed by the same epitaxial growth process. The method for manufacturing a semiconductor device according to claim 10, wherein the first anisotropic etching process is different from the second anisotropic etching process. The method for manufacturing a semiconductor device according to claim 10, wherein the low-k dielectric material is silicon oxycarbide. According to claim 10, the method of manufacturing a semiconductor device, wherein forming the first spacer structures includes: Using a first deposition process to deposit a first layer of the low-k dielectric material; Performing an implantation process on the first layer of the low-k dielectric material; and After performing the implantation process, a second deposition process is used to deposit a second layer of the low-k dielectric material. The method for manufacturing a semiconductor device according to claim 10, wherein performing the first wet deslagging process includes heating a mixture of sulfuric acid and hydrogen peroxide to a temperature of 80°C to 180°C. The manufacturing method of a semiconductor device according to claim 10, wherein the volume of the first source/drain structures is larger than that of the second source/drain structures. The method for manufacturing a semiconductor device according to claim 10, wherein the first anisotropic etching process etches the first spacer structures more than the second anisotropic etching process etches the second spacer structures. A method for manufacturing a semiconductor device includes: Forming a first fin extending from a base; Forming a first gate stack above and along the sidewall of the first fin; Forming a first spacer along the sidewall of the first gate stack, the first spacer including a first composition of silicon oxycarbide; A second spacer is formed along the sidewall of the first spacer, and the second spacer includes a second composition of silicon oxycarbide; Forming a third spacer along the sidewall of the second spacer, the third spacer including silicon nitride; and A first epitaxial source/drain region is formed in the first fin and adjacent to the third spacer. For example, the manufacturing method of the semiconductor device of claim 18 further includes: Forming a second fin extending from the base; Forming a second gate stack above and along the sidewall of the second fin; A fourth spacer is formed along the sidewall of the second gate stack, the fourth spacer includes the first composition of the silicon oxycarbide; A fifth spacer is formed along the sidewall of the fourth spacer, and the fifth spacer includes the second composition of the silicon oxycarbide; A sixth spacer is formed along the sidewall of the fifth spacer, the sixth spacer includes silicon nitride; and A second epitaxial source/drain region is formed in the second fin adjacent to the sixth spacer, wherein the volume of the second epitaxial source/drain region is different from that of the first epitaxial source /Volume of the drain region. The method of manufacturing a semiconductor device according to claim 18, wherein the first fin includes silicon germanium.

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