KR20200037110A - Semiconductor device and method - Google Patents

Abstract

According to the present invention, provided is a method comprising the steps of: forming a first fin extending from a substrate; forming a first gate stack over the first fin and along a sidewall of the first fin; forming a first spacer along a sidewall of the first gate stack, wherein the first spacer includes a first composition of silicon oxide carbide; forming a second spacer along a sidewall of the first spacer, wherein the second spacer includes a second composition of silicon oxide carbide; forming a third spacer along a sidewall of the second spacer, wherein the third spacer includes silicon nitride; and forming a first epitaxial source/drain region within the first fin and adjacent to the third spacer.

Description

Semiconductor device and method {SEMICONDUCTOR DEVICE AND METHOD}

[Priority claim and cross-reference]

This patent application claims priority to U.S. Provisional Patent Application No. 62 / 738,881, filed on September 28, 2018 and entitled "Semiconductor Device and Method." The patent application is hereby incorporated by reference in its entirety as if to be reproduced.

Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically manufactured by sequentially depositing an insulator or dielectric layer, a conductive layer, and a layer of semiconductor material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and devices.

The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) with continuous reduction in minimum feature size, allowing more components to be integrated into a given area do. However, when the minimum feature size is reduced, there are additional problems to be solved.

Aspects of the present disclosure may be best understood by reading the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. Indeed, the dimensions of the various features can be arbitrarily increased or decreased for clarity of explanation. In addition, the drawings are illustrative and not intended to be limiting as examples of embodiments of the invention.
1 shows an example of a FinFET according to some embodiments in a three-dimensional view.
2, 3, 4, 5, 6, 7, 8A, 8B, 9A, and 9B are cross-sectional views of intermediate steps in the manufacturing process of a FinFET in accordance with some embodiments.
10 is a graph showing simulation data of a change in parasitic capacitance of a FinFET device with respect to a dielectric constant of a spacer of a FinFET device according to some embodiments.
11A and 11B are cross-sectional views of an intermediate step in the manufacturing process of a FinFET according to some embodiments.
12A and 12B are cross-sectional views of a first wet cleaning process at an intermediate stage in the manufacturing process of a FinFET in accordance with some embodiments.
13A, 13B, 14A, and 14B are cross-sectional views of an intermediate step in the manufacturing process of a FinFET in accordance with some embodiments.
15A and 15B are cross-sectional views of a second wet cleaning process at an intermediate stage in the manufacturing process of a FinFET in accordance with some embodiments.
16A, 16B, 17A, 17B, 18A, and 18B are cross-sectional views of an intermediate step in the manufacturing process of a FinFET in accordance with some embodiments.
19A and 19B are cross-sectional views of the formation of an epitaxial source / drain region in an intermediate step in the manufacturing process of a FinFET in accordance with some embodiments.
20A, 20B, 21A, 21B, 22A, 22B, 23A, 23B, 24, 25A, 25B, 26A, and 26B are in the middle of a FinFET manufacturing process according to some embodiments It is a cross-section of steps.
27 is a graph showing experimental data of a carbon concentration change in a spacer layer of a FinFET device according to some embodiments.

The disclosure below provides many different embodiments or examples for implementing different features of the disclosure. To simplify the present disclosure, certain examples of components and arrangements are described below. Of course, this is only an example and is not intended to be limiting. For example, in the following description, the formation of the first feature on or over the second feature may include embodiments in which the first and second features are formed in direct contact, and additional features may also be included in the first feature. And an embodiment formed between the second features so that the first and second features are not in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for simplicity and clarity and does not itself represent the relationship between the various embodiments and / or configurations discussed.

Also, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. are shown in the drawings. In describing a relationship between one element or feature being different from another element (s) or feature (s), it may be used for convenience of description. The spatially relative terms encompass, in addition to the directions shown in the figures, different directions of the device being used or in operation. The equipment can be placed in different directions (rotated 90 degrees or rotated in different directions), and the spatially relative predicates used in the present disclosure can be interpreted accordingly.

Various embodiments provide a process for forming a gate spacer and forming an epitaxial source / drain region in a FinFET device. In some embodiments, low-k materials such as silicon oxide carbide can be used for some or all of the gate spacers. The use of silicon oxide carbide for the gate spacer can reduce parasitic capacitance in FinFET devices. Also, selectively masking the device regions and individually etching the recesses for the epitaxial source / drain regions in each device region uses the same epitaxial formation process to create different epitaxial source / drain regions in each device region. It can be formed at the same time. Thus, epitaxial source / drain regions for different types of devices can be formed simultaneously to have properties for each type of device. By using a wet chemical process of heated sulfuric acid and hydrogen peroxide, the damage to the silicon carbide layer can be reduced by cleaning and preparing the surface before each multiple patterning step. Thus, both the benefits of silicon carbide and the benefits of multiple patterning can be achieved in process flows with low probability of processing defects.

1 shows an example of a FinFET according to some embodiments in a three-dimensional view. The FinFET includes fins 52 on a substrate 50 (eg, a semiconductor substrate). The isolation region 56 is disposed on the substrate 50, and the pins 52 protrude upward from between adjacent isolation regions 56. Although the isolation region 56 is described / shown as being separated from the substrate 50, the term “substrate” as used in the present disclosure may be used to refer to only a semiconductor substrate or semiconductor substrate comprising an isolation region. Further, the pin 52 is shown as a single continuous material with the substrate 50, but the pin 52 and / or the substrate 50 may include a single material or a plurality of materials. The gate dielectric layer 92 is located along the sidewalls of the fin 52 and over the top surface, and the gate electrode 94 is positioned over the gate dielectric layer 92. The source / drain regions 82 are disposed on both sides of the fin 52 with respect to the gate dielectric layer 92 and the gate electrode 94.

1 further shows a reference cross-section used in the following figures. The cross-sections A-A are located along the longitudinal axis of the gate electrode 94 and in a direction perpendicular to the direction of current flow, for example between the source / drain regions 82 of the FinFET. The cross section B-B is perpendicular to the cross section A-A and is located along the longitudinal axis of the fin 52 and in the direction of current flow, for example between the source / drain regions 82 of the FinFET. Section C-C is parallel to section A-A and extends through the source / drain regions of the FinFET. Subsequent drawings refer to these reference sections for clarity.

Some embodiments discussed in this disclosure are discussed in the context of FinFETs formed using a gate last process. In other embodiments, a gate priority process can be used. Also, some embodiments contemplate aspects used in planar devices such as planar FETs.

2 to 9B and FIGS. 11A to 26B are cross-sectional views of intermediate steps of a manufacturing process of a FinFET according to some embodiments. 2 to 7 show the reference cross-section A-A shown in FIG. 1, with the exception of multiple pins / FinFETs. 8A to 9B, 11A and 11B, and 20A to 26B, except for the multi-pin / FinFET, the drawing ending with the name "a" is shown along the reference section AA shown in FIG. 1, Drawings ending with the name "b" are shown along similar cross-section BB shown in FIG. 1. 12A to 19B, except for the multi-pin / FinFET, the drawing ending with the name "a" is shown along the reference cross-section CC shown in FIG. 1, and the drawing ending with the "b" name is shown in FIG. A similar cross-section BB is shown. FIG. 24 is shown along the reference cross-section B-B shown in FIG. 1, with the exception of multiple fins / FinFETs.

In Figure 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may or may not be doped (eg, with a p-type or n-type dopant). . The substrate 50 may be a wafer such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon substrate or a glass substrate. Other substrates such as multilayer or gradient substrates can also be used. In some embodiments, the semiconductor material of the substrate 50 is silicon; germanium; Compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; Alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; Or combinations thereof.

The substrate 50 has a region 50N and a region 50P. The region 50N may be for forming an n-type device, such as an NMOS transistor, for example, an n-type FinFET. The region 50P may be for forming a p-type device such as a PMOS transistor, for example, a p-type FinFET. Region 50N can be physically separated from region 50P (as shown by divider 51), and can be any number of device features (eg, other active devices, doped regions, isolation structures, etc.) ) May be disposed between the region 50N and the region 50P. In some embodiments, both region 50N and region 50P are used to form the same type of device (eg both regions are for n-type devices or p-type devices).

In some embodiments, two or more types of n-type devices may be formed in the region 50N, or two or more types of p-type devices may be formed in the region 50P. For example, in some embodiments, the region 50P includes a sub-region 50P-1 where a first p-type device (eg, a p-type FinFET of the first design) is formed and a second p-type device (eg For example, a sub-region 50P-2 on which a second type p-type FinFET) is formed may be included. (See, for example, the embodiments described below in connection with FIGS. 12A-19B.) In some embodiments, different devices within different sub-regions may have multiple patterning processes (eg, “2P2E” processes or other types of processes). Multiple patterning process). The region 50N may similarly include sub-regions in which different n-type devices are formed. In some embodiments, the region 50N or the region 50P may include only one region or two or more sub-regions. The sub-regions may be physically separated from other sub-regions, and any number of device features may be disposed between the sub-regions.

In Fig. 3, a pin 52 is formed on the substrate 50. The pin 52 is a semiconductor strip. In some embodiments, fins 52 may be formed on the substrate 50 by etching the trench of the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. Etching can be anisotropic.

The pin can be patterned by any suitable method. For example, the pins can be patterned using one or more photolithography processes, including dual patterning or multiple patterning processes. In general, a double patterning or multiple patterning process can combine a photolithography and self-alignment process to create a pattern with a smaller pitch than can be achieved using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a photolithography process. The spacer is formed with a patterned sacrificial layer using a self-aligning process. The sacrificial layer can then be removed and the pins can be patterned using the remaining spacers.

In FIG. 4, an insulating material 54 is formed over the substrate 50 and between neighboring fins 52. The insulating material 54 may be an oxide, nitride, etc., such as silicon oxide, or a combination thereof, High Density Plasma Chemical Vapor Deposition (HDP-CVD), Flowable CVD (FCVD) ( For example, it can be formed by depositing a CVD-based material in a remote plasma system and converting it to another material, such as oxide, by post-cure), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material 54 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, insulating material 54 is formed such that excess insulating material 54 covers fin 52. The insulating material 54 is shown as a single layer, but some embodiments may use multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along the surface of the substrate 50 and pin 52. Thereafter, a filling material as discussed above can be formed over the liner.

In FIG. 5, a removal process is applied to the insulating material 54 to remove excess insulating material 54 over the fins 52. In some embodiments, a planarization process such as Chemical Mechanical Polish (CMP), etch back process, combinations thereof, and the like can be used. The planarization process exposes the fins 52 so that the top surfaces of the fins 52 and the insulating material 54 are level after the planarization process is completed.

In FIG. 6, the insulating material 54 is recessed to form a shallow trench isolation (STI) region 56. The insulating material 54 is recessed such that the top of the pin 52 in the region 50N and the region 50P protrudes between neighboring STI regions 56. In addition, the top surface of the STI region 56 can have a flat surface, convex surface, concave surface (eg dishing), or a combination thereof, as shown. The top surface of the STI region 56 can be formed flat, convex, and / or concave by appropriate etching. The STI region 56 uses, for example, an etching process that is selectively acceptable for the material of the insulating material 54 (eg, the material of the insulating material 54 at a faster rate than the material of the fin 52). By etching). For example, chemical oxides can be removed by a suitable etching process using dilute hydrofluoric (dHF) acid.

The process described with respect to FIGS. 2-6 is only an example of how the fin 52 is formed. In some embodiments, fins may be formed by an epitaxial growth process. For example, a dielectric layer can be formed over the top surface of the substrate 50, and a trench can be etched through the dielectric layer to expose the underlying substrate 50. The homoepitaxial structure can grow epitaxially in the trench, and the dielectric layer is recessed so that the homoepitaxial structure protrudes from the dielectric layer to form a fin. Also, in some embodiments, a heteroepitaxial structure can be used for the fin 52. For example, the pin 52 of FIG. 5 may be recessed, and a material different from the pin 52 may be epitaxially grown on the recessed pin 52. In this embodiment, the pin 52 includes a recessed material as well as an epitaxially grown material disposed over the recessed material. In another embodiment, a dielectric layer can be formed over the top surface of the substrate 50 and a trench can be etched through the dielectric layer. Next, the heteroepitaxial structure can be epitaxially grown in the trench using a different material than the substrate 50, and the dielectric layer is recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. You can. In some embodiments where the homoepitaxial or heteroepitaxial structure is epitaxially grown, the epitaxially grown material may be doped in situ during growth, and in situ and implantation doping may be used together. In this way, pre- and subsequent infusions can be excluded.

Also, it may be advantageous to epitaxially grow a material in the region 50N (eg, NMOS region) that is different from the material in the region 50P (eg, PMOS region). In various embodiments, the top of fin 52 is silicon germanium (Si _x Ge _1-x , where x can range from 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductor , II-VI compound semiconductors, and the like. For example, materials available for forming III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

Further, in FIG. 6, an appropriate well (not shown) can be formed in the fin 52 and / or the substrate 50. In some embodiments, a P well may be formed in the region 50N, and an N well may be formed in the region 50P. In some embodiments, P wells or N wells are formed in both region 50N and region 50P.

In embodiments with different well types, different implantation steps for region 50N and region 50P may be achieved using a photoresist or other mask (not shown). For example, photoresist may be formed on the fin 52 and the STI region 56 in the region 50N. The photoresist is patterned to expose an area 50P of the substrate 50, such as a PMOS area. Photoresists can be formed using spin-on techniques and patterned using acceptable photolithography techniques. When the photoresist is patterned, implantation of n-type impurities is performed in the region 50P, and the photoresist can act as a mask that substantially prevents n-type impurities from being implanted into the region 50N, such as the NMOS region. The n-type impurity may be phosphorus, arsenic or the like injected into the region at a concentration of 10 ¹⁸ cm ^-3 or less, such as about 10 ¹⁷ cm ^-3 to about 10 ¹⁸ cm ^-3 . After implantation, the photoresist is removed, for example, by an acceptable ashing process.

After implantation of region 50P, photoresist is formed over fin 52 and STI region 56 of region 50P. The photoresist is patterned to expose the region 50N of the substrate 50, such as the NMOS region. Photoresists can be formed using spin-on techniques and patterned using acceptable photolithography techniques. When the photoresist is patterned, implantation of p-type impurities is performed in the region 50N, and the photoresist can act as a mask that substantially prevents p-type impurities from being injected into the region 50P, such as the PMOS region. The p-type impurity may be boron, BF ₂ or the like injected into the region at a concentration of 10 ¹⁸ cm ^-3 or less, such as about 10 ¹⁷ cm ^-3 to about 10 ¹⁸ cm ^-3 . After implantation, the photoresist is removed, for example, by an acceptable ashing process.

After implantation of the regions 50N and 50P, annealing may be performed to activate the implanted p-type and / or n-type impurities. In some embodiments, the epitaxial growth material can be in-situ doped during growth, and in-situ and infusion doping can be used together, but this can exclude infusion.

In FIG. 7, a dummy dielectric layer 60 is formed on the fin 52. The dummy dielectric layer 60 may be, for example, silicon oxide, silicon nitride, or a combination thereof, and may be deposited or thermally grown depending on acceptable techniques. The dummy gate layer 62 is formed on the dummy dielectric layer 60, and the mask layer 64 is formed on the dummy gate layer 62. After the dummy gate layer 62 is deposited on the dummy dielectric layer 60, it may be planarized by CMP or the like. The mask layer 64 may be deposited on the dummy gate layer 62. The dummy gate layer 62 may be a conductive material, and may be selected from the group comprising polysilicon, polycrystalline silicon-germanium, metal nitride, metal silicide, metal oxide, and metal. In one embodiment, amorphous silicon is deposited and recrystallized to produce polysilicon. The dummy gate layer 62 may be deposited by Physical Vapor Deposition (PVD), CVD, sputter deposition, or other techniques known in the art and used to deposit conductive materials. The dummy gate layer 62 may be made of another material having high etch selectivity from etching of the isolation region. The mask layer 64 may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed over the region 50N and the region 50P. In some embodiments, separate dummy gate layers may be formed in the regions 50N and 50P, and separate mask layers may be formed in the regions 50N and 50P. The dummy dielectric layer 60 is shown to cover only the fin 52 for illustrative purposes. In some embodiments, dummy dielectric layer 60 may be deposited such that dummy dielectric layer 60 extends between dummy gate layer 62 and STI region 56 to cover STI region 56.

8A-9B, 11A and 11B illustrate various additional steps in the manufacturing process of a device embodiment. 8A to 9B, 11A, and 11B describe features of one of the region 50N and the region 50P. For example, the illustrated structure may be applicable to both region 50N and region 50P. The differences (if any) in the structures of the regions 50N and 50P are described in the text accompanying each figure.

8A and 8B, the mask layer 64 can be patterned using acceptable photolithography and etching techniques to form the mask 74. Next, the pattern of the mask 74 may be transferred to the dummy gate layer 62. In some embodiments, the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 by an acceptable etching technique, forming a dummy gate 72 over the rest of the dummy dielectric layer 60. In some embodiments (not shown separately), dummy dielectric layer 60 may not be patterned. The dummy gate 72 covers each channel region 58 of the fin 52. The pattern of the mask 74 can be used to physically separate each dummy gate 72 from adjacent dummy gates. The dummy gate 72 may also have a longitudinal direction substantially perpendicular to the longitudinal direction of each epitaxial fin 52.

8A and 8B, the first spacer material 78 is formed on the exposed surfaces of the dummy gate 72, mask 74 and / or fin 52. The first spacer material 78 is used to form the first spacer 80 (see FIGS. 11A and 11B). In some embodiments, the first spacer material 78 may be a material such as oxide, nitride, silicon oxynitride, silicon oxycarbonitride, silicon oxycarbide, or the like, or combinations thereof. In some embodiments, the first spacer material 78 can be formed using processes such as thermal oxidation, CVD, PE-CVD, ALD, PVD, sputtering, and the like. In FIG. 8B, the first spacer material 78 is shown extending vertically over the dummy gate 72 and mask 74 and extending laterally over the fin 52. In some embodiments, the first spacer material 78 can include multiple layers of one or more materials. In some embodiments, the first spacer material 78 can be formed to have a thickness of about 3 nm to about 5 nm.

In some cases, parasitic capacitance of a device (eg, a FinFET device) can be reduced by using a material having a smaller dielectric constant (k). For example, if a first spacer material 78 having a smaller dielectric constant is used to form the first spacer 80, for example, the gate electrode 94 and the source / drain contact 112 (FIG. 26A) And FIG. 26B) can reduce parasitic capacitance in the FinFET device. In some embodiments, first spacer material 78 may include a material having a dielectric constant less than about k = 3.9, such as about k = 3.5 or less. For example, in some embodiments, a silicon oxide carbide material can be used as the first spacer material 78. Since silicon carbide has a dielectric constant of about k = 3.5 or less, the use of silicon oxide as the first spacer material 78 can reduce parasitic capacitance in the FinFET device. In some embodiments, silicon carbide materials can be deposited using techniques such as ALD. In some embodiments, the silicon carbide material can be deposited using a process temperature from about 50 ° C to about 80 ° C and a process pressure from about 5 torr to about 10 torr. In some embodiments, the silicon oxide carbide may be formed to have about 40 atomic% to about 46 atomic% silicon, about 45 atomic% to about 50 atomic% oxygen, or about 5 atomic% to about 18 atomic% carbon. have. In some embodiments, different regions or different layers of the first spacer material 78 may contain different compositions of silicon oxide carbide.

After formation of the first spacer material 78, implantation for Lightly Doped Source / Drain (LDD) regions (not explicitly shown) may be performed. In embodiments with different device types, similar to the implantation described above in FIG. 6, while exposing area 50P, a mask, such as a photoresist, can be formed over area 50N, and of the appropriate type (eg , n-type or p-type impurities may be injected into the fin 52 in the region 50P through the first spacer material 78. Thereafter, the mask can be removed. Subsequently, while exposing the region 50N, a mask, such as a photoresist, may be formed over the region 50P, and an appropriate type of impurity may pass through the first spacer material 78 to pin 52 in the region 50N. Can be injected into. Thereafter, the mask can be removed. The n-type impurity may be one of the n-type impurities described in FIG. 6 or another n-type impurity, and the p-type impurity may be one of the p-type impurities described in FIG. 6 or another p-type impurity. The harding source / drain region may have an impurity concentration of about 10 ¹⁵ cm ^-3 to about 10 ¹⁶ cm ^-3 . Annealing can be used to activate the implanted impurities. Since the LDD dopant implantation is performed through the first spacer material 78, a portion of the first spacer material 78 (and a portion of the first spacer 80) can also be doped with implanted impurities. As such, in some embodiments, the first spacer material 78 may have a higher concentration of impurities than the second spacer material 79 (see FIGS. 9A and 9B) formed after implantation of impurities.

9A and 9B, a second spacer material 79 is formed on the first spacer material 78. The second spacer material 79 is used to form the second spacer 81 (see FIGS. 11A and 11B). In some embodiments, the second spacer material 79 may be a material such as oxide, nitride, silicon oxynitride, silicon oxycarbonitride, silicon oxycarbide, or the like, or a combination thereof. In some embodiments, the second spacer material 79 may be formed using processes such as CVD, PE-CVD, ALD, PVD, sputtering, and the like. In some embodiments, the second spacer material 79 can include multiple layers of one or more materials. In some embodiments, the second spacer material 79 may be formed to have a thickness of about 3 nm to about 5 nm. Since the second spacer material 79 is formed after implantation of impurities, the second spacer material 79 may have a lower impurity concentration than the first spacer material 78. In some embodiments, second spacer material 79 and second spacer 81 are omitted (not shown separately).

Similar to the first spacer material 78 described above (see FIG. 8B), by forming the second spacer 81 (see FIG. 11B) from the second spacer material 79 having a low dielectric constant, a device (eg, For example, parasitic capacitance may be reduced in a FinFET device). In some embodiments, the second spacer material 79 may include silicon oxide carbide, and thus may have a dielectric constant less than about k = 3.9, such as about k = 3.5 or less. The silicon carbide material of the second spacer material 79 can be formed in a similar manner to that described above to form the silicon carbide of the first spacer material 78, but in other embodiments the second spacer material 79 This can be formed differently. The composition of silicon oxide of the second spacer material 79 may be similar to that described above for silicon oxide of the first spacer material 78.

In some embodiments, both the first spacer material 78 of the first spacer 80 and the second spacer material 79 of the second spacer 81 may be formed of silicon oxide carbide. The first spacer material 78 and the second spacer material 79 may have approximately the same silicon oxide carbide composition or may have different compositions. For example, the first spacer material 78 may have a composition of about 45 atomic% to about 48 atomic% oxygen and / or about 12 atomic% to about 15 atomic% carbon. The second spacer material 79 may have a composition of about 47 atomic% to about 50 atomic% oxygen and / or about 10 atomic% to about 13 atomic% carbon. The first spacer material 78 or the second spacer material 79 may have a composition other than these examples. In some cases, forming both the first spacer material 78 of the first spacer 80 and the second spacer material 79 of the second spacer 81 with silicon oxide carbide is a material having a higher dielectric constant. The parasitic capacitance may be further reduced than forming one or both of the first spacer 80 or the second spacer 81 with different materials, such as.

Referring to FIG. 10, the graph shows simulation data of a rate of change of parasitic capacitance of the FinFET device (Y-axis) with respect to the dielectric constant k of the second spacer 81 (X-axis). The change in parasitic capacitance is a point 121 representing both the first spacer material 78 of the first spacer 80 and the second spacer material 79 of the second spacer 81 having a dielectric constant of about k = 5. It is about. Point 122 represents the change in capacitance due to the first spacer material 78 having a dielectric constant of about k = 5 and the second spacer material 79 having a dielectric constant of about k = 4. As shown, the smaller dielectric constant of the second spacer material 79 reduces the parasitic capacitance by about 2%.

Referring again to FIG. 10, point 123 is formed of a first spacer material 78 of a first spacer 80 having a dielectric constant of about k = 5 and silicon oxide carbide having a dielectric constant of about k = 3.5. It represents a change in capacitance due to the second spacer material 79 of the second spacer 81. As shown, the smaller dielectric constant of silicon oxide reduces parasitic capacitance by about 3.5%. Point 124 represents the change in capacitance due to both the first spacer material 78 and the second spacer material 79 formed of silicon oxide having a dielectric constant of about k = 3.5. As shown, by forming both the first spacer material 78 and the second spacer material 79 from silicon oxide carbide, the parasitic capacitance can be reduced by about 6.5%. Thus, as shown in the graph of FIG. 10, forming both the first spacer material 78 of the first spacer 80 and the second spacer material 79 of the second spacer 81 with silicon oxide carbide It can reduce parasitic capacitance of devices such as FinFET devices. The graphs and simulation data shown in FIG. 10 are for illustration, and in other cases, the dielectric constant of the first spacer material 78 or the second spacer material 79 is different, or in other cases, the first spacer material 78 And a change in capacitance of the second spacer material 79 for various materials.

11A and 11B, a first spacer 80, a second spacer 81, and sidewall spacers 86 are formed. The sidewall spacers 86 may be formed, for example, by conformally depositing an insulating material over the second spacer material 79 and then anisotropically etching the insulating material. In some embodiments, anisotropic etching of the insulating material also etches the first spacer material 78 to form the first spacer 80 and etches the second spacer material 79 to form the second spacer 81. . As described above for the second spacer material 79 and the first spacer material 78, the second spacer 81 may have a lower concentration of implanted impurities than the first spacer 80. In some embodiments, the insulating material of the sidewall spacer 86 is phosphosilicate glass (PSG), borophosphosilicate glass (BoroPhosphoSilicate Glass; BPSG), fluorinated silicate glass (FSG), silicon It may be a low-k dielectric material such as nitride, silicon oxide carbide, silicon carbide, silicon carbonitride, or the like, or a combination thereof. The material of the sidewall spacer 86 can be formed by any suitable method, such as CVD, PE-CVD, ALD, and the like. In some embodiments, sidewall spacers 86 may have a thickness of about 3 nm to about 5 nm.

12A-B, epitaxial source / drain regions 82A and 82B are formed in fin 52, in accordance with some embodiments. 12A-19B show the formation of epitaxial source / drain regions 82A in sub-regions 50P-1 and the formation of epitaxial source / drain regions 82B in sub-regions 50P-2. The sub-region 50P-1 and the sub-region 50P-2 may be sub-regions of the region 50P of the substrate 50. Region 50N and epitaxial source / drain regions of region 50P (including epitaxial source / drain regions 82A and 82B) may be collectively referred to as epitaxial source / drain regions 82 in this disclosure. . 12A, 13A, 14A, 15A, 16A, 17A, 18A, and 19A are shown along the reference cross-section CC shown in FIG. 1, and FIGS. 12B, 13B, 14B, and 15B , FIGS. 16B, 17B, 18B and 19B are shown along the reference cross-section BB shown in FIG. 1. An epitaxial source / drain region 82 is formed in the fin 52 such that each dummy gate 72 is disposed between each neighboring pair of epitaxial source / drain regions 82. In some embodiments, epitaxial source / drain regions 82 extend to fins 52. In some embodiments, sidewall spacers 86 are epitaxial source / drain from dummy gate 72 by an appropriate lateral distance so that epitaxial source / drain region 82 does not short-circuit the resulting resulting FinFET gate. Used to separate region 82.

12A and 12B, a first wet cleaning process 95A is performed. The first wet cleaning process 95B may be a wet chemical cleaning process (eg, a “descum” process) that removes residue from the surface. The first wet scrubbing process 95A may also include a surface treatment that allows oxygen atoms to bond to the surface of the sidewall spacers 86, which reduces gas evolution of species such as nitrogen or hydrogen during subsequent process steps. In some cases, gas removal (eg, NH _x gas removal) can cause defects (sometimes referred to as "photoresist poisons") during photoresist development. A first wet cleaning process 95A may be performed to prepare a structure for formation of the mask 91A (see FIGS. 13A and 13B).

In some embodiments, the first wet cleaning process 95A can include a heated mixture of sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ). The mixture can be, for example, sulfuric acid and hydrogen peroxide mixed in a molar ratio of about 2: 1 to about 5: 1. The mixture can be heated to a temperature of about 80 ° C to about 180 ° C. During the first wet cleaning process 95A, the structure can be immersed, for example, in a heated mixture. Such mixtures described in this disclosure can remove residues and also reduce the likelihood of photolithography-related defects during photoresist patterning, such as defects due to “photoresist poisons”.

In addition, the heated mixture of sulfuric acid and hydrogen peroxide used in the first wet cleaning process 95A may have a first spacer (such as a plasma based technology (e.g., using hydrogen plasma, oxygen plasma, etc.)) than other cleaning technologies. 80) and the second spacer 81 may be less damaged. For example, some oxygen plasma cleaning techniques can deplete the silicon oxide carbide layer of carbon, thereby damaging the layer, thus also causing possible processing problems or defects. Thus, the use of the mixtures described in this disclosure can reduce photolithography-related defects (eg, “photoresist poisons”) as well as damage-related defects when silicon oxide carbide materials are used. For example, by using the mixture described in the present disclosure for the first wet cleaning process 95A, both the first spacer 80 and the second spacer 81 are silicones with reduced overall probability of treatment problems or defects It may be formed of an oxide carbide material. In this way, the advantage of using both a cleaning process (eg, improved photolithography) and a silicon oxide carbide material (eg, reduced parasitic capacitance) can be realized.

13A and 13B, a mask 91A is formed on the sub-region 50P-2. The mask 91A may include a single layer or may be a multi-layer structure (eg, a double-layer structure, a triple-layer structure, or a structure having more than three layers). The mask 91A may include a material such as a photoresist material, oxide material, nitride material, other dielectric material, or a combination thereof. In some embodiments, the mask 91A includes a bottom anti-reflective coating (BARC). The mask 91A can be formed using one or more suitable techniques, such as spin-on technology, CVD, PE-CVD, ALD, PVD, sputtering, or a combination thereof. The mask 91A can be patterned to expose a portion of the sub-region 50P-1 using an appropriate photolithography and etching process. For example, one or more wet etching processes or anisotropic dry etching processes may be used to etch the mask 91A.

14A and 14B, a recess 84A is formed in the fin 52 of the sub-region 50P-1, according to some embodiments. The recess 84A can be formed using, for example, an anisotropic dry etching process. In some cases, a portion of the first spacer 80, second spacer 81, or sidewall spacer 86 may also be etched by an anisotropic dry etch process. The exemplary etching of the spacers 80, 81 and 86 shown in FIG. 14A is intended to be exemplary, and the anisotropic dry etching process may etch the spacers 80, 81 or 86 differently in other embodiments. For example, in other embodiments, the anisotropic dry etch process may include a spacer (such that one or more spacers 80, 81 or 86 extend higher above the STI region 56 than the other spacer 80, 81 or 86). Portions of 80, 81 and 86) can be etched in different amounts. These and other modifications are intended to be within the scope of this disclosure. In some embodiments, the process parameters of the anisotropic dry etch process can be controlled to etch the recess 84A or spacers 80, 81 or 86 to have the desired properties. Process parameters can include, for example, process gas mixtures, voltage bias, RF power, process temperature, process pressure, other parameters, or combinations thereof. In some cases, by controlling the etching of the recess 84A or the spacers 80, 81 or 86 in this manner, epitaxial source / drain regions 82A formed in the recess 84A (FIGS. 18A and 18B) Shape, volume, size or other characteristics of the reference) can be controlled.

15A and 15B, the mask 91A is removed and a second wet cleaning process 95B is performed. The mask 91A can be removed using a suitable process such as a wet chemical process or a dry process. After removing the mask 91A, a second wet cleaning process 95B is performed to prepare the surface of the structure to remove the residue and form the mask 91B (see FIGS. 16A and 16B). In some embodiments, the mask 91A is removed as part of performing the second wet cleaning process 95B. The second wet cleaning process 95B may be similar to the first wet cleaning process 95A (see FIGS. 12A and 12B). For example, the second wet cleaning process 95B can use a heated mixture of sulfuric acid and hydrogen peroxide. The mixture can have a composition similar to that described for the first wet cleaning process 95A, and can be heated to a similar temperature. In other cases, the second wet cleaning process 95B may be a mixture of sulfuric acid and hydrogen peroxide that is different from that used in the first wet cleaning process 95A and can be heated to different temperatures. Similar to the first wet cleaning process 95A, using a heated mixture of sulfuric acid and hydrogen peroxide, as in the embodiment where the first spacer 80 and / or the second spacer 81 is formed of silicon carbide, Damage to the silicon oxide layer can be reduced.

16A and 16B, a mask 91B is formed on the sub-region 50P-1. The mask 91B may include a single layer or may be a multi-layer structure (eg, a double-layer structure, a triple-layer structure, or a structure having more than three layers). The mask 91B may include a material such as photoresist material, oxide material, nitride material, other dielectric material, or a combination thereof. In some embodiments, the mask 91B includes a bottom anti-reflective coating (BARC). The mask 91B may be formed using one or more suitable techniques, such as spin-on technology, CVD, PE-CVD, ALD, PVD, sputtering, or a combination thereof. The mask 91B can be patterned to expose a portion of the sub-region 50P-1 using an appropriate photolithography and etching process. For example, one or more wet etching processes or anisotropic dry etching processes can be used to etch the mask 91B. The mask 91B may be similar to the mask 91A (see FIGS. 13A and 13B), or may be different from the mask 91A.

17A and 17B, a recess 84B is formed in the fin 52 of the sub-region 50P-2, according to some embodiments. The recess 84B may be formed using, for example, an anisotropic dry etching process. In some cases, a portion of the first spacer 80, second spacer 82, or sidewall spacer 86 may also be etched by an anisotropic dry etching process. In some embodiments, the process parameters of the anisotropic dry etch process can be controlled to etch the recess 84B or spacers 80, 81 or 86 to have the desired properties. The process parameter of etching for the sub-region 50P-2 may be different from the process parameter of etching for the sub-region 50P-1. Process parameters can include, for example, process gas mixtures, voltage bias, RF power, process temperature, process pressure, other parameters, or combinations thereof. In some embodiments, the recess 84B of the sub-region 50P-2 is different from the recess 84A of the sub-region 50P-1 (eg, having a different height, width, shape, etc.) Process parameters can be controlled. The process parameters may also be such that the spacers 80, 81 or 86 of the sub-area 50P-2 differ from the spacers 80, 81 or 86 of the sub-area 50P-1 (eg, different heights, widths, Shape). These are examples, and such and other modifications are intended to be within the scope of the present disclosure. In some cases, epitaxial source / drain regions 82B formed in recesses 84B (see FIGS. 19A and 19B) by controlling the etching of recesses 84B or spacers 80, 81 or 86 in this manner. ) Shape, volume, size or other characteristics can be controlled. By using separate different etching processes in the sub-regions 50P-1 and 50P-2, the epitaxial source / drain regions in each sub-region can be formed to have different characteristics.

18A and 18B, the mask 91B is removed. The mask 91B can be removed using a suitable process, such as a wet chemical process or a dry process. In this way, the source / drain regions of the sub-regions 50P-1 and 50P-2 can be prepared for the formation of epitaxial source / drain regions 82A and 82B (see FIGS. 19A and 19B). 12A-18B, a multiple patterning process can be used to etch different sub-regions differently. In some embodiments, the multiple patterning process can be a “2P2E” process, such as that described in FIGS. 12A-18B, where a second sub-region (eg, sub-region 50P-1) is etched during etching. One sub-region (eg, sub-region 50P-2) is masked, and then the second sub-region is masked while the first sub-region is etched. In another embodiment, before the sub-region 50P-2 is masked and the sub-region 50P-1 is etched, the sub-region 50P-1 is first masked and the sub-region 50P-2 is etched. . By sequentially masking and etching the appropriate sub-regions, two or more sub-regions can be etched using different etching processes in this manner. In addition, by using a wet cleaning process similar to the wet cleaning processes 95A and 95B, a wet cleaning process before each masking step can be performed while reducing the possibility of damage to the layer formed of silicon oxide.

19A and 19B, epitaxial source / drain regions 82 are formed in regions 50P, according to some embodiments. In some embodiments, a pre-cleaning process may first be performed to remove oxides (eg, natural oxides) from recesses 84A and 84B. The pre-cleaning process can include a wet chemical process (eg, diluted HF), a plasma process, or a combination thereof. Using the same epitaxial process, epitaxial source / drain regions 82A are formed in the recesses 84A of the sub-regions 50P-1, and epitaxial source / drain regions 82B are sub-regions 50P- It is formed in the recess 84B of 2). In some embodiments, additional epitaxial source / drain regions, if present, may be formed in different sub-regions using the same epitaxial process as in epitaxial source / drain regions 82A and 82B. The epitaxial source / drain regions 82A and 82B may include any acceptable material suitable for p-type FinFETs, for example. For example, when the pin 52 is silicon or SiGe, the epitaxial source / drain regions 82A and 82B may include SiGe, SiGeB, Ge, GeSn, other materials, or the like, or a combination thereof.

In some embodiments, a single epitaxial process can form different epitaxial source / drain regions in different sub-regions. Different etching processes performed in the sub-regions, forming a difference in the recesses (e.g., recesses 84A and 84B) or a spacer (e.g., spacers 80, 81 or 86) in the sub-regions Due to this, the epitaxial source / drain regions may be different. For example, as shown in FIG. 19A, epitaxial source / drain regions 82A formed in recesses 84A of sub-regions 50P-1 are single epitaxial source / drain regions 82A during epitaxy. ), But the epitaxial source / drain regions 82B formed in the recesses 84B of the sub-regions 50P-2 remain unmerged. In this way, epitaxial source / drain region 82A is formed to have a larger volume than epitaxial source / drain region 82B.

The merged epitaxial source / drain regions 82A and the unmerged epitaxial source / drain regions 82B, shown in FIGS. 19A and 19B, are formed in different sub-regions using the same epitaxial process. It is an illustration of the alternative source / drain regions, and such and other variations are also intended to be within the scope of the present disclosure. In other embodiments, epitaxial source / drain regions formed in different sub-regions may be different in other respects such as height, width, shape, volume, and profile. In this way, FinFET devices with different epitaxial source / drain regions can be formed using the same epitaxial process in different sub-regions. For example, a logic device may be formed in the first sub-region (eg, sub-region 50P-1), and the SRAM device may be formed in a second sub-region (eg, sub-region 50P-2). Can be formed on. These are examples and other types of devices are possible.

The epitaxial source / drain region 82 of the region 50N, for example the NMOS region, masks the region 50P, for example the PMOS region, and the source / drain region of the pin 52 in the region 50N. Is formed by etching to form a recess in the fin 52. Next, the epitaxial source / drain regions 82 of the region 50N may be epitaxially grown in the recess. The epitaxial source / drain region 82 of the region 50N is before or after forming the epitaxial source / drain region 82 in the region 50P (e.g., epitaxial shown in FIGS. 19A and 19B). Source / drain regions 82A and 82B). The epitaxial source / drain region 82 of region 50N may include any acceptable material suitable for n-type FinFETs. For example, when the pin 52 is silicon, the epitaxial source / drain region 82 of the region 50N may include silicon, SiC, SiCP, SiP, and the like. The epitaxial source / drain regions 82 of the region 50N may have a raised surface from each surface of the fin 52, may or may not be merged, or may have facets.

In some embodiments, region 50N may include sub-regions, and multiple patterning processes may be used to mask and etch separate sub-regions before forming epitaxial source / drain regions 82 in region 50N. You can. The multiple patterning process can be similar to the multiple patterning process performed on sub-regions 50P-1 and 50P-2 of region 50P, as described in FIGS. 12A-18B. In this way, different epitaxial source / drain regions can be formed in different sub-regions using the same epitaxial process, so different FinFET devices (e.g., SRAM devices, logic devices, etc.) are formed in different sub-regions. Can be. In some embodiments, multiple patterning processes may include one or more wet cleaning processes similar to wet cleaning processes 95A and 95B described above. In this way, during the multiple patterning process, silicon oxide carbide can be used for the first spacer 80 and the second spacer 81 in the region 50N with low probability of damage. In some embodiments, after forming the epitaxial source / drain regions in the region 50N or 50P or its sub-regions, sidewall spacers 86 may be removed. The sidewall spacers 86 can be removed using, for example, anisotropic dry etching.

Similar to the process discussed above to form the doping source / drain regions, a dopant may be injected into the epitaxial source / drain regions 82 and / or fins 52 to form the source / drain regions, the After it is annealed. The source / drain region may have an impurity concentration of about 10 ¹⁹ cm ^-3 to about 10 ²¹ cm ^-3 . The n-type and / or p-type impurity for the source / drain region may be any of the impurities described above. In some embodiments, epitaxial source / drain regions 82 may be doped in-situ during growth.

20A and 20B, the ILD 88 is deposited over the regions 50N and 50P. The structures shown in FIGS. 20A and 20B are exemplary structures in accordance with the formation of epitaxial source / drain regions 82, and the described processing steps may be applicable to any of the structures, embodiments, or devices described above. ILD 88 can be formed of a dielectric material or a semiconductor material, and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials include Phosphosilicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-doped PhosphoSilicate Glass (BPSG), Undoped Silicate Glass Glass; USG). The semiconductor material may include amorphous silicon, silicon germanium (Si _x Ge _1-x , where x can be between approximately 0 and 1), pure germanium, and the like. Other insulating or semiconductive materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the ILD 88 and the epitaxial source / drain regions 82, hard mask 74, and sidewall spacers 86. do. The CESL 87 may include dielectric materials such as silicon nitride, silicon oxide, silicon oxynitride, or the like, or combinations thereof.

21A and 21B, a planarization process such as CMP may be performed to planarize the top surface of the dummy gate 72 and the top surface of the ILD 88. The planarization process can also remove the mask 74 on the dummy gate 72, and along the sidewalls of the mask 74, the first spacer 80, the second spacer 81, and a portion of the sidewall spacer 86 can be removed. It can also be removed. After the planarization process, the top surfaces of the dummy gate 72, the first spacer 80, the second spacer 81, the sidewall spacer 86, and the ILD 88 are horizontal. Thus, the top surface of dummy gate 72 is exposed through ILD 88.

22A and 22B, a portion of the dummy gate 72 and a portion of the dummy dielectric layer 60 located immediately below the exposed dummy gate 72 is removed in one or more etching steps, thereby forming a recess 90. In some embodiments, dummy gate 72 is removed by an anisotropic dry etch process. For example, the etching process may include a dry etching process that uses one or more process gases to selectively etch the dummy gate 72 without etching the ILD 88 or gate spacer 86. Each recess 90 exposes the channel region of each fin 52. Each channel region 58 is disposed between neighboring pairs of epitaxial source / drain regions 82. During removal, the dummy dielectric layer 60 may be used as an etch stop layer when the dummy gate 72 is etched. The dummy dielectric layer 60 may be selectively removed after the dummy gate 72 is removed.

23A and 23B, in accordance with some embodiments, gate dielectric layer 92 and gate electrode 94 are formed for an alternate gate. As indicated, FIG. 24 shows a detailed view of FIG. 23B. The gate dielectric layer 92 is conformally deposited on the recess 90, such as on the top surface and sidewalls of the fins 52 and on the sidewalls of the first spacers 80. Gate dielectric layer 92 may also be formed on the top surface of first ILD 88. According to some embodiments, the gate dielectric layer 92 includes silicon oxide, silicon nitride, or multilayers thereof. In some embodiments, the gate dielectric layer 92 is a high-k dielectric material, and in these embodiments, the gate dielectric layer 92 can have a k value greater than about 7.0, Hf, Al, Zr, La, Mg, Metal oxides or silicates of Ba, Ti, and Pb, and combinations thereof. The method of forming the gate dielectric layer 92 may include atomic beam deposition (MBD), ALD, PECVD, or the like. In an embodiment where a portion of the dummy gate dielectric 60 remains in the recess 90, the gate dielectric layer 92 comprises a material (eg, silicon oxide) of the dummy gate dielectric 60.

Each of the gate electrodes 94 is deposited on the gate dielectric layer 92 and fills the rest of the recess 90. The gate electrode 94 may be a metal-containing material such as TiN, TiO, TaN, TaC, Co, Ru, Al, W, combinations thereof, or multiple layers thereof. For example, although the single layer gate electrode 94 is shown in FIG. 23B, the gate electrode 94 can be any number of liner layers 94A, any number of work function adjustment layers as shown in FIG. 94B and a filling material 94C. After filling the gate electrode 94, a planarization process such as CMP can be performed to remove the material of the gate electrode 94 and the excess portion of the gate dielectric layer 92, which excess portion is the top surface of the ILD 88 Up there. The remainder of the material of gate electrode 94 and gate dielectric layer 92 forms the replacement gate of the resulting FinFET. The gate electrode 94 and the gate dielectric layer 92 may be collectively referred to as a “gate stack”. The gate and gate stack can extend along sidewalls of the channel region 58 of the fin 52.

The formation of the gate dielectric layer 92 in the region 50N and the region 50P may occur simultaneously so that the gate dielectric layer 92 is formed of the same material in each region, and the formation of the gate electrode 94 is performed in each region. Can occur simultaneously so that the gate electrode 94 of is formed of the same material. In some embodiments, the gate dielectric layer 92 in each region is formed by a separate process, such that the gate dielectric layer 92 can be a different material, and / or the gate electrode 94 in each region is in a separate process. Formed by, the gate electrode 94 may be of a different material. Various masking steps can be used to mask and expose the appropriate area when using separate processes.

25A and 25B, ILD 108 is deposited over ILD 88. In one embodiment, ILD 108 is a flowable film formed by a flowable CVD method. In some embodiments, ILD 108 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method, such as CVD, PE-CVD, and the like.

26A and 26B, according to some embodiments, contacts 110 and 112 are formed through ILD 108 and ILD 88. In some embodiments, an annealing process may be performed to form a silicide at the interface between epitaxial source / drain region 82 and contact 112 before contact 112 is formed. The contact 110 is physically and electrically connected to the gate electrode 94, and the contact 112 is physically and electrically connected to the epitaxial source / drain region 82. 26A and 26B show contacts 110 and 112 of the same cross section. However, in other embodiments, the contacts 110 and 112 may be disposed in different cross sections. In addition, the locations of the contacts 110 and 112 in FIGS. 26A and 26B are merely exemplary and are not intended to be limiting in any way. For example, the contact 110 can be vertically aligned with the pin 52 as shown, or can be placed at a different location on the gate electrode 94. Further, the contacts 112 may be formed before, simultaneously, or after forming the contacts 110.

Referring to FIG. 27, the graph shows experimental data of measurement of the carbon concentration present in the first spacer 80 and the second spacer 81 formed of a silicon carbide material. Figure 27 shows the carbon concentrations measured after different treatment steps designated as steps (A, B, C and D). In FIG. 27, points 125A to 125D indicate the carbon concentration of the first sample, points 126A to 126D indicate the carbon concentration of the second sample, and points 127A to 127D indicate the carbon concentration of the third sample. Shows. As described in more detail below, the first wet cleaning process 95A and the second wet cleaning process are used to clean the first sample (points 125A to 125D) and the second sample (points 126A to 126D). (95B) is used, but an oxygen plasma process is used to clean the third sample (points 127A to 127D). The processing step (A) corresponds to the step after the formation of the first spacer 80 and the second spacer 81, and these points 125A, 126A and 127A represent the initial carbon concentration of the sample (eg, FIG. 11a and 11b).

The processing step (B) corresponds to a step after the 2P2E multiple patterning process described in FIGS. 12A to 18B is performed. However, the first sample (points 125A to 125D) and the second sample (points 126A to 126D) used the above-described first wet cleaning process 95A and second wet cleaning process 95B, whereas the first sample For the 3 samples (points 127A to 127D), separate oxygen plasma processes were used instead of the first wet cleaning process 95A and the second wet cleaning process 95B. As shown by points 125B and 126B, wet cleaning processes 95A and 95B performed on the first sample and the second sample include first and second spacers 80 and second spacers of the first and second samples ( The carbon concentration of 81) was reduced to about 50% of the initial carbon concentration (points 125A and 126A). As shown by point 127B, the oxygen plasma treatment performed on the third sample causes the carbon concentration of the first spacer 80 and the second spacer 81 to be about 10 of the initial carbon concentration (point 127A). %. The reduction in carbon concentration indicates an increase in damage to the first spacer 80 and the second spacer 81 due to the oxygen plasma process. Thus, FIG. 27 shows that the use of wet cleaning processes 95A and 95B can reduce the carbon concentration of silicon carbide materials less than other types of cleaning processes. The data shown in FIG. 27 is an illustrative example, and the use of wet cleaning processes 95A and 95B can reduce carbon concentrations to a greater or lesser extent in other cases.

The treatment step (C) corresponds to the step before the pre-cleaning process as described in FIGS. 19A and 19B is performed. As shown, the first sample (point 125C), the second sample (point 126C), and the third sample (point 127C) maintain approximately the same carbon concentration as in the treatment step (B). The processing step (D) corresponds to the step before the epitaxial source / drain regions 82A and 82B are formed as described in FIGS. 19A and 19B. As shown, the first sample (point 125D), the second sample (point 126D) and the third sample (point 127D) are approximately the same carbon as the treatment step (B) and treatment step (C). Maintain concentration. Thus, in some cases, the further treatment does not further reduce the carbon concentration after performing the wet cleaning processes 95A and 95B.

The embodiments described in this disclosure can achieve this. By using a wet cleaning process comprising a heated mixture of sulfuric acid and hydrogen peroxide, silicon carbide material can be used as part of the FinFET device with a low risk of damage to the silicon oxide material. For example, silicon oxide carbide materials can be used in one, two or more spacers formed on the sidewalls of the dummy gate during processing. Since silicon carbide has a relatively low dielectric constant, the use of silicon carbide (eg, as a material for spacers) in FinFET devices can reduce the parasitic capacitance of the FinFET device. For example, the parasitic capacitance between the metal gate and the source / drain contact can be reduced. By reducing parasitic capacitance, it is possible to improve the performance of FinFET devices, especially in high frequency operation. In addition, the use of the wet cleaning process mixtures described in this disclosure allows silicon carbide to be used more reliably in addition to multiple patterning techniques. For example, multiple patterning can be used to form devices having different epitaxial regions using the same epitaxial step, by using selective masking and different etching processes for different devices. This can provide the advantage of using silicon carbide, while reducing the overall processing steps, improving processing efficiency, and reducing manufacturing costs.

In one embodiment, a method includes forming a first fin and a second fin over a substrate, forming a first dummy gate structure over a first fin and forming a second dummy gate structure over a second fin, a first Depositing a first layer of silicon carbide material on the fin, on the second fin, on the first dummy gate structure, and on the second dummy gate structure, through the first layer of silicon oxide material Injecting impurities into the first fin and into the second fin, after implanting the impurities, depositing a second layer of silicon carbide material over the first layer of silicon oxide material, the second layer of silicon oxide carbide material After depositing, performing a wet cleaning process on the first fin and the second fin, forming a first mask on the second fin and the second dummy gate structure, and forming a first fin adjacent to the first dummy gate structure. By recessing, Forming a first recess in the first fin, after recessing the first fin, performing a wet cleaning process on the first fin and the second fin, a second mask over the first fin and the first dummy gate structure Forming, recessing a second fin adjacent to the second dummy gate structure, forming a second recess in the second fin, and performing an epitaxy process to perform a first epitaxial in the first recess And simultaneously forming a source / drain region and a second epitaxial source / drain region in the second recess. In one embodiment, the method performs an anisotropic etching process on a first layer of silicon oxide material, forming a first spacer on the first dummy gate structure, and anisotropic etching process on a second layer of silicon oxide material And forming a second spacer on the second dummy gate structure. In one embodiment, the first layer of silicon oxide material has a higher impurity concentration than the second layer of silicon oxide material. In one embodiment, the wet cleaning process includes using a heated mixture of sulfuric acid and hydrogen peroxide. In one embodiment, the mixture of sulfuric acid and hydrogen peroxide is mixed in a molar ratio between 2: 1 and 5: 1. In one embodiment, the heated mixture is at a temperature between 80 ° C and 180 ° C. In one embodiment, the method includes forming a sidewall spacer over the second layer of silicon carbide material, the sidewall spacer comprising a dielectric material different from the silicon oxide material. In one embodiment, at least two first epitaxial source / drain regions are merged with each other. In one embodiment, the first recess has a first depth and the second recess has a second depth different from the first depth.

In one embodiment, a method includes patterning a substrate to form a plurality of first fins and a plurality of second fins, forming a plurality of first dummy gate structures on the plurality of first fins, a plurality of Forming a plurality of second dummy gate structures on the second fin, forming a plurality of first spacer structures on the plurality of first dummy gate structures, and a plurality of second on the plurality of second dummy gate structures Forming a spacer structure, the plurality of first spacer structures and the plurality of second spacer structures comprising a low-k dielectric material, forming a plurality of second spacer structures, the first in the plurality of first fins A step of forming a recess, comprising: performing a first wet descum process, and performing a first anisotropic etching process to form a first recess in the plurality of first fins. 1 recess Forming, forming a first recess in the plurality of first fins, and then forming a second recess in the plurality of second fins, performing a second wet discom process, and a second anisotropy Performing an etch process to form a second recess comprising forming a second recess in the plurality of second fins, and epitaxially growing the first source / drain structure in the first recess and removing the second recess. And epitaxially growing the second source / drain structure in the two recesses. In one embodiment, the first source / drain structure and the second source / drain structure are simultaneously formed by the same epitaxial growth process. In one embodiment, the first anisotropic etching process is different from the second anisotropic etching process. In one embodiment, the low-k dielectric material is silicon oxide carbide. In one embodiment, forming the plurality of first spacer structures comprises depositing a first layer of low-k dielectric material using a first deposition process, and implanting a first layer of low-k dielectric material And after performing the implantation process, depositing a second layer of low-k dielectric material using a second deposition process. In one embodiment, performing the first wet descum process includes heating a mixture of sulfuric acid and hydrogen peroxide to a temperature between 80 ° C and 180 ° C. In one embodiment, the first source / drain structure has a larger volume than the second source / drain structure. In one embodiment, the first anisotropic etch process etches the plurality of first spacer structures more than the second anisotropic etch process etches the plurality of second spacer structures.

In one embodiment, a method includes forming a first fin extending from a substrate, forming a first gate stack over the first fin and along a sidewall of the first fin, along a sidewall of the first gate stack Forming a first spacer, the first spacer comprising a first composition of silicon oxide, forming a first spacer, forming a second spacer along a sidewall of the first spacer, and a second spacer Forming a second spacer comprising a second composition of silicon oxide, forming a third spacer along the sidewalls of the second spacer, wherein the third spacer comprises a silicon nitride, Forming, and forming a first epitaxial source / drain region within the first fin and adjacent to the third spacer. In one embodiment, the method includes forming a second fin extending from the substrate, forming a second gate stack over the second fin and along a sidewall of the second fin, along a sidewall of the second gate stack Forming a fourth spacer, the fourth spacer comprising a first composition of silicon oxide, forming a fourth spacer, forming a fifth spacer along the sidewall of the fourth spacer, and a fifth spacer Forming a fifth spacer comprising a second composition of silicon oxide, forming a sixth spacer along sidewalls of the fifth spacer, the sixth spacer comprising a silicon nitride, Forming, and forming a second epitaxial source / drain region within the second fin and adjacent to the sixth spacer, the second epitaxial source / drain region comprising 1 has a different volume and the epitaxial source / drain regions. In one embodiment, the first fin comprises silicon germanium.

The foregoing outlines features of some embodiments to enable those skilled in the art to better understand aspects of the present disclosure. Those skilled in the art will understand that the present disclosure can be readily used as a basis for designing or modifying other processes and structures to accomplish the same purpose and / or achieve the same advantages as the embodiments introduced in the present disclosure. Those skilled in the art will also appreciate that such equivalent arrangements do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

<Bookkeeping>

1. In the method,

Forming a first fin and a second fin on the substrate;

Forming a first dummy gate structure on the first fin and a second dummy gate structure on the second fin;

Depositing a first layer of silicon carbide material on the first fin, on the second fin, on the first dummy gate structure, and on the second dummy gate structure;

Injecting impurities into the first fin and into the second fin through the first layer of silicon carbide material;

Depositing a second layer of silicon oxide material over the first layer of silicon oxide material after implanting impurities;

After depositing a second layer of the silicon carbide material, performing a wet cleaning process on the first fin and the second fin;

Forming a first mask over the second fin and the second dummy gate structure;

Recessing the first fin adjacent to the first dummy gate structure to form a first recess in the first fin;

After recessing the first fin, performing the wet cleaning process on the first fin and the second fin;

Forming a second mask over the first fin and the first dummy gate structure;

Recessing the second fin adjacent to the second dummy gate structure to form a second recess in the second fin; And

Performing an epitaxy process to simultaneously form a first epitaxial source / drain region in the first recess and a second epitaxial source / drain region in the second recess simultaneously

How to include.

2. The method of claim 1, wherein an anisotropic etching process is performed on the first layer of the silicon oxide carbide material, to form a first spacer on the first dummy gate structure, and to the second layer of the silicon oxide carbide material. And performing the anisotropic etching process to form a second spacer on the second dummy gate structure.

3. The method of claim 1, wherein the first layer of silicon carbide material has a higher impurity concentration than the second layer of silicon oxide material.

4. The method of claim 1, wherein the wet cleaning process comprises using a heated mixture of sulfuric acid and hydrogen peroxide.

5. The method of claim 4, wherein the mixture of sulfuric acid and hydrogen peroxide is mixed in a molar ratio between 2: 1 and 5: 1.

6. The method of claim 4, wherein the heated mixture is between 80 ° C and 180 ° C.

7. The method of claim 1 further comprising forming a sidewall spacer on the second layer of silicon carbide material, the sidewall spacer comprising a dielectric material different from the silicon carbide material.

8. The method of claim 1, wherein the at least two first epitaxial source / drain regions are merged with each other.

9. The method of claim 1, wherein the first recess has a first depth and the second recess has a second depth different from the first depth.

10. In the method,

Patterning the substrate to form a plurality of first fins and a plurality of second fins;

Forming a plurality of first dummy gate structures on the plurality of first fins;

Forming a plurality of second dummy gate structures on the plurality of second fins;

Forming a plurality of first spacer structures on the plurality of first dummy gate structures;

Forming a plurality of second spacer structures on the plurality of second dummy gate structures, wherein the plurality of first spacer structures and the plurality of second spacer structures comprise a low-k dielectric material, Forming a second spacer structure;

Forming a first recess in the plurality of first fins,

Performing a first wet descum process; And

Forming a first recess in the plurality of first fins by performing a first anisotropic etching process

Forming the first recess comprising;

After forming the first recess in the plurality of first fins, forming a second recess in the plurality of second fins,

Performing a second wet discom process; And

Forming a second recess in the plurality of second fins by performing a second anisotropic etching process

Forming the second recess comprising; And

Epitaxially growing a first source / drain structure in the first recess and epitaxially growing a second source / drain structure in the second recess.

How to include.

11. The method of claim 10, wherein the first source / drain structure and the second source / drain structure are simultaneously formed by the same epitaxial growth process.

12. The method according to 10, wherein the first anisotropic etching process is different from the second anisotropic etching process.

13. The method of claim 10, wherein the low-k dielectric material is silicon oxide carbide.

14. The method of claim 10, wherein forming the plurality of first spacer structures comprises:

Depositing a first layer of the low-k dielectric material using a first deposition process;

Performing an implantation process on the first layer of the low-k dielectric material; And

And after performing the implantation process, depositing a second layer of the low-k dielectric material using a second deposition process.

15. The method of claim 10, wherein performing the first wet discom process comprises heating a mixture of sulfuric acid and hydrogen peroxide to a temperature between 80 ° C. and 180 ° C.

16. The method of claim 10, wherein the first source / drain structure has a larger volume than the second source / drain structure.

17. The method of claim 10, wherein the first anisotropic etching process further etches the plurality of first spacer structures than the second anisotropic etching process etches the plurality of second spacer structures.

18. In the method,

Forming a first fin extending from the substrate;

Forming a first gate stack over the first fin and along a sidewall of the first fin;

Forming a first spacer along sidewalls of the first gate stack, the first spacer comprising a first composition of silicon oxide carbide, forming the first spacer;

Forming a second spacer along a sidewall of the first spacer, wherein the second spacer comprises a second composition of silicon oxide carbide, forming the second spacer;

Forming a third spacer along sidewalls of the second spacer, wherein the third spacer comprises silicon nitride, forming the third spacer; And

Forming a first epitaxial source / drain region in the first fin and adjacent to the third spacer;

How to include.

19. The method of claim 18,

Forming a second fin extending from the substrate;

Forming a second gate stack over the second fin and along a sidewall of the second fin;

Forming a fourth spacer along sidewalls of the second gate stack, wherein the fourth spacer comprises a first composition of the silicon oxide carbide, forming the fourth spacer;

Forming a fifth spacer along sidewalls of the fourth spacer, wherein the fifth spacer comprises a second composition of the silicon oxide carbide, forming the fifth spacer;

Forming a sixth spacer along a sidewall of the fifth spacer, wherein the sixth spacer comprises silicon nitride, forming the sixth spacer; And

Forming a second epitaxial source / drain region in the second fin and adjacent to the sixth spacer, wherein the second epitaxial source / drain region comprises the first epitaxial source / drain region and Method having a different volume.

20. The method of claim 18, wherein the first fin comprises silicon germanium.

Claims (10)

In the way,
Forming a first fin and a second fin on the substrate;
Forming a first dummy gate structure on the first fin and a second dummy gate structure on the second fin;
Depositing a first layer of silicon carbide material on the first fin, on the second fin, on the first dummy gate structure, and on the second dummy gate structure;
Injecting impurities into the first fin and into the second fin through the first layer of silicon carbide material;
Depositing a second layer of silicon oxide material over the first layer of silicon oxide material after implanting impurities;
After depositing a second layer of the silicon carbide material, performing a wet cleaning process on the first fin and the second fin;
Forming a first mask over the second fin and the second dummy gate structure;
Recessing the first fin adjacent to the first dummy gate structure to form a first recess in the first fin;
After recessing the first fin, performing the wet cleaning process on the first fin and the second fin;
Forming a second mask over the first fin and the first dummy gate structure;
Recessing the second fin adjacent to the second dummy gate structure to form a second recess in the second fin; And
Performing an epitaxy process to simultaneously form a first epitaxial source / drain region in the first recess and a second epitaxial source / drain region in the second recess simultaneously
How to include. The method of claim 1, wherein an anisotropic etching process is performed on the first layer of the silicon carbide material to form a first spacer on the first dummy gate structure, and the anisotropy is performed on the second layer of the silicon oxide material. And performing an etching process to form a second spacer on the second dummy gate structure. The method of claim 1, wherein the first layer of silicon carbide material has a higher impurity concentration than the second layer of silicon oxide material. The method of claim 1, wherein the wet cleaning process comprises using a heated mixture of sulfuric acid and hydrogen peroxide. The method of claim 1, further comprising forming a sidewall spacer over the second layer of silicon carbide material, the sidewall spacer comprising a dielectric material different from the silicon carbide material. The method of claim 1, wherein at least two first epitaxial source / drain regions are merged with each other. The method of claim 1, wherein the first recess has a first depth and the second recess has a second depth different from the first depth. In the way,
Patterning the substrate to form a plurality of first fins and a plurality of second fins;
Forming a plurality of first dummy gate structures on the plurality of first fins;
Forming a plurality of second dummy gate structures on the plurality of second fins;
Forming a plurality of first spacer structures on the plurality of first dummy gate structures;
Forming a plurality of second spacer structures on the plurality of second dummy gate structures, the plurality of first spacer structures and the plurality of second spacer structures comprising a low-k dielectric material, Forming a second spacer structure;
Forming a first recess in the plurality of first fins,
Performing a first wet descum process; And
Forming a first recess in the plurality of first fins by performing a first anisotropic etching process
Forming the first recess comprising;
After forming the first recess in the plurality of first fins, forming a second recess in the plurality of second fins,
Performing a second wet discom process; And
Forming a second recess in the plurality of second fins by performing a second anisotropic etching process
Forming the second recess comprising; And
Epitaxially growing a first source / drain structure in the first recess and epitaxially growing a second source / drain structure in the second recess.
How to include. In the way,
Forming a first fin extending from the substrate;
Forming a first gate stack over the first fin and along a sidewall of the first fin;
Forming a first spacer along sidewalls of the first gate stack, the first spacer comprising a first composition of silicon oxide carbide, forming the first spacer;
Forming a second spacer along a sidewall of the first spacer, wherein the second spacer comprises a second composition of silicon oxide carbide, forming the second spacer;
Forming a third spacer along sidewalls of the second spacer, wherein the third spacer comprises silicon nitride, forming the third spacer; And
Forming a first epitaxial source / drain region in the first fin and adjacent to the third spacer;
How to include. The method of claim 9,
Forming a second fin extending from the substrate;
Forming a second gate stack over the second fin and along a sidewall of the second fin;
Forming a fourth spacer along sidewalls of the second gate stack, wherein the fourth spacer comprises a first composition of the silicon oxide carbide, forming the fourth spacer;
Forming a fifth spacer along sidewalls of the fourth spacer, wherein the fifth spacer comprises a second composition of the silicon oxide carbide, forming the fifth spacer;
Forming a sixth spacer along a sidewall of the fifth spacer, wherein the sixth spacer comprises silicon nitride, forming the sixth spacer; And
Forming a second epitaxial source / drain region in the second fin and adjacent to the sixth spacer, wherein the second epitaxial source / drain region comprises the first epitaxial source / drain region and Method having a different volume.

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