CN110970489A

CN110970489A - Semiconductor device and method of forming a semiconductor device

Info

Publication number: CN110970489A
Application number: CN201910913267.2A
Authority: CN
Inventors: 谭伟钧; 翁翊轩; 程德恩; 林咏惠; 林玮耿; 李威养; 粘志鸿
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2018-09-28
Filing date: 2019-09-25
Publication date: 2020-04-07
Anticipated expiration: 2039-09-25
Also published as: KR20200037110A; KR102284473B1; TWI725557B; TW202025261A; CN110970489B

Abstract

The present disclosure relates to semiconductor devices and methods of forming semiconductor devices. One method comprises the following steps: the method includes forming a first fin extending from a substrate, forming a first gate stack over the first fin and along sidewalls of the first fin, forming a first spacer along sidewalls of the first gate stack, the first spacer comprising a first silicon oxycarbide composition, forming a second spacer along sidewalls of the first spacer, the second spacer comprising a second silicon oxycarbide composition, forming a third spacer along sidewalls of the second spacer, the third spacer comprising silicon nitride, and forming a first epitaxial source/drain region in the first fin and adjacent to the third spacer.

Description

Semiconductor device and method of forming a semiconductor device

Technical Field

The present disclosure relates generally to semiconductor devices and methods of forming semiconductor devices.

Background

Semiconductor devices are used in various electronic applications such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by the following steps: layers of insulating or dielectric material, conductive material, and semiconductor material are sequentially deposited over a semiconductor substrate, and photolithography is used to pattern the various material layers to form circuit components and elements thereon.

The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated in a given area. However, as the minimum feature size decreases, other problems arise that should be addressed.

Disclosure of Invention

According to an embodiment of the present disclosure, there is provided a method of forming a semiconductor device, including: forming a first fin and a second fin over a substrate; forming a first dummy gate structure over the first fin and a second dummy gate structure over the second fin; depositing a first layer of silicon oxycarbide material on the first fin, on the second fin, on the first dummy gate structure, and on the second dummy gate structure; implanting impurities into the first and second fins through the first layer of silicon oxycarbide material; depositing a second layer of silicon oxycarbide material over the first layer of silicon oxycarbide material after implanting impurities; performing a wet clean process on the first fin and the second fin after depositing the second layer of silicon oxycarbide material; forming a first mask over the second fin and the second dummy gate structure; recessing the first fin adjacent to the first dummy gate structure to form a first recess in the first fin; performing the wet clean process on the first fin and the second fin after recessing the first fin; forming a second mask over the first fin and the first dummy gate structure; recessing the second fin adjacent to the second dummy gate structure to form a second recess in the second fin; and performing an epitaxial process to simultaneously form a first epitaxial source/drain region in the first recess and a second epitaxial source/drain region in the second recess.

According to another embodiment of the present disclosure, there is provided a method of forming a semiconductor device, including: patterning the substrate to form a plurality of first fins and a plurality of second fins; forming a plurality of first dummy gate structures on the plurality of first fins; forming a plurality of second dummy gate structures on the plurality of second fins; forming a plurality of first spacer structures on the plurality of first dummy gate structures; forming a plurality of second spacer structures on the plurality of second dummy gate structures, wherein the plurality of first spacer structures and the plurality of second spacer structures comprise a low-k dielectric material; forming a first groove in the plurality of first fins, comprising: performing a first wet-process deslagging process; and performing a first anisotropic etch process to form a first recess in the plurality of first fins; forming a second recess in the plurality of second fins after forming the first recess in the plurality of first fins, comprising: performing a second wet-process deslagging process; and performing a second anisotropic etch process to form a second recess in the plurality of second fins; and epitaxially growing a first source/drain structure in the first recess and a second source/drain structure in the second recess.

According to still another embodiment of the present disclosure, there is provided a method of forming a semiconductor device, including: forming a first fin extending from a substrate; forming a first gate stack over the first fin and along sidewalls of the first fin; forming first spacers along sidewalls of the first gate stack, the first spacers comprising a first silicon oxycarbide composition; forming second spacers along sidewalls of the first spacers, the second spacers comprising a second silicon oxycarbide composition; forming a third spacer along sidewalls of the second spacer, the third spacer comprising silicon nitride; and forming a first epitaxial source/drain region in the first fin and adjacent to the third spacer.

Drawings

Various aspects of the disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 illustrates an example of a FinFET in a three-dimensional view in accordance with some embodiments.

Fig. 2, 3, 4, 5, 6, 7, 8A, 8B, 9A, and 9B are cross-sectional views of intermediate stages of fabrication of a FinFET according to some embodiments.

Fig. 10 is a graph of simulation data showing a change in parasitic capacitance of a FinFET device relative to a dielectric constant of a spacer of the FinFET device, according to some embodiments.

Fig. 11A and 11B are cross-sectional views of an intermediate stage of fabrication of a FinFET according to some embodiments.

Fig. 12A and 12B are cross-sectional views of a first wet clean process in an intermediate stage of fabrication of a FinFET according to some embodiments.

Fig. 13A, 13B, 14A, and 14B are cross-sectional views of intermediate stages of fabrication of a FinFET according to some embodiments.

Fig. 15A and 15B are cross-sectional views of a second wet clean process in an intermediate stage of fabrication of a FinFET according to some embodiments.

16A, 16B, 17A, 17B, 18A, and 18B are cross-sectional views of an intermediate stage of fabrication of a FinFET according to some embodiments.

Fig. 19A-19B are cross-sectional views of forming epitaxial source/drain regions in an intermediate stage of fabrication of a FinFET, according to some embodiments.

20A, 20B, 21A, 21B, 22A, 22B, 23A, 23B, 24, 25A, 25B, 26A, and 26B are cross-sectional views of an intermediate stage of fabrication of a FinFET according to some embodiments.

Fig. 27 is a graph illustrating experimental data for variation in carbon concentration of a spacer layer of a FinFET device, according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to readily describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Various embodiments provide processes for forming gate spacers and forming epitaxial source/drain regions in a FinFET device. In some embodiments, a low-k material such as silicon oxycarbide may be used for some or all of the gate spacers. The use of silicon oxycarbide for the gate spacers may reduce parasitic capacitance within the FinFET device. Further, selectively masking the device regions and etching recesses for the epitaxial source/drain regions in each device region separately may simultaneously form different epitaxial source/drain regions in each device region using the same epitaxial formation process. Thus, epitaxial source/drain regions for different types of devices may be formed simultaneously, with characteristics for each type of device. Damage to the silicon oxycarbide layer may be reduced by cleaning and preparing the surface using a wet chemical process of heated sulfuric acid and hydrogen peroxide prior to each multiple patterning step. Thus, both the benefits of silicon oxycarbide and the benefits of multi-patterning can be realized in the process flow while reducing the likelihood of process defects.

Fig. 1 illustrates an example of a FinFET in a three-dimensional view in accordance with some embodiments. The FinFET includes a fin 52 located on a substrate 50 (e.g., a semiconductor substrate). Isolation regions 56 are disposed in substrate 50, and fins 52 protrude from between and above adjacent isolation regions 56. Although the isolation region 56 is described/illustrated as being separate from the substrate 50, as used herein, the term "substrate" may be used to refer to only a semiconductor substrate or a semiconductor substrate that includes an isolation region. Further, although fin 52 is shown as a single continuous material as substrate 50, fin 52 and/or substrate 50 may comprise a single material or multiple materials. A gate dielectric layer 92 is along the sidewalls of fin 52 and over the top surface of fin 52, and a gate electrode 94 is over gate dielectric layer 92. Source/drain regions 82 are disposed in an opposite side of fin 52 relative to gate dielectric layer 92 and gate electrode 94.

Fig. 1 further shows a reference cross section used in the following figures. The cross-section a-a is along the longitudinal axis of the gate electrode 94 and in a direction, for example, perpendicular to the direction of current flow between the source/drain regions 82 of the FinFET. Cross section B-B is perpendicular to cross section a-a and along the longitudinal axis of fin 52, and in the direction of current flow between source/drain regions 82 of, for example, a FinFET. Cross section C-C is parallel to cross section a-a and extends through the source/drain regions of the FinFET. For clarity, the subsequent figures refer to these reference cross sections.

Some embodiments discussed herein are discussed in the context of finfets formed using a gate-last process. In other embodiments, a gate first process may be used. Further, some embodiments contemplate aspects for use in planar devices (e.g., planar FETs).

Fig. 2-9B and 11A-26B are cross-sectional views of intermediate stages of fabrication of a FinFET according to some embodiments. Fig. 2-7 show the reference cross-section a-a shown in fig. 1, except for a plurality of fins/finfets. In fig. 8A-9B, 11A-11B, and 20A-26B, the figures labeled "a" are shown along reference cross-section a-a shown in fig. 1 and the figures labeled "B" are shown along similar reference cross-section B-B shown in fig. 1, except for multiple fins/finfets. In fig. 12A-19B, the figures ending with the "a" label are shown along reference cross-section C-C shown in fig. 1, and the figures ending with the "B" label are shown along similar reference cross-section B-B shown in fig. 1, except for multiple fins/finfets. Fig. 24 is shown along reference cross section B-B shown in fig. 1, except for a plurality of fins/finfets.

In fig. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, e.g., a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. Substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is disposed on a substrate, which is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of substrate 50 may include: silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof.

Substrate 50 has region 50N and region 50P. Region 50N may be used to form an N-type device, e.g., an NMOS transistor, such as an N-type FinFET. Region 50P may be used to form a P-type device, e.g., a PMOS transistor, such as a P-type FinFET. Region 50N may be physically separated from region 50P (as shown by spacer 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between region 50N and region 50P. In some embodiments, region 50N and region 50P are both used to form the same type of device, e.g., both regions are used for either an N-type device or a P-type device.

In some embodiments, more than one N-type device may be formed in region 50N, or more than one P-type device may be formed in region 50P. For example, in some embodiments, region 50P may include sub-region 50P-1 in which a first P-type device (e.g., a first design of P-type FinFET) is formed, and sub-region 50P-2 in which a second P-type device (e.g., a second design of P-type FinFET) is formed (see, e.g., the embodiments described below with reference to fig. 12A-19B.) in some embodiments, a multi-patterning process (e.g., a "2P 2E" process or other type of multi-patterning process) may be used to form different devices in different sub-regions, region 50N may similarly include sub-regions in which different N-type devices are formed, in some embodiments, region 50N or region 50P may contain only one region or may contain two or more sub-regions, a sub-region may be physically separate from other sub-regions, and any number of device features may be disposed between the sub-regions.

In fig. 3, a fin 52 is formed in a substrate 50. Fin 52 is a semiconductor strip. In some embodiments, the fin 52 may be formed in the substrate 50 by etching a trench in the substrate 50. The etch may be any acceptable etch process, such as Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), the like, or combinations thereof. The etching may be anisotropic.

The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, double-patterning or multi-patterning processes combine lithographic and self-aligned processes, allowing for the creation of patterns with, for example, smaller pitches than are obtainable using a single direct lithographic process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the fin may then be patterned using the remaining spacers.

In fig. 4, an insulating material 54 is formed over substrate 50 and between adjacent fins 52. The insulating material 54 may be an oxide, such as silicon oxide, nitride, etc., or combinations thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (fcvd) (e.g., CVD-based material deposition and post-cure in a remote plasma system to convert it to another material, such as an oxide), etc., or combinations thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material 54 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. In an embodiment, insulating material 54 is formed such that excess insulating material 54 covers fin 52. Although insulating material 54 is shown as a single layer, some embodiments may use multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along the surfaces of substrate 50 and fin 52. Thereafter, a fill material, such as discussed above, may be formed over the liner.

In fig. 5, a removal process is applied to insulative material 54 to remove excess insulative material 54 over fin 52. In some embodiments, a planarization process may be used, such as, for example, Chemical Mechanical Polishing (CMP), an etch back process, combinations thereof, and the like. The planarization process exposes the fin 52 such that the top surface of the fin 52 and the insulating material 54 is horizontal after the planarization process is complete.

In fig. 6, insulating material 54 is recessed to form Shallow Trench Isolation (STI) regions 56. Insulating material 54 is recessed so that upper portions of fins 52 in

regions

50N and 50P protrude from between adjacent STI regions 56. Further, the top surface of STI region 56 may have a flat surface, a convex surface, a concave surface (e.g., depression), or a combination thereof, as shown. The top surface of STI region 56 may be formed flat, convex, and/or concave by appropriate etching. STI regions 56 may be recessed using an acceptable etch process, e.g., an etch process that is selective to the material of insulating material 54 (e.g., etches the material of insulating material 54 at a faster rate than the material of fin 52). For example, chemical oxides that can be removed using a suitable etch process, for example using dilute hydrofluoric (dHF) acid, can be used.

The process described with respect to fig. 2-6 is only one example of how the fin 52 may be formed. In some embodiments, the fins may be formed by an epitaxial growth process. For example, a dielectric layer may be formed over the top surface of substrate 50, and a trench may be etched through the dielectric layer to expose the underlying substrate 50. A homoepitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed such that the homoepitaxial structure protrudes from the dielectric layer to form the fin. Furthermore, in some embodiments, a heteroepitaxial structure may be used for the fin 52. For example, fin 52 in fig. 5 may be recessed, and a material different from fin 52 may be epitaxially grown over recessed fin 52. In such embodiments, fin 52 comprises a recessed material, and an epitaxially grown material disposed over the recessed material. In still further embodiments, a dielectric layer may be formed over the top surface of substrate 50, and a trench may be etched through the dielectric layer. A heteroepitaxial structure may then be epitaxially grown in the trench using a different material than the substrate 50, and the dielectric layer may be recessed such that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. In some embodiments, a homoepitaxial structure or a heteroepitaxial structure is epitaxially grown. The epitaxially grown material may be doped in-situ during growth, which may avoid previous and subsequent implantations, but in-situ doping and implant doping may be used together.

Still further, it may be advantageous to epitaxially grow a medium material in region 50N (e.g., NMOS region) that is different from the material in region 50P (e.g., PMOS region). In various embodimentsThe upper portion of fin 52 may be formed of silicon germanium (Si)_xGe_1-xWhere x may be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, and the like. For example, useful materials for forming III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

Furthermore, in fig. 6, appropriate wells (not shown) may be formed in fin 52 and/or substrate 50. In some embodiments, a P-well may be formed in region 50N, and an N-well may be formed in region 50P. In some embodiments, a P-well or an N-well is formed in both region 50N and region 50P.

In embodiments with different well types, different implantation steps of region 50N and region 50P may be achieved using a photoresist or other mask (not shown). For example, a photoresist may be formed over fin 52 and STI region 56 in region 50N. The photoresist is patterned to expose a region 50P of the substrate 50, e.g., a PMOS region. The photoresist may be formed by using a spin coating technique and may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, N-type impurity implantation is performed in the region 50P, and the photoresist may be used as a mask to substantially prevent N-type impurities from being implanted into the region 50N, e.g., an NMOS region. The n-type impurity may be 10 or less¹⁸cm^-3(e.g., at about 10)¹⁷cm^-3And about 10¹⁸cm^-3In between) is implanted into the region. After implantation, the photoresist is removed, for example, by an acceptable ashing process.

After implanting region 50P, a photoresist is formed over fin 52 and STI region 56 in region 50P. The photoresist is patterned to expose regions 50N of the substrate 50, e.g., NMOS regions. The photoresist may be formed by using a spin coating technique and may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implant is performed in the region 50N, and the photoresist is photo-inducedThe resist may be used as a mask to substantially prevent P-type impurities from being implanted into the region 50P, e.g., the PMOS region. The p-type impurity may be 10 or less¹⁸cm^-3(e.g., at about 10)¹⁷cm^-3And about 10¹⁸cm^-3In between) boron, BF in the region is implanted₂And the like. After implantation, the photoresist is removed, for example, by an acceptable ashing process.

Following the implantation of the

regions

50N and 50P, an anneal may be performed to activate the implanted P-type and/or N-type impurities. In some embodiments, the growth material of the epitaxial fin may be doped in-situ during growth, which may avoid implantation, but in-situ doping and implant doping may be used together.

In fig. 7, a dummy dielectric layer 60 is formed on the fin 52. Dummy dielectric layer 60 may be, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed over the dummy dielectric layer 60, and a mask layer 64 is formed over the dummy gate layer 62. Dummy gate layer 62 may be deposited on dummy dielectric layer 60 and then planarized, for example by CMP. A mask layer 64 may be deposited over the dummy gate layer 62. The dummy gate layer 62 may be a conductive material and may be selected from the group consisting of polysilicon (polysilicon), polycrystalline silicon germanium (poly SiGe), metal nitride, metal silicide, metal oxide, and metal. In one embodiment, amorphous silicon is deposited and recrystallized to produce polysilicon. The dummy gate layer 62 may be deposited by Physical Vapor Deposition (PVD), CVD, sputter deposition, or other techniques known in the art and used to deposit conductive materials. The dummy gate layer 62 may be made of other materials having high etch selectivity from the etching of the isolation region. The mask layer 64 may comprise, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across region 50N and region 50P. In some embodiments, separate dummy gate layers may be formed in the region 50N and the region 50P, and separate mask layers may be formed in the region 50N and the region 50P. Note that dummy dielectric layer 60 is shown covering only fin 52 for illustrative purposes only. In some embodiments, the dummy dielectric layer 60 may be deposited such that the dummy dielectric layer 60 covers the STI regions 56, extending between the dummy gate layer 62 and the STI regions 56.

Fig. 8A-9B and 11A-11B illustrate various additional steps in the fabrication of an embodiment device. Fig. 8A to 9B and fig. 11A to 11B show features of any one of the region 50N and the region 50P. For example, the illustrated structure may be applied to both the region 50N and the region 50P. The differences, if any, in the structure of region 50N and region 50P are described in the text incorporated in each figure.

In fig. 8A and 8B, mask layer 64 may be patterned to form mask 74 using acceptable photolithography and etching techniques. The pattern of the mask 74 may then be transferred to the dummy gate layer 62. In some embodiments, the pattern of mask 74 may also be transferred to dummy dielectric layer 60 by acceptable etching techniques, forming dummy gate 72 over the remaining portions of dummy dielectric layer 60. In some embodiments (not separately shown), the dummy dielectric layer 60 may not be patterned. Dummy gates 72 overlie respective channel regions 58 of fins 52. The pattern of the mask 74 may be used to physically separate each dummy gate 72 from adjacent dummy gates. The dummy gates 72 may also have a length direction substantially perpendicular to a length direction of the respective epitaxial fins 52.

Further, in fig. 8A and 8B, a first spacer material 78 is formed on the exposed surfaces of the dummy gate 72, the mask 74, and/or the fin 52. The first spacer material 78 is used to form first spacers 80 (see fig. 11A-11B). In some embodiments, the first spacer material 78 may be a material such as an oxide, a nitride, a material such as silicon oxynitride, silicon oxycarbide, or the like, or combinations thereof. In some embodiments, the first spacer material 78 may be formed using a process such as thermal oxidation, CVD, PE-CVD, ALD, PVD, sputtering, and the like. In fig. 8B, a first spacer material 78 is shown extending vertically over the dummy gate 72 and mask 74, and laterally over the fin 52. In some embodiments, the first spacer material 78 may include multiple layers of one or more materials. In some embodiments, the first spacer material 78 may be formed to have a thickness between about 3nm and about 5 nm.

In some cases, the parasitic capacitance of a device (e.g., a FinFET device) may be reduced by using a material with a smaller dielectric constant (k). For example, forming the first spacers 80 using the first spacer material 78 having a smaller dielectric constant may reduce parasitic capacitance within the FinFET device, e.g., between the gate electrode 94 and the source/drain contacts 112 (see fig. 26A-B). In some embodiments, the first spacer material 78 may comprise a material having a dielectric constant of less than about k 3.9, for example, about k 3.5 or less. For example, in some embodiments, a silicon oxycarbide material may be used for the first spacer material 78. Silicon oxycarbide has a dielectric constant of about k-3.5 or less, and thus using silicon oxycarbide for the first spacer material 78 may reduce parasitic capacitance within the FinFET device. In some embodiments, silicon oxycarbide materials may be deposited using techniques such as ALD and the like. In some embodiments, the silicon oxycarbide material may be deposited using a process temperature between about 50 ℃ and about 80 ℃ and a process pressure between about 5 torr and about 10 torr. In some embodiments, the silicon oxycarbide may be formed to have between about 40 atomic% and about 46 atomic% silicon, to have between about 45 atomic% and about 50 atomic% oxygen, or to have between about 5 atomic% and about 18 atomic% carbon. In some embodiments, different regions or different layers of the first spacer material 78 may comprise different silicon oxycarbide compositions.

After forming the first gate spacer material 78, an implant of lightly doped source/drain (LDD) regions (not explicitly shown) may be performed. In embodiments having different device types, similar to the implantation discussed above in fig. 6, a mask, e.g., photoresist, may be formed over region 50N to expose region 50P, and an impurity of the appropriate type (e.g., N-type or P-type) may be implanted through first spacer material 78 into fin 52 in region 50P. The mask may then be removed. Subsequently, a mask, e.g., photoresist, may be formed over region 50P to expose the region50N and an appropriate type of impurity may be implanted into fin 52 in region 50N through first spacer material 78. The mask may then be removed. The n-type impurity may be any of the n-type impurities previously discussed above in fig. 6 or other n-type impurities, and the p-type impurity may be any of the p-type impurities previously discussed above in fig. 6 or other p-type impurities. The lightly doped source/drain region may have a thickness of about 10¹⁵cm^-3And about 10¹⁶cm^-3Impurity concentration in between. Annealing may be used to activate the implanted impurities. Since the LDD dopant implantation is performed through the first spacer material 78, portions of the first spacer material 78 (and portions of the first spacers 80) may also be doped with the implanted impurities. As such, in some embodiments, the first spacer material 78 may have a higher impurity concentration than the second spacer material 79 (see fig. 9A-9B) formed after the impurity implantation.

In fig. 9A and 9B, a second spacer material 79 is formed on the first spacer material 78. The second spacer material 79 is used to form a second spacer 81 (see fig. 11A-11B). In some embodiments, the second spacer material 79 may be a material such as an oxide, a nitride, a material such as silicon oxynitride, silicon oxycarbonitride, silicon oxycarbide, or the like, or a combination thereof. In some embodiments, second spacer material 79 may be formed using a process such as CVD, PE-CVD, ALD, PVD, sputtering, and the like. In some embodiments, the second spacer material 79 may comprise multiple layers of one or more materials. In some embodiments, the second spacer material 79 may be formed to have a thickness between about 3nm and about 5 nm. Since the second spacer material 79 is formed after the impurity implantation, the second spacer material 79 may have a lower impurity concentration than the first spacer material 78. In some embodiments, the second spacer material 79 and the second spacer 81 (not separately illustrated) are omitted.

Similar to the first spacer material 78 described above (see fig. 8B), by forming the second spacer 81 from the second spacer material 79 having a lower dielectric constant (see fig. 11B), parasitic capacitance within the device (e.g., FinFET device) may be reduced. In some embodiments, the second spacer material 79 may include silicon oxycarbide and, thus, may have a dielectric constant of less than about k 3.9, e.g., about k 3.5 or less. The silicon oxycarbide material of the second spacer material 79 may be formed in a manner similar to that previously described for forming the silicon oxycarbide of the first spacer material 78, but the second spacer material 79 may be formed differently in other embodiments. The composition of the silicon oxycarbide of the second spacer material 79 may be similar to that previously described for the silicon oxycarbide of the first spacer material 78.

In some embodiments, the first spacer material 78 of the first spacer 80 and the second spacer material 79 of the second spacer 81 may both be formed of silicon oxycarbide. The first spacer material 78 and the second spacer material 79 may have about the same silicon oxycarbide composition or have different compositions. For example, the first spacer material 78 may have a composition of between about 45 atomic% and about 48 atomic% oxygen and/or between about 12 atomic% and about 15 atomic% carbon. The second spacer material 79 may have a composition of between about 47 atomic% and about 50 atomic% oxygen and/or between about 10 atomic% and about 13 atomic% carbon. The first spacer material 78 or the second spacer material 79 may have other compositions in addition to these examples. In some cases, forming both the first spacer material 78 of the first spacer 80 and the second spacer material 79 of the second spacer 81 from silicon oxycarbide may reduce parasitic capacitance more than forming one or both of the first spacer 80 or the second spacer from a different material (e.g., a material having a higher dielectric constant).

Turning to fig. 10, a graph illustrates simulated data of the percentage change in parasitic capacitance (on the Y-axis) of a FinFET device relative to the dielectric constant (k) of the second spacer 81 (on the X-axis). The change in parasitic capacitance with respect to point 121 represents that both the first spacer material 78 of the first spacer 80 and the second spacer material 79 of the second spacer 81 have a dielectric constant of about k-5. Point 122 represents the change in capacitance due to the first spacer material 78 having a dielectric constant of about k-5 and the second spacer material 79 having a dielectric constant of about k-4. As shown, the smaller dielectric constant of the second spacer material 79 reduces the parasitic capacitance by about 2%.

Still referring to fig. 10, point 123 represents the change in capacitance due to the first spacer material 78 of the first spacer 80 having a dielectric constant of about k-5 and the second spacer material 79 of the second spacer 81 being formed of silicon oxycarbide having a dielectric constant of about k-3.5. As shown, the smaller dielectric constant of silicon oxycarbide reduces parasitic capacitance by about 3.5%. Point 124 represents the change in capacitance due to the first spacer material 78 and the second spacer material 79 both being formed of silicon oxycarbide having a dielectric constant of about 3.5. As shown, by forming the first spacer material 78 and the second spacer material 79 from silicon oxycarbide, the parasitic capacitance may be reduced by approximately 6.5%. Thus, as shown in the graph of fig. 10, forming both the first spacer material 78 of the first spacer 80 and the second spacer material 79 of the second spacer 81 from silicon oxycarbide may reduce the parasitic capacitance of devices such as FinFET devices. The graph and simulation data shown in fig. 10 are for purposes of illustration, and the dielectric constant of the first spacer material 78 or the second spacer material 79 may be different in other cases, or the capacitance change of the various materials of the first spacer material 78 or the second spacer material 79 may be different in other cases.

Turning to fig. 11A and 11B, first spacers 80, second spacers 81, and sidewall spacers 86 are formed. For example, the sidewall spacers 86 may be formed by conformally depositing an insulating material over the second spacer material 79 and then anisotropically etching the insulating material. In some embodiments, the anisotropic etching of the insulating material also etches the first spacer material 78 to form first spacers 80 and etches the second spacer material 79 to form second spacers 81. The second spacer 81 may have a lower implanted impurity concentration than the first spacer 80, as described above with respect to the second spacer material 79 and the first spacer material 78. In some embodiments, the insulating material of the sidewall spacers 86 may be a low-k dielectric material, such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), Fluorinated Silicate Glass (FSG), silicon nitride, silicon oxycarbide, silicon carbide, silicon carbonitride, the like, or combinations thereof. The material of the sidewall spacers 86 may be formed by any suitable method, such as CVD, PE-CVD, ALD, and the like. In some embodiments, the sidewall spacers 86 may have a thickness between about 3nm and about 5 nm.

Turning to fig. 12A-19B, epitaxial source/drain regions 82A-B are formed in fin 52, according to some embodiments. Fig. 12A-19B illustrate the formation of epitaxial source/drain regions 82A in sub-region 50P-1 and epitaxial source/drain regions 82B in sub-region 50P-2. Sub-regions 50P-1 and 50P-2 may be sub-regions of region 50P of substrate 50. The epitaxial source/drain regions in region 50N and in region 50P (including epitaxial source/drain regions 82A-B) may be collectively referred to herein as epitaxial source/drain regions 82. Fig. 12A, 13A, 14A, 15A, 16A, 17A, 18A and 19A are shown along a reference cross-section C-C shown in fig. 1, and fig. 12B, 13B, 14B, 15B, 16B, 17B, 18B and 19B are shown along a reference cross-section B-B shown in fig. 1. Epitaxial source/drain regions 82 are formed in the fin 52 such that each dummy gate 72 is disposed between a respective adjacent pair of epitaxial source/drain regions 82. In some embodiments, the epitaxial source/drain regions 82 may extend into the fin 52. In some embodiments, the sidewall spacers 86 are used to separate the epitaxial source/drain regions 82 from the dummy gate 72 by an appropriate lateral distance so that the epitaxial source/drain regions 82 do not short the gates of subsequently formed finfets.

Turning to fig. 12A-12B, a first wet clean process 95A is performed. The first wet clean process 95B may be a wet chemical cleaning process (e.g., a "deslag" process) that removes residues from the surface. The first wet clean process 95A may also include a surface treatment that bonds oxygen atoms to the surface of the sidewall spacers 86, which reduces outgassing of species such as nitrogen or hydrogen during subsequent process steps. In some cases, outgassing (e.g., NH)_xOutgassing) can lead to defects (sometimes referred to as "photoresist poisons") occurring during photoresist development. A first wet clean process 95A may be performed to prepare the structure for forming the mask 91A (see fig. 13A-13B).

In some casesIn an embodiment, the first wet clean process 95A may include sulfuric acid (H)₂SO₄) And hydrogen peroxide (H)₂O₂) The heated mixture of (a). The mixture may be, for example, in a ratio of about 2: 1 and about 5: 1, sulfuric acid and hydrogen peroxide in a molar ratio of between. The mixture may be heated to a temperature between about 80 ℃ and about 180 ℃. During the first wet clean process 95A, for example, the structure may be immersed in the heated mixture. Such mixtures described herein can remove residues and also reduce the likelihood of photolithography-related defects during photoresist patterning, e.g., defects due to "photoresist poisons".

Furthermore, the heated mixture of sulfuric acid and hydrogen peroxide used in the first wet cleaning process 95A may damage the first and

second spacers

80, 81 less than other cleaning techniques, such as plasma-based techniques (e.g., using a hydrogen plasma, an oxygen plasma, etc.). For example, some oxygen plasma cleaning techniques may deplete the carbon silicon oxycarbide layer, resulting in damage to the layer and thus also causing possible process problems or defects. Thus, when silicon oxycarbide materials are used, the use of the mixtures described herein can reduce lithography-related defects (e.g., "photoresist poisons") while also causing fewer damage-related defects. For example, by using the mixtures described herein for the first wet clean process 95A, both the first and

second spacers

80, 81 may be formed of silicon oxycarbide materials, reducing the overall likelihood of process problems or defects. In this way, benefits of using both cleaning processes (e.g., improved lithography) and silicon oxycarbide materials (e.g., reduced parasitic capacitance) may be realized.

Turning to fig. 13A-13B, a mask 91A is formed over sub-region 50P-2. The mask 91A may include a single layer or may be a multi-layer structure (e.g., a double-layer structure, a triple-layer structure, or have more than three layers). The mask 91A may include materials such as photoresist materials, oxide materials, nitride materials, other dielectric materials, and the like, or combinations thereof. In some embodiments, mask 91A includes a bottom anti-reflective coating (BARC). Mask 91A may be formed using one or more suitable techniques, such as spin-on techniques, CVD, PE-CVD, ALD, PVD, sputtering, the like, or combinations thereof. Mask 91A may be patterned using suitable photolithography and etching processes to expose portions of sub-regions 50P-1. For example, the mask 91A may be etched using one or more wet etching processes or anisotropic dry etching processes.

Turning to fig. 14A-14B, according to some embodiments, a recess 84A is formed in fin 52 of sub-region 50P-1. The recess 84A may be formed using, for example, an anisotropic dry etching process. In some cases, portions of the first spacers 80, the second spacers 81, or the sidewall spacers 86 may also be etched by an anisotropic dry etch process. The exemplary etching of

spacers

80, 81, and 86 shown in fig. 14A is intended to be illustrative, and in other embodiments, the anisotropic dry etch process may etch

spacers

80, 81, or 86 differently. For example, in other embodiments, the anisotropic dry etch process may etch portions of the

spacers

80, 81, and 86 by different amounts such that one or more of the

spacers

80, 81, or 86 extends higher above the STI regions 56 than another of the

spacers

80, 81, or 86. These and other variations are intended to fall within the scope of the present disclosure. In some embodiments, the process parameters of the anisotropic dry etch process may be controlled so as to etch the recesses 84A or the

spacers

80, 81, or 86 to have desired characteristics. The process parameters may include, for example, process gas mixture, voltage bias, RF power, process temperature, process pressure, other parameters, or combinations thereof. In some cases, the shape, volume, size, or other characteristics of the epitaxial source/drain regions 82A formed in the recesses 84A may be controlled by controlling the etching of the recesses 84A or

spacers

80, 81, or 86 in this manner (see fig. 18A-18B).

Turning to fig. 15A-15B, the mask 91A is removed and a second wet clean process 95B is performed. The mask 91A may be removed using a suitable process, for example, a wet chemical process or a dry process. After removing the mask 91A, a second wet cleaning process 95B is performed to remove residues and prepare a surface of a structure for forming the mask 91B (see fig. 16A to 16B). In some embodiments, the mask 91A is removed as part of performing the second wet clean process 95B. The second wet clean process 95B may be similar to the first wet clean process 95A (see fig. 12A-12B). For example, the second wet clean process 95B may use a heated mixture of sulfuric acid and hydrogen peroxide. The mixture may have a similar composition as described for the first wet clean process 95A and may be heated to a similar temperature. In other cases, the second wet clean process 95B may be a different mixture of sulfuric acid and hydrogen peroxide than that used for the first wet clean process 95A, and may be heated to a different temperature. Similar to the first wet clean process 95A, the use of a heated mixture of sulfuric acid and hydrogen peroxide may reduce damage to the silicon oxycarbide layer, e.g., embodiments in which the first spacers 80 and/or the second spacers 81 are formed from silicon oxycarbide.

Turning to fig. 16A-16B, a mask 91B is formed over the sub-region 50P-1. The mask 91B may include a single layer or may be a multi-layer structure (e.g., a double-layer structure, a triple-layer structure, or have more than three layers). The mask 91A may include materials such as photoresist materials, oxide materials, nitride materials, other dielectric materials, and the like, or combinations thereof. In some embodiments, mask 91B includes a bottom anti-reflective coating (BARC). Mask 91B may be formed using one or more suitable techniques, such as spin-on techniques, CVD, PE-CVD, ALD, PVD, sputtering, the like, or combinations thereof. Mask 91B may be patterned using suitable photolithography and etching processes to expose portions of sub-regions 50P-2. For example, one or more wet etching processes or anisotropic dry etching processes may be used to etch the mask 91B. The mask 91B may be similar to the mask 91A (see fig. 13A-13B) or different from the mask 91A.

Turning to fig. 17A-17B, according to some embodiments, a recess 84B is formed in fin 52 of sub-region 50P-2. The recess 84B may be formed using, for example, an anisotropic dry etching process. In some cases, portions of the first spacers 80, the second spacers 81, or the sidewall spacers 86 may also be etched by an anisotropic dry etch process. In some embodiments, the process parameters of the anisotropic dry etch process may be controlled so as to etch the recesses 84B or the

spacers

80, 81, or 86 to have desired characteristics. The process parameters for the etching of sub-region 50P-2 may be different from the process parameters for the etching of sub-region 50P-1. The process parameters may include, for example, process gas mixture, voltage bias, RF power, process temperature, process pressure, other parameters, or combinations thereof. In some embodiments, the process parameters may be controlled such that the grooves 84B in sub-region 50P-2 are different (e.g., have different depths, widths, shapes, etc.) than the grooves 84A in sub-region 50P-1. The process parameters may also be controlled such that the

spacers

80, 81, or 86 in sub-region 50P-2 are different (e.g., have different heights, widths, shapes, etc.) than the

spacers

80, 81, or 86 in sub-region 50P-1. These are examples, and these and other variations are intended to fall within the scope of the present disclosure. In some cases, the shape, volume, size, or other characteristics of the epitaxial source/drain regions 82B formed in the recesses 84B may be controlled by controlling the etching of the recesses 84B or

spacers

80, 81, or 86 in this manner (see fig. 18A-18B). By using separate and distinct etch processes within sub-region 50P-1 and sub-region 50P-2, epitaxial source/drain regions in each sub-region having different characteristics may be formed.

Turning to fig. 18A-18B, mask 91B is removed. The mask 91B may be removed using a suitable process, for example, a wet chemical process or a dry process. In this manner, the source/drain regions of sub-regions 50P-1 and 50P-2 may be prepared for forming epitaxial source/drain regions 82A-B (see FIGS. 19A-19B). As described in fig. 12A-18B, multiple patterning processes may be used to etch different sub-regions differently. In some embodiments, the multiple patterning process may be, for example, a "2P 2E" process as described in fig. 12A-18B, wherein a first sub-region (e.g., sub-region 50P-2) is masked while a second sub-region (e.g., sub-region 50P-1) is etched, and then the second sub-region is masked while the first sub-region is etched. In other embodiments, sub-region 50P-1 may be masked and sub-region 50P-2 etched first before masking sub-region 50P-2 and etching sub-region 50P-1. By masking and etching the appropriate sub-regions in sequence, more than two sub-regions can be etched in this manner using different etching processes. Furthermore, by using a wet cleaning process similar to wet cleaning processes 95A-B, the wet cleaning process may be performed before each masking step and the layer formed of silicon oxycarbide is less likely to be damaged.

Turning to fig. 19A-19B, epitaxial source/drain regions 82 are formed in the region 50P, according to some embodiments. In some embodiments, a pre-clean process may first be performed to remove oxide (e.g., native oxide) from the recesses 84A-B. The pre-clean process may include a wet chemical process (e.g., diluted HF), a plasma process, or a combination. Using the same epitaxial process, epitaxial source/drain regions 82A are formed in recesses 84A of sub-region 50P-1 and epitaxial source/drain regions 82B are formed in recesses 84B of sub-region 50P-2. In some embodiments, additional epitaxial source/drain regions may be formed in other sub-regions (if any) using the same epitaxial process as epitaxial source/drain regions 82A-B. The epitaxial source/drain regions 82A-B may comprise any acceptable material, for example, a material suitable for a p-type FinFET. For example, if fin 52 is silicon or SiGe, epitaxial source/drain regions 82A-B may include SiGe, SiGeB, Ge, GeSn, other materials, the like, or combinations thereof.

In some embodiments, a single epitaxial process may form different epitaxial source/drain regions in different sub-regions. The epitaxial source/drain regions may be different due to differences in the different etch processes performed in the sub-regions to form the recesses (e.g., recesses 84A-B), or differences in the spacers (e.g., spacers 80, 81, or 86) in the sub-regions. For example, as shown in FIG. 19A, the epitaxial source/drain regions 82A formed in the recesses 84A of sub-region 50P-1 merge together into a single epitaxial source/drain region 82A during epitaxy, but the epitaxial source/drain regions 82B formed in the recesses 84B of sub-region 50P-2 remain un-merged. In this manner, the epitaxial source/drain regions 82A are formed to have a larger volume than the epitaxial source/drain regions 82B.

The merged epitaxial source/drain regions 82A and the un-merged epitaxial source/drain regions 82B shown in fig. 19A-19B are intended to be illustrative examples of different epitaxial source/drain regions formed in different sub-regions using the same epitaxial process, and these and other variations are intended to fall within the scope of the present disclosure. In other embodiments, the epitaxial source/drain regions formed in different sub-regions may differ in other ways, such as height, width, shape, volume, profile, and so forth. In this manner, FinFET devices having different epitaxial source/drain regions may be formed in different sub-regions and using the same epitaxial process. For example, a logic device may be formed in a first sub-region (e.g., sub-region 50P-1) and an SRAM device may be formed in a second sub-region (e.g., sub-region 50P-2). These are examples and other types of devices are possible.

Epitaxial source/drain regions 82 in region 50N (e.g., NMOS region) may be formed by masking region 50P (e.g., PMOS region) and etching the source/drain regions of fin 52 in region 50N to form a recess in fin 52. Epitaxial source/drain regions 82 in region 50N may then be epitaxially grown in the recesses. The epitaxial source/drain regions 82 in the region 50N may be formed before or after the epitaxial source/drain regions 82 in the region 50P are formed (e.g., before or after the epitaxial source/drain regions 82A-B shown in fig. 19A-19B are formed). The epitaxial source/drain regions 82 of the region 50N may comprise any acceptable material, for example, a material suitable for an N-type FinFET. For example, if fin 52 is silicon, epitaxial source/drain regions 82 in region 50N may comprise silicon, SiC, SiCP, SiP, or the like. The epitaxial source/drain regions 82 in region 50N may have surfaces that protrude from the respective surfaces of the fin 52, may or may not be merged, or may have facets.

In some embodiments, the region 50N may include sub-regions, and a multiple patterning process to mask and etch individual sub-regions may be used prior to forming the epitaxial source/drain regions 82 in the region 50N. The multi-patterning process may be similar to the multi-patterning process performed for sub-regions 50P-1 and 50P-2 of region 50P as described in fig. 12A-18B. In this manner, different epitaxial source/drain regions may be formed in different sub-regions using the same epitaxial process, and thus different FinFET devices (e.g., SRAM devices, logic devices, etc.) may be formed in different sub-regions. In some embodiments, the multi-patterning process may include one or more wet clean processes similar to the wet clean processes 95A-B previously described. In this manner, silicon oxycarbide may be used for the first and

second spacers

80, 81 in the region 50N and is less likely to be damaged during the multiple patterning process. In some embodiments, the sidewall spacers 86 may be removed after the epitaxial source/drain regions are formed in or in sub-regions of the

regions

50N or 50P. The sidewall spacers 86 may be removed using, for example, an anisotropic dry etch.

Epitaxial source/drain regions 82 and/or fin 52 may be implanted with dopants to form source/drain regions, similar to the processes previously discussed for forming lightly doped source/drain regions, and then annealed. The impurity concentration of the source/drain region may be about 10¹⁹cm^-3And about 10²¹cm^-3In the meantime. The n-type and/or p-type impurities of the source/drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source/drain regions 82 may be doped in-situ during growth.

Turning to fig. 20A and 20B, ILD88 is deposited over region 50N and region 50P. The structure shown in fig. 20A-20B is an example structure after formation of epitaxial source/drain regions 82, and the process steps described may be applied to any of the structures, embodiments, or devices previously described. ILD88 may be formed of a dielectric or semiconductor material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (pecvd), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), Undoped Silicate Glass (USG), and the like. The semiconductor material may comprise amorphous silicon, silicon germanium (Si)_xGe_1-xWhere x may be between about 0 and 1), pure germanium, and the like. Other insulating or semiconducting materials formed by any acceptable process may be used. In some implementationsIn the example, a Contact Etch Stop Layer (CESL)87 is disposed between ILD88 and epitaxial source/drain regions 82, hardmask 74, and sidewall spacers 86. CESL 87 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, the like, or combinations thereof.

In fig. 21A and 21B, a planarization process (e.g., CMP) may be performed to make the top surface of ILD88 flush with the top surface of dummy gate 72. The planarization process may also remove the mask 74 over the dummy gate 72 and may also remove portions of the first, second, and

sidewall spacers

80, 81, 86 along the sidewalls of the mask 74. After the planarization process, the top surfaces of dummy gate 72, first spacers 80, second spacers 81, sidewall spacers, and ILD88 are horizontal. Thus, the top surface of dummy gate 72 is exposed by ILD 88.

In fig. 22A and 22B, the dummy gate 72 and the portion of the dummy dielectric layer 60 directly underlying the exposed dummy gate 72 are removed in one or more etching steps to form a recess 90. In some embodiments, dummy gate 72 is removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using one or more process gases that selectively etches the dummy gate 72 without etching the ILD88 or the gate spacers 86. Each recess 90 exposes a channel region of a respective fin 52. Each channel region 58 is disposed between an adjacent pair of epitaxial source/drain regions 82. During removal, the dummy dielectric layer 60 may act as an etch stop layer when the dummy gate 72 is etched. The dummy dielectric layer 60 may then optionally be removed after the dummy gate 72 is removed.

In fig. 23A and 23B, a gate dielectric layer 92 and a gate electrode 94 are formed for replacement gates, according to some embodiments. Fig. 24 shows a detailed view of fig. 23B, as shown. A gate dielectric layer 92 is conformally deposited in the recess 90, e.g., on the top surface and sidewalls of the fin 52 and on the sidewalls of the first spacer 80. A gate dielectric layer 92 may also be formed on the top surface of the first ILD 88. According to some embodiments, gate dielectric layer 92 comprises silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, gate dielectric layer 92 is a high-k dielectric material, and in these embodiments, gate dielectric layer 92 may have a k value greater than approximately 7.0 and may include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The formation method of the gate dielectric layer 92 may include Molecular Beam Deposition (MBD), ALD, PECVD, and the like. In embodiments in which portions of dummy gate dielectric 60 remain in recesses 90, gate dielectric layer 92 comprises the material of dummy gate dielectric 60 (e.g., silicon oxide).

Gate electrodes 94 are respectively deposited over gate dielectric layer 92 and fill the remainder of recesses 90. The gate electrode 94 may be a metal-containing material, such as TiN, TiO, TaN, TaC, Co, Ru, Al, W, combinations thereof, or multiple layers thereof. For example, although a single layer gate electrode 94 is shown in fig. 23B, the gate electrode 94 may include any number of liner layers 94A, any number of work function adjusting layers 94B, and a filler material 94C, as shown in fig. 24. After filling gate electrode 94, a planarization process, such as CMP, may be performed to remove excess portions of gate dielectric layer 92 and material of gate electrode 94, which are above the top surface of ILD 88. Thus, the remaining portions of the material of gate electrode 94 and gate dielectric layer 92 form the replacement gates of the resulting FinFET. Gate electrode 94 and gate dielectric layer 92 may be collectively referred to as a "gate stack". The gate and gate stack may extend along sidewalls of the channel region 58 of the fin 52.

The formation of gate dielectric layer 92 in region 50N and region 50P may occur simultaneously such that gate dielectric layer 92 in each region is formed of the same material, and the formation of gate electrode 94 may occur simultaneously such that gate electrode 94 in each region is formed of the same material. In some embodiments, gate dielectric layer 92 in each region may be formed by a different process such that gate dielectric layer 92 may be a different material, and/or gate electrode 94 in each region may be formed by a different process such that gate electrode 94 may be a different material. When different processes are used, various masking steps may be used to mask and expose the appropriate areas.

In fig. 25A and 25B, ILD 108 is deposited over ILD 88. In an embodiment, ILD 108 is a flowable film formed by a flowable CVD process. In some embodiments, ILD 108 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and may be deposited by any suitable method, e.g., CVD, PE-CVD, etc.

In fig. 26A and 26B,

contacts

110 and 112 are formed through ILD 108 and ILD88, according to some embodiments. In some embodiments, an annealing process may be performed to form a silicide at the interface between the epitaxial source/drain regions 82 and the contacts 112 prior to forming the contacts 112. Contact 110 is physically and electrically connected to gate electrode 94, and contact 112 is physically and electrically connected to epitaxial source/drain regions 82. 26A-

26B show contacts

110 and 112 in the same cross-section; however, in other embodiments,

contacts

110 and 112 may be disposed in different cross-sections. Furthermore, the locations of

contacts

110 and 112 in fig. 26A-26B are merely illustrative and are not intended to be limiting in any way. For example, the contacts 110 may be vertically aligned with the fins 52 as shown, or may be disposed at different locations on the gate electrode 94. Further, contact 112 may be formed before, at the same time as, or after contact 110 is formed.

Turning to fig. 27, a graph illustrates experimental data for a measurement of the presence of carbon concentration in a first spacer 80 and a second spacer 81 formed of silicon oxycarbide material. Fig. 27 shows the carbon concentration measured after the different process steps, referred to as steps A, B, C and D. In FIG. 27, points 125A-D show the carbon concentration of the first sample, points 126A-D show the carbon concentration of the second sample, and points 127A-D show the carbon concentration of the third sample. As described in more detail below, the first wet clean process 95A and the second wet clean process 95B are used to clean the first sample (points 125A-D) and the second sample (points 126A-D), but the oxygen plasma process is used to clean the third sample (points 127A-D). Process step a corresponds to a step after forming the first and

second spacers

80 and 81, and thus points 125A, 126A, and 127A show the initial carbon concentration of the sample (e.g., as shown in fig. 11A-11B).

Process step B corresponds to a step after the 2P2E multi-patterning process described in fig. 12A-18B has been performed. However, the first sample (points 125A-D) and the second sample (points 126A-D) use the first wet clean process 95A and the second wet clean process 95B previously described, while the third sample (points 127A-D) uses a separate oxygen plasma process instead of the first wet clean process 95A and the second wet clean process 95B. As shown at

points

125B and 126B, the wet cleaning processes 95A-B performed on the first and second samples reduced the carbon concentration of the first and

second spacers

80 and 81 of the first and second samples to about 50% of the initial carbon concentration (

points

125A and 126A). As shown at point 127B, the oxygen plasma process performed on the third sample reduced the carbon concentration of the first and

second spacers

80 and 81 to less than about 10% of the initial carbon concentration (point 127A). The decrease in the carbon concentration indicates an increase in the damage of the oxygen plasma process to the first and

second spacers

80 and 81. Thus, fig. 27 illustrates that the carbon concentration of the silicon oxycarbide material may be reduced less than other types of cleaning processes using the wet cleaning processes 95A-B. The data shown in fig. 27 is an illustrative example, and the carbon concentration may be reduced by a greater or lesser amount in other cases using the wet clean processes 95A-B.

Process step C corresponds to the step before performing the pre-clean process as described in fig. 19A-19B. As shown, the first sample (point 125C), the second sample (point 126C), and the third sample (point 127C) maintained approximately the same carbon concentration as at process step B. Process step D corresponds to a step prior to forming epitaxial source/drain regions 82A-B as described in fig. 19A-19B. As shown, the first sample (point 125D), the second sample (point 126D), and the third sample (point 127D) maintained approximately the same carbon concentration as at process step B and process step C. Thus, in some cases, additional processes may not further reduce the carbon concentration after performing the wet clean processes 95A-B.

Advantages may be realized by the embodiments described herein. By using a wet clean process that includes a heated mixture of sulfuric acid and hydrogen peroxide, a silicon oxycarbide material may be used as part of a FinFET device with less risk of damage to the silicon oxycarbide material. For example, a silicon oxycarbide material may be used for one, two, or more spacers formed on the sidewalls of the dummy gate during the process. Because silicon oxycarbide has a relatively low dielectric constant, the use of silicon oxycarbide (e.g., as a material for the spacers) within a FinFET device may reduce the parasitic capacitance of the FinFET device. For example, parasitic capacitance between the metal gate and the source/drain contacts may be reduced. By reducing parasitic capacitance, performance of the FinFET device may be improved, particularly at higher frequencies of operation. Additionally, using a wet clean process mixture as described herein may allow for more reliable use of silicon oxycarbide in addition to multiple patterning techniques. For example, multiple patterning may be used to form devices with different epitaxial regions using the same epitaxial step, using selective masking and different etching processes for different devices. This may reduce the overall process steps, increase process efficiency and reduce manufacturing costs, while also providing the benefits of using silicon oxycarbide.

In an embodiment, a method comprises: forming a first fin and a second fin over a substrate, forming a first dummy gate structure over the first fin and a second dummy gate structure over the second fin, depositing a first layer of silicon oxycarbide material over the first fin, over the second fin, over the first dummy gate structure, and over the second dummy gate structure, implanting impurities into the first fin and the second fin through the first layer of silicon oxycarbide material, depositing a second layer of silicon oxycarbide material over the first layer of silicon oxycarbide material after implanting the impurities, performing a wet cleaning process on the first fin and the second fin after depositing the second layer of silicon oxycarbide material, forming a first mask over the second fin and the second dummy gate structure, recessing the first fin adjacent to the first dummy gate structure to form a first recess in the first fin, performing a wet cleaning process on the first fin and the second fin after recessing the first fin, the method further includes forming a second mask over the first fin and the first dummy gate structure, recessing a second fin adjacent to the second dummy gate structure to form a second recess in the second fin, and performing an epitaxy process to simultaneously form a first epitaxial source/drain region in the first recess and a second epitaxial source/drain region in the second recess. In an embodiment, the method includes performing an anisotropic etch process on a first layer of silicon oxycarbide material to form first spacers on the first dummy gate structure and performing an anisotropic etch process on a second layer of silicon oxycarbide material to form second spacers on the second dummy gate structure. In an embodiment, the first layer of silicon oxycarbide material has a higher impurity concentration than the second layer of silicon oxycarbide material. In an embodiment, the wet cleaning process comprises using a heated mixture of sulfuric acid and hydrogen peroxide. In the examples, the mixture of sulfuric acid and hydrogen peroxide was a 2: 1 and 5: 1, are mixed in a molar ratio of between 1. In an embodiment, the heated mixture is at a temperature between 80 ℃ and 180 ℃. In an embodiment, the method includes forming a sidewall spacer over the second layer of silicon oxycarbide material, the sidewall spacer comprising a dielectric material different from the silicon oxycarbide material. In an embodiment, at least two first epitaxial source/drain regions are merged together. In an embodiment, the first groove has a first depth and the second groove has a second depth different from the first depth.

In an embodiment, a method comprises: patterning the substrate to form a plurality of first fins and a plurality of second fins, forming a plurality of first dummy gate structures on the plurality of first fins, forming a plurality of second dummy gate structures on the plurality of second fins, forming a plurality of first spacer structures on the plurality of first dummy gate structures, forming a plurality of second spacer structures on the plurality of second dummy gate structures, wherein the plurality of first spacer structures and the plurality of second spacer structures comprise a low-k dielectric material, forming first recesses in the plurality of first fins, including performing a first wet deglaze process and performing a first anisotropic etch process to form first recesses in the plurality of first fins, forming second recesses in the plurality of second fins after forming the first recesses in the plurality of first fins, including performing a second wet deglaze process, and performing a second anisotropic etch process to form second recesses in the plurality of second fins, and epitaxially growing a first source/drain structure in the first recess and a second source/drain structure in the second recess. In an embodiment, the first source/drain structure and the second source/drain structure are formed simultaneously by the same epitaxial growth process. In an embodiment, the first anisotropic etch process is different from the second anisotropic etch process. In an embodiment, the low-k dielectric material is silicon oxycarbide. In an embodiment, forming the plurality of first spacer structures comprises: the method includes depositing a first layer of low-k dielectric material using a first deposition process, performing an implant process on the first layer of low-k dielectric material, and after performing the implant process, depositing a second layer of low-k dielectric material using a second deposition process. In an embodiment, performing the first wet deslag process includes: the mixture of sulfuric acid and hydrogen peroxide is heated to a temperature between 80 ℃ and 180 ℃. In an embodiment, the first source/drain structure has a larger volume than the second source/drain structure. In an embodiment, the first anisotropic etch process etches more of the plurality of first spacer structures than the second anisotropic etch process etches the plurality of second spacer structures.

In an embodiment, a method comprises: the method includes forming a first fin extending from a substrate, forming a first gate stack over the first fin and along sidewalls of the first fin, forming a first spacer along sidewalls of the first gate stack, the first spacer comprising a first silicon oxycarbide composition, forming a second spacer along sidewalls of the first spacer, the second spacer comprising a second silicon oxycarbide composition, forming a third spacer along sidewalls of the second spacer, the third spacer comprising silicon nitride, and forming a first epitaxial source/drain region in the first fin and adjacent to the third spacer. In an embodiment, the method comprises: forming a second fin extending from the substrate, forming a second gate stack over the second fin and along sidewalls of the second fin, forming a fourth spacer along sidewalls of the second gate stack, the fourth spacer comprising a first silicon oxycarbide composition, forming a fifth spacer along sidewalls of the fourth spacer, the fifth spacer comprising a second silicon oxycarbide composition, forming a sixth spacer along sidewalls of the fifth spacer, the sixth spacer comprising silicon nitride, and forming a second epitaxial source/drain region in the second fin and adjacent to the sixth spacer, wherein the second epitaxial source/drain region has a different volume than the first epitaxial source/drain region. In an embodiment, the first fin includes silicon germanium.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Example 1 is a method of forming a semiconductor device, comprising: forming a first fin and a second fin over a substrate; forming a first dummy gate structure over the first fin and a second dummy gate structure over the second fin; depositing a first layer of silicon oxycarbide material on the first fin, on the second fin, on the first dummy gate structure, and on the second dummy gate structure; implanting impurities into the first and second fins through the first layer of silicon oxycarbide material; depositing a second layer of silicon oxycarbide material over the first layer of silicon oxycarbide material after implanting impurities; performing a wet clean process on the first fin and the second fin after depositing the second layer of silicon oxycarbide material; forming a first mask over the second fin and the second dummy gate structure; recessing the first fin adjacent to the first dummy gate structure to form a first recess in the first fin; performing the wet clean process on the first fin and the second fin after recessing the first fin; forming a second mask over the first fin and the first dummy gate structure; recessing the second fin adjacent to the second dummy gate structure to form a second recess in the second fin; and performing an epitaxial process to simultaneously form a first epitaxial source/drain region in the first recess and a second epitaxial source/drain region in the second recess.

Example 2 is the method of example 1, further comprising: an anisotropic etch process is performed on the first layer of silicon oxycarbide material to form first spacers on the first dummy gate structure, and an anisotropic etch process is performed on the second layer of silicon oxycarbide material to form second spacers on the second dummy gate structure.

Example 3 is the method of example 1, wherein the first layer of silicon oxycarbide material has a higher impurity concentration than the second layer of silicon oxycarbide material.

Example 4 is the method of example 1, wherein the wet cleaning process comprises using a heated mixture of sulfuric acid and hydrogen peroxide.

Example 5 is the method of example 4, wherein the mixture of sulfuric acid and hydrogen peroxide is a mixture of 2: 1 and 5: 1, are mixed in a molar ratio of between 1.

Example 6 is the method of example 4, wherein the heated mixture is at a temperature between 80 ℃ and 180 ℃.

Example 7 is the method of example 1, further comprising: forming a sidewall spacer over the second layer of silicon oxycarbide material, the sidewall spacer comprising a dielectric material different from the silicon oxycarbide material.

Example 8 is the method of example 1, wherein at least two first epitaxial source/drain regions are merged together.

Example 9 is the method of example 1, wherein the first groove has a first depth and the second groove has a second depth different from the first depth.

Example 10 is a method of forming a semiconductor device, comprising: patterning the substrate to form a plurality of first fins and a plurality of second fins; forming a plurality of first dummy gate structures on the plurality of first fins; forming a plurality of second dummy gate structures on the plurality of second fins; forming a plurality of first spacer structures on the plurality of first dummy gate structures; forming a plurality of second spacer structures on the plurality of second dummy gate structures, wherein the plurality of first spacer structures and the plurality of second spacer structures comprise a low-k dielectric material; forming a first groove in the plurality of first fins, comprising: performing a first wet-process deslagging process; and performing a first anisotropic etch process to form a first recess in the plurality of first fins; forming a second recess in the plurality of second fins after forming the first recess in the plurality of first fins, comprising: performing a second wet-process deslagging process; and performing a second anisotropic etch process to form a second recess in the plurality of second fins; and epitaxially growing a first source/drain structure in the first recess and a second source/drain structure in the second recess.

Example 11 is the method of example 10, wherein the first source/drain structure and the second source/drain structure are formed simultaneously by a same epitaxial growth process.

Example 12 is the method of example 10, wherein the first anisotropic etch process is different from the second anisotropic etch process.

Example 13 is the method of example 10, wherein the low-k dielectric material is silicon oxycarbide.

Example 14 is the method of example 10, wherein forming the plurality of first spacer structures comprises: depositing a first layer of low-k dielectric material using a first deposition process; performing an implantation process on the first layer of low-k dielectric material; and depositing a second layer of low-k dielectric material using a second deposition process after performing the implantation process.

Example 15 is the method of example 10, wherein performing the first wet strip process comprises: the mixture of sulfuric acid and hydrogen peroxide is heated to a temperature between 80 ℃ and 180 ℃.

Example 16 is the method of example 10, wherein the first source/drain structure has a larger volume than the second source/drain structure.

Example 17 is the method of example 10, wherein the first anisotropic etch process etches the plurality of first spacer structures more than the second anisotropic etch process etches the plurality of second spacer structures.

Example 18 is a method of forming a semiconductor device, comprising: forming a first fin extending from a substrate; forming a first gate stack over the first fin and along sidewalls of the first fin; forming first spacers along sidewalls of the first gate stack, the first spacers comprising a first silicon oxycarbide composition; forming second spacers along sidewalls of the first spacers, the second spacers comprising a second silicon oxycarbide composition; forming a third spacer along sidewalls of the second spacer, the third spacer comprising silicon nitride; and forming a first epitaxial source/drain region in the first fin and adjacent to the third spacer.

Example 19 is the method of example 18, further comprising: forming a second fin extending from the substrate; forming a second gate stack over the second fin and along sidewalls of the second fin; forming fourth spacers along sidewalls of the second gate stack, the fourth spacers comprising the first silicon oxycarbide composition; forming fifth spacers along sidewalls of the fourth spacers, the fifth spacers comprising the second silicon oxycarbide composition; forming sixth spacers along sidewalls of the fifth spacers, the sixth spacers comprising silicon nitride; and forming a second epitaxial source/drain region in the second fin and adjacent to the sixth spacer, wherein the second epitaxial source/drain region has a different volume than the first epitaxial source/drain region.

Example 20 is the method of example 18, wherein the first fin includes silicon germanium.

Claims

1. A method of forming a semiconductor device, comprising:

forming a first fin and a second fin over a substrate;

forming a first dummy gate structure over the first fin and a second dummy gate structure over the second fin;

depositing a first layer of silicon oxycarbide material on the first fin, on the second fin, on the first dummy gate structure, and on the second dummy gate structure;

implanting impurities into the first and second fins through the first layer of silicon oxycarbide material;

depositing a second layer of silicon oxycarbide material over the first layer of silicon oxycarbide material after implanting impurities;

performing a wet clean process on the first fin and the second fin after depositing the second layer of silicon oxycarbide material;

forming a first mask over the second fin and the second dummy gate structure;

recessing the first fin adjacent to the first dummy gate structure to form a first recess in the first fin;

performing the wet clean process on the first fin and the second fin after recessing the first fin;

forming a second mask over the first fin and the first dummy gate structure;

recessing the second fin adjacent to the second dummy gate structure to form a second recess in the second fin; and

performing an epitaxial process to simultaneously form a first epitaxial source/drain region in the first recess and a second epitaxial source/drain region in the second recess.

2. The method of claim 1, further comprising: an anisotropic etch process is performed on the first layer of silicon oxycarbide material to form first spacers on the first dummy gate structure, and an anisotropic etch process is performed on the second layer of silicon oxycarbide material to form second spacers on the second dummy gate structure.

3. The method of claim 1, wherein the first layer of silicon oxycarbide material has a higher impurity concentration than the second layer of silicon oxycarbide material.

4. The method of claim 1, wherein the wet cleaning process comprises using a heated mixture of sulfuric acid and hydrogen peroxide.

5. The method of claim 4, wherein the mixture of sulfuric acid and hydrogen peroxide is a 2: 1 and 5: 1, are mixed in a molar ratio of between 1.

6. The method of claim 4, wherein the heated mixture is at a temperature between 80 ℃ and 180 ℃.

7. The method of claim 1, further comprising: forming a sidewall spacer over the second layer of silicon oxycarbide material, the sidewall spacer comprising a dielectric material different from the silicon oxycarbide material.

8. The method of claim 1, wherein at least two first epitaxial source/drain regions are merged together.

9. A method of forming a semiconductor device, comprising:

patterning the substrate to form a plurality of first fins and a plurality of second fins;

forming a plurality of first dummy gate structures on the plurality of first fins;

forming a plurality of second dummy gate structures on the plurality of second fins;

forming a plurality of first spacer structures on the plurality of first dummy gate structures;

forming a plurality of second spacer structures on the plurality of second dummy gate structures, wherein the plurality of first spacer structures and the plurality of second spacer structures comprise a low-k dielectric material;

forming a first groove in the plurality of first fins, comprising:

performing a first wet-process deslagging process; and is

Performing a first anisotropic etch process to form a first recess in the plurality of first fins; forming a second recess in the plurality of second fins after forming the first recess in the plurality of first fins, comprising:

performing a second wet-process deslagging process; and is

Performing a second anisotropic etch process to form a second recess in the plurality of second fins; and

epitaxially growing a first source/drain structure in the first recess and epitaxially growing a second source/drain structure in the second recess.

10. A method of forming a semiconductor device, comprising:

forming a first fin extending from a substrate;

forming a first gate stack over the first fin and along sidewalls of the first fin;

forming first spacers along sidewalls of the first gate stack, the first spacers comprising a first silicon oxycarbide composition;

forming second spacers along sidewalls of the first spacers, the second spacers comprising a second silicon oxycarbide composition;

forming a third spacer along sidewalls of the second spacer, the third spacer comprising silicon nitride; and

a first epitaxial source/drain region is formed in the first fin and adjacent to the third spacer.