CN110676256A

CN110676256A - 3D memory device and method of manufacturing the same

Info

Publication number: CN110676256A
Application number: CN201910972636.5A
Authority: CN
Inventors: 谢柳群; 杨川; 许波; 殷姿
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2019-10-14
Filing date: 2019-10-14
Publication date: 2020-01-10
Anticipated expiration: 2039-10-14
Also published as: CN110676256B

Abstract

The application discloses a 3D memory device and a method of manufacturing the same. The 3D memory device includes: a substrate; a gate stack structure over the substrate, the gate stack structure including a plurality of gate conductors and a plurality of interlayer insulating layers that are alternately stacked; a plurality of channel pillars penetrating the gate stack structure; and a conductive channel penetrating through the gate stack structure, wherein at least a portion of a bottom surface of the conductive channel is a curved surface. At least part of the bottom surface of the conductive channel in the 3D memory device is a curved surface, so that the uniformity of the bottom surface profile of the conductive channel is improved, better electrical parameters can be realized, and the yield and the reliability of the 3D memory device are improved.

Description

3D memory device and method of manufacturing the same

Technical Field

The invention relates to the technical field of memories, in particular to a 3D memory device and a manufacturing method thereof.

Background

The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As the feature size of semiconductor manufacturing processes becomes smaller, the memory density of memory devices becomes higher. In order to further increase the memory density, a memory device of a three-dimensional structure (i.e., a 3D memory device) has been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can increase integration in multiples on a unit area of a wafer, and can reduce cost.

Existing 3D memory devices are mainly used as non-volatile flash memories. Two major non-volatile flash memory technologies employ NAND and NOR architectures, respectively. The read speed is slightly slower in the NAND memory device compared to the NOR memory device, but the write speed is fast, the erase operation is simple, and a smaller memory cell can be realized, thereby achieving a higher memory density. Therefore, the 3D memory device adopting the NAND structure is widely used.

In a 3D memory device of NAND structure, the gate conductors of the select transistors and the memory transistors are provided in a stacked structure, and the interconnection of the memory cell strings is realized using a conductive path through the stacked structure. However, the bottom surface of the conductive channel is perpendicular to the sidewall, which may adversely affect the bottom gate oxide layer and may adversely affect the subsequent ion implantation process.

Accordingly, it is desirable to further improve the 3D memory device and the method of manufacturing the same to improve the yield and reliability of the 3D memory device.

Disclosure of Invention

In view of the above problems, it is an object of the present invention to provide a 3D memory device and a method for manufacturing the same, in which at least a portion of a bottom surface of a conductive channel is curved, thereby facilitating improvement of uniformity of ion implantation.

According to a first aspect of the present invention, there is provided a 3D memory device comprising: a substrate; a gate stack structure over the substrate, the gate stack structure including a plurality of gate conductors and a plurality of interlayer insulating layers that are alternately stacked; a plurality of channel pillars penetrating the gate stack structure; and a conductive channel penetrating through the gate stack structure, wherein at least a portion of a bottom surface of the conductive channel is a curved surface.

Preferably, the bottom surface of the conductive channel is a conical surface.

Preferably, the conductive channel extends to the substrate, and a doped region is provided at a position of the substrate corresponding to a bottom surface of the conductive channel, and the doped region electrically connects the conductive channel and the substrate.

Preferably, the plurality of channel pillars are connected to a source line via the conductive channel.

Preferably, the method further comprises the following steps: CMOS circuitry in the substrate, the conductive vias providing electrical connections between the CMOS circuitry and external circuitry.

According to a second aspect of the present invention, there is provided a method of manufacturing a 3D memory device, comprising: forming a gate stack structure over a substrate, the gate stack structure including a plurality of gate conductors and a plurality of interlayer insulating layers that are alternately stacked; forming a plurality of trench pillars penetrating the insulating stack structure; and forming a conductive channel penetrating through the gate stack structure, wherein at least part of the bottom surface of the conductive channel is a curved surface.

Preferably, the method of forming the gate stack structure includes: forming an insulating stack structure over the substrate, the gate stack structure including a plurality of sacrificial layers and a plurality of interlayer insulating layers that are alternately stacked; forming a gate line gap penetrating through the insulation laminated structure; and replacing the plurality of sacrificial layers in the insulation laminated structure with a plurality of grid conductors to form a grid laminated structure, wherein the conductive channel is formed in the grid line gap, and the shape of the bottom surface of the grid line gap is matched with that of the bottom surface of the conductive channel.

Preferably, the method of forming the gate line slit includes: forming the gate line gap penetrating through the insulation laminated structure by adopting a dry etching process; and processing the bottom surface of the gate line gap by adopting a soft etching process so that at least part of the bottom surface of the gate line gap is a curved surface.

Preferably, after the forming the gate line slit, the method further includes: and carrying out ion implantation on the substrate through the bottom of the grid line gap to form a doped region.

Preferably, the method further comprises the following steps: forming a source connected to the conductive channel, the plurality of channel pillars being connected to the source via the conductive channel.

According to the 3D memory device and the manufacturing method thereof provided by the invention, at least part of the bottom surface of the conductive channel is a curved surface, so that the uniformity of the bottom surface profile of the conductive channel is improved, and therefore, better electrical parameters can be realized, for example, the electrical performance of the lightly doped drain acting on the common source can be improved. Furthermore, at least one part of the bottom surface of the gate line gap is a curved surface, so that the uniformity of ion implantation can be improved when ion implantation is carried out, and the adverse effect of the ion implantation on the bottom gate oxide layer is avoided.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1a and 1b show an equivalent circuit diagram and a structural schematic diagram, respectively, of a memory cell string of a 3D memory device.

Fig. 2 shows a perspective view of a 3D memory device.

Fig. 3a to 3h show cross-sectional views of stages of a method of manufacturing a 3D memory device according to an embodiment of the present invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.

It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.

If for the purpose of describing the situation directly on another layer, another area, the expression "directly on … …" or "on … … and adjacent to" will be used herein.

In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

The present invention may be embodied in various forms, some examples of which are described below.

Fig. 1a and 1b show a circuit diagram and a structural schematic diagram, respectively, of a memory cell string of a 3D memory device. The case where the memory cell string includes 4 memory cells is shown in this embodiment. It is to be understood that the present invention is not limited thereto, and the number of memory cells in the memory cell string may be any number, for example, 32 or 64.

As shown in fig. 1a, the memory cell string 100 has a first terminal connected to a bit line BL and a second terminal connected to a source line SL. The memory cell string 100 includes a plurality of transistors connected in series between a first terminal and a second terminal, including: a first select transistor Q1, memory transistors M1-M4, and a second select transistor Q2. The gate of the first select transistor Q1 is connected to a string select line SSL, and the gate of the second select transistor Q2 is connected to a ground select line GSL. The gates of the memory transistors M1 through M4 are connected to corresponding ones of the word lines WL1 through WL4, respectively.

As shown in fig. 1b, the first and second select transistors Q1 and Q2 of the memory cell string 100 include

gate conductors

122 and 123, respectively, and the memory transistors M1 through M4 include gate conductors 121, respectively. The

gate conductors

121, 122, and 123 correspond to a stacking order of transistors in the memory cell string 100, and adjacent gate conductors are spaced apart from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel pillar 110. Channel pillar 110 extends through the gate stack structure. In the middle portion of the channel pillar 110, a tunnel dielectric layer 112, a charge storage layer 113, and a blocking dielectric layer 114 are interposed between the gate conductor 121 and the channel layer 111, thereby forming memory transistors M1 through M4. A blocking dielectric layer 114 is sandwiched between the

gate conductors

122 and 123 and the channel layer 111 at both ends of the channel pillar 110, thereby forming a first selection transistor Q1 and a second selection transistor Q2. Only 4 memory transistors are given as an example in this embodiment, and it is understood that the present invention is not limited thereto, and the number of memory transistors may be any plural.

In this embodiment, the channel layer 111 is composed of, for example, doped polysilicon, the tunneling dielectric layer 112 and the blocking dielectric layer 114 are respectively composed of an oxide such as silicon oxide, the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals such as silicon nitride containing metal or semiconductor particles, and the

gate conductors

121, 122 and 123 are composed of a metal such as tungsten. The channel layer 111 serves to provide channel regions for controlling the selection transistor and the memory transistor, and the doping type of the channel layer 111 is the same as that of the selection transistor and the memory transistor. For example, for N-type select and memory transistors, the channel layer 111 may be N-type doped polysilicon.

In this embodiment, the core of channel pillar 110 is channel layer 111, and tunnel dielectric layer 112, charge storage layer 113, and blocking dielectric layer 114 form a gate stack structure around the core sidewalls. In an alternative embodiment, the core of channel pillar 110 is an additional insulating layer, and channel layer 111, tunneling dielectric layer 112, charge storage layer 113, and blocking dielectric layer 114 form a gate stack structure around the core.

In this embodiment, the first and second selection transistors Q1 and Q2, the memory transistors M1 to M4 use a common channel layer 111 and a blocking dielectric layer 114. In the channel pillar 110, the channel layer 111 provides source-drain regions and a channel layer of a plurality of transistors. In an alternative embodiment, the epitaxial layers and the blocking dielectric layers of the first and second selection transistors Q1 and Q2 and the epitaxial layers and the blocking dielectric layers of the memory transistors M1 to M4, respectively, may be formed in separate steps from each other.

In a write operation, the memory cell string 100 writes data to a selected one of the memory transistors M1 through M4 using FN tunneling efficiency. Taking the memory transistor M2 as an example, while the source line SL is grounded, the ground selection line GSL is biased to a voltage of about zero volts, so that the selection transistor Q2 corresponding to the ground selection line GSL is turned off, and the string selection line SSL is biased to a high voltage VDD, so that the selection transistor Q1 corresponding to the string selection line SSL is turned on. Further, BIT line BIT2 is grounded, word line WL2 is biased at the programming voltage VPG, e.g., around 20V, and the remaining word lines are biased at the low voltage VPS 1. Since only the word line voltage of the selected memory transistor M2 is higher than the tunneling voltage, electrons of the channel region of the memory transistor M2 reach the charge storage layer 113 via the tunneling dielectric layer 112, thereby converting data into charges to be stored in the charge storage layer 113 of the memory transistor M2.

In a read operation, the memory cell string 100 determines the amount of charge in the charge storage layer from the on-state of a selected one of the memory transistors M1 through M4, thereby obtaining data indicative of the amount of charge. Taking the memory transistor M2 as an example, the word line WL2 is biased at the read voltage VRD, and the remaining word lines are biased at the high voltage VPS 2. The on state of the memory transistor M2 is related to its threshold voltage, i.e., the amount of charge in the charge storage layer, so that the data value can be determined according to the on state of the memory transistor M2. The memory transistors M1, M3, and M4 are always in a conductive state, and therefore, the conductive state of the memory cell string 100 depends on the conductive state of the memory transistor M2. The control circuit judges the conductive state of the memory transistor M2 based on the electric signals detected on the bit line BL and the source line SL, thereby obtaining the data stored in the memory transistor M2.

Fig. 2 shows a perspective view of a 3D memory device. For clarity, the respective insulating layers in the 3D memory device are not shown in fig. 2.

The 3D memory device 200 shown in this embodiment includes 4 x 4 and a total of 16 memory cell strings 100, each memory cell string 100 including 4 memory cells, thereby forming a memory array of 64 memory cells in total 4 x 4. It is to be appreciated that the invention is not so limited and that the 3D memory device can include any number of memory cell strings, e.g., 1024, and that the number of memory cells in each memory cell string can be any number, e.g., 32 or 64.

In the 3D memory device, the memory cell strings respectively include the respective channel pillars 110, and the common gate conductor layers 121, 122, and 123. The gate conductor layers 121, 122, and 123 are in accordance with the stacking order of the transistors in the memory cell string 100, and adjacent gate conductor layers are spaced apart from each other by an interlayer insulating layer, thereby forming a gate stack structure 120. The interlayer insulating layer is not shown in the figure.

The internal structure of the channel pillar 110 is shown in fig. 1b and will not be described in detail. In the middle portion of the channel pillar 110, the gate conductor layer 121 forms memory transistors M1 through M4 together with the channel layer 111, the tunnel dielectric layer 112, the charge storage layer 113, and the gate dielectric layer 114 inside the channel pillar 110. At both ends of the channel pillar 110, the gate conductor layers 122 and 123 form the selection transistors Q1 and Q2 together with the channel layer 111 and the gate dielectric layer 114 inside the channel pillar 110.

The channel pillars 110 penetrate the gate stack 120 and are arranged in an Array, wherein a first end of each of the plurality of channel pillars 110 in a same column is commonly connected to a same bit line (i.e., one of the bit lines BL1 to BL 4), a second end of each of the plurality of channel pillars 110 is commonly connected to the substrate 101, and the second end of each of the plurality of channel pillars 110 forms A Common Source (ACS) connection through the substrate 101.

The gate conductor 122 of the first selection transistor Q1 is divided into different gate lines by a gate line slit (gate line slit) 161. The gate lines of the channel pillars 110 in the same row are commonly connected to the same string selection line (i.e., one of the string selection lines SSL1 through SSL 4).

The gate conductors 121 of the memory transistors M1 and M4 are integrally connected at different levels. If the gate conductors 121 of the memory transistors M1 and M4 are split into different gate lines by the gate line slit, the gate lines of the same level reach the interconnect layer 132 via respective conductive paths 131, are thereby interconnected with each other, and are then connected to the same word line (i.e., one of the word lines WL1 to WL 4) via a conductive path 133.

The gate conductors of the second select transistors Q2 are connected in one piece. If the gate conductor 123 of the second selection transistor Q2 is divided into different gate lines by the gate line slit 161, the gate lines reach the interconnection layer 132 via respective conductive paths 131 to be interconnected with each other, and then are connected to the same ground selection line GSL via the conductive path 133.

In still other embodiments, the 3D memory device 200 has a plurality of dummy channel pillars (not shown) in the non-storage region, which may be the same or different from the internal structure of the channel pillars 110 and which pass through at least a portion of the gate conductor in the gate stack structure. In the final 3D memory device, the dummy channel pillars are not connected to the bit lines, thereby providing only a mechanical support function, and are not used for forming the select transistors and the memory transistors. Therefore, the dummy channel pillar does not form an effective memory cell.

Fig. 3a to 3g show cross-sectional views of stages of a method of manufacturing a 3D memory device according to an embodiment of the present invention. The cross-sectional view is taken along line AA in fig. 2.

The method begins with a semiconductor structure in which a channel pillar 110 has been formed, as shown in figure 3 a.

A stacked structure 150 in which interlayer insulating layers 151 and sacrificial layers 152 are alternately stacked is formed on a substrate 101, and a channel column 110 penetrating the stacked structure 150 is formed. In this embodiment, the substrate 101 is, for example, a single crystal silicon substrate, the interlayer insulating layer 151 is, for example, composed of silicon oxide, and the sacrificial layer 152 is, for example, composed of silicon nitride.

Sacrificial layer 122 will be replaced with a gate conductor that is further connected to a word line, as described below. To form a conductive path from the gate conductor to the word line, the plurality of sacrificial layers 122 are, for example, patterned in a step shape, i.e., an edge portion of each sacrificial layer 122 is exposed with respect to an overlying sacrificial layer to provide an electrical connection region. After the patterning step of the plurality of sacrificial layers 122, the insulating stack structure may be covered with an insulating layer. The interlayer insulating layer 108 between the plurality of sacrificial layers 122 and the interlayer insulating layer covering the insulating stack structure are shown in fig. 3a as a whole. However, the present invention is not limited thereto, and a plurality of independent deposition steps may be employed to form the interlayer insulating layer between and over the plurality of sacrificial layers 122.

The internal structure of the channel pillar 110 is shown in fig. 1b and will not be described in detail. Referring to fig. 1b, in the middle portion of the channel pillar 110, the channel pillar 110 includes a channel layer 111, a tunneling dielectric layer 112, a charge storage layer 113, and a gate dielectric layer 114, which are sequentially stacked, and at both ends of the channel pillar 110, the channel pillar 110 includes the channel layer 111 and the gate dielectric layer 114, which are sequentially stacked.

Further, a gate line slit 161 is formed in the stacked structure 150, as shown in fig. 3 b.

In this step, for example, a photoresist mask is formed on the surface of the semiconductor structure, and then anisotropic etching, which may be dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation, is performed. For example, by controlling the etching time so that the etching stops below the surface of the substrate 101. The photoresist mask is removed after etching by dissolving or ashing in a solvent. After the anisotropic etching, the bottom of the gate line slit 161 is processed by a soft etching (softetch) process, and a flexible mask is used as a medium for pattern transfer, such as microcontact printing, transfer micro-molding, capillary micro-molding, solvent-assisted micro-molding, near-field photo-etching, soft-forming, nano-imprinting, and the like, so that at least a portion of the bottom surface of the gate line slit 161 is a curved surface.

In this embodiment, the gate line slit 161 is used not only to divide the gate conductor into a plurality of gate lines, but also to form a conductive channel of common source connection. For this, the gate line slit 161 penetrates the stacked structure 150 to reach the substrate 101.

Further, a doped region 102 is formed in the substrate 101, as shown in fig. 3 c.

In this step, an ion Implantation (IMP) is performed on the substrate 101 through the gate line slit 161 to form a doped region 102 of an N-type (using an N-type dopant, e.g., P, As) or a P-type (using a P-type dopant, e.g., B) in the substrate 101. The doped region 102 serves as a contact region for a common source connection for reducing the contact resistance between a subsequently formed conductive channel and the substrate 101. After the ion implantation, the semiconductor structure is annealed.

In this embodiment, since at least a part of the bottom surface of the gate line slit 161 is a curved surface, preferably, the bottom surface of the gate line slit 161 is a conical surface, when ion implantation is performed, the ion distribution conforms to gaussian distribution, so that the uniformity of ion implantation can be improved, and the adverse effect of ion implantation on the bottom gate oxide layer 153 can be avoided.

Further, the sacrificial layer 152 in the stacked structure 150 is removed by isotropic etching using the gate line slit 161 as an etchant channel to form a cavity 162, as shown in fig. 3 d.

The isotropic etching may employ selective wet etching or vapor etching. An etching solution is used as an etchant in wet etching, wherein the semiconductor structure is immersed in the etching solution. Etching gases are used as etchants in vapor phase etching, wherein the semiconductor structure is exposed to the etching gas. In the case where the interlayer insulating layer 151 and the sacrificial layer 152 in the stacked-layer structure 150 are composed of silicon oxide and silicon nitride, respectively, a phosphoric acid solution may be used as an etchant in wet etching, and one or more of C4F8, C4F6, CH2F2, and O2 may be used in vapor phase etching. In the etching step, the gate line slit 161 is filled with an etchant. The end portion of the sacrificial layer 152 in the stacked structure 150 is exposed to the opening of the gate line slit 161, and thus, the sacrificial layer 152 is contacted to the etchant. The etchant gradually etches the sacrificial layer 152 from the opening of the gate line slit 161 toward the inside of the stacked-layer structure 150. The etching removes the sacrificial layer 152 with respect to the interlayer insulating layer 151 in the stack structure 150 due to the selectivity of the etchant.

Preferably, after the above-described wet etching step, an additional etching step may be employed to remove an etching product (e.g., silicon oxide) attached on the interlayer insulating layer 151, so that the exposed surface of the interlayer insulating layer 151 in the cavity 162 is planarized.

Further, the metal layer 154 is filled in the gate line slit 161 and the cavity 162, as shown in fig. 3 e. The metal layer 154 is composed of tungsten, for example.

In this step, the metal layer 154 is filled in the gate line slit 161 and the cavity 162 using Atomic Layer Deposition (ALD) using the gate line slit 161 as a deposition path. For example, a precursor source used in atomic layer deposition is, for example, tungsten hexafluoride WF6, and a reducing gas is, for example, silane SiH4 or diborane B2H 6. In the step of atomic layer deposition, the deposition process is realized by obtaining tungsten material by chemical adsorption of a reaction product of tungsten hexafluoride WF6 and silane SiH 4.

Preferably, a nucleation layer (not shown) is formed on the exposed surface of the interlayer insulating layer 151 using Atomic Layer Deposition (ALD), before the metal layer 154 is formed, and the nucleation layer is composed of, for example, silicide or nitride of tungsten. The metal layer 154 is formed on the surface of the nucleation layer, the chemisorption characteristic of the precursor on the surface during atomic layer deposition can be improved, and the adhesion strength of the metal layer 154 on the interlayer insulating layer 151 can be improved.

Further, the gate line slit 161 is newly formed in the metal layer 154, as shown in fig. 3 f.

In this step, a photoresist mask is formed on the surface of the semiconductor structure, and then an etch back (etch back) is performed to re-form the gate line slit 161 in the metal layer 154, the etch back using sulfur fluoride, nitrogen and chlorine as etchants to remove the tungsten material of the gate line slit 161. Further, the gate line slit 161 not only separates the metal layer 154 into different layers to form the

gate conductors

121, 122, and 123, but also separates the gate conductor of each layer into a plurality of gate lines. On the sidewalls of the gate line slit 161, end portions of the

gate conductors

121, 122, and 123 adjacent to the gate line slit 161 are exposed.

The

gate conductors

121, 122, and 123 formed in this step are alternately stacked with the interlayer insulating layers 151, thereby forming the gate stack structure 120. In contrast to stack structure 150,

gate conductors

121, 122, and 123 in gate stack structure 120 replace sacrificial layer 152 in stack structure 150.

Further, an interlayer 155 is formed to cover the upper surface of the gate stack structure 120 and the sidewalls of the gate line slit 161, as shown in fig. 3 g. Dielectric layer 155 is, for example, silicon oxide, and dielectric layer 155 is formed using a chemical vapor deposition process.

Further, a conductive via 141 filled in the gate line slit 161 is formed, as shown in fig. 3 h. The material of the conductive channel 141 is, for example, metal tungsten or other conductive materials, and in alternative embodiments, the conductive channel 141 may be a reasonable combination of a metal material and an insulating material, and the specific structure of the conductive channel 141 is not limited in this application.

Channel pillars 110 form a common source connection via substrate 100, and conductive channel 141 provides a conductive path connecting the common source to source line SL. In this embodiment, the conductive channel 141 penetrates through the gate stack structure 120, and a first end of the conductive channel 141 is connected to the substrate 101 and contacts the doped region 102 in the substrate 101, thereby achieving connection with the substrate 101. Preferably, there are CMOS circuits in the substrate 101, with conductive vias 141 also providing electrical connections between the CMOS circuits and external circuitry.

In this embodiment, since at least a portion of the bottom surface of the gate line slit 161 is a curved surface, at least a portion of the bottom surface of the conductive via 141 is a curved surface, so as to improve the uniformity of the bottom surface profile of the conductive via 141, thereby achieving better electrical parameters, for example, improving the electrical performance of the Lightly Doped Drain (LDD) acting on the common source.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the above-described method. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.

Claims

1. A 3D memory device, comprising:

a substrate;

a gate stack structure over the substrate, the gate stack structure including a plurality of gate conductors and a plurality of interlayer insulating layers that are alternately stacked;

a plurality of channel pillars penetrating the gate stack structure; and

a conductive via extending through the gate stack structure,

wherein, at least part of the bottom surface of the conductive channel is a curved surface.

2. The 3D memory device of claim 1, wherein the bottom surface of the conductive channel is tapered.

3. The 3D memory device of claim 1, wherein the conductive via extends to the substrate with a doped region at a location of the substrate corresponding to a bottom surface of the conductive via, the doped region electrically connecting the conductive via to the substrate.

4. The 3D memory device of claim 1 or 3, wherein the plurality of channel pillars are connected to a source line via the conductive channel.

5. The 3D memory device of claim 1 or 3, further comprising: CMOS circuitry in the substrate, the conductive vias providing electrical connections between the CMOS circuitry and external circuitry.

6. A method of fabricating a 3D memory device, comprising:

forming a gate stack structure over a substrate, the gate stack structure including a plurality of gate conductors and a plurality of interlayer insulating layers that are alternately stacked;

forming a plurality of trench pillars penetrating the insulating stack structure;

forming a conductive via through the gate stack structure,

7. The method of manufacturing according to claim 6, wherein the method of forming the gate stack structure comprises:

forming an insulating stack structure over the substrate, the gate stack structure including a plurality of sacrificial layers and a plurality of interlayer insulating layers that are alternately stacked;

forming a gate line gap penetrating through the insulation laminated structure; and

replacing the plurality of sacrificial layers in the insulating stack structure with a plurality of gate conductors to form a gate stack structure,

the conductive channel is formed in the grid line gap, and the shape of the bottom surface of the grid line gap is matched with that of the bottom surface of the conductive channel.

8. The method of manufacturing according to claim 7, wherein the method of forming the gate line slit includes:

forming the gate line gap penetrating through the insulation laminated structure by adopting a dry etching process; and

and processing the bottom surface of the grid line gap by adopting a soft etching process to ensure that at least part of the bottom surface of the grid line gap is a curved surface.

9. The method of manufacturing according to claim 7, further comprising, after forming the gate line slit: and carrying out ion implantation on the substrate through the bottom surface of the grid line gap to form a doped region.

10. The manufacturing method according to claim 6, further comprising: forming a source connected to the conductive channel, the plurality of channel pillars being connected to the source via the conductive channel.