CN112530873B - Display panel, manufacturing method thereof and electronic equipment - Google Patents
Display panel, manufacturing method thereof and electronic equipment Download PDFInfo
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- CN112530873B CN112530873B CN201910880470.4A CN201910880470A CN112530873B CN 112530873 B CN112530873 B CN 112530873B CN 201910880470 A CN201910880470 A CN 201910880470A CN 112530873 B CN112530873 B CN 112530873B
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- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 8
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 8
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- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 claims description 4
- 229910002113 barium titanate Inorganic materials 0.000 claims description 4
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 claims description 4
- 241000588731 Hafnia Species 0.000 claims 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims 1
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- 229910000449 hafnium oxide Inorganic materials 0.000 description 4
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- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- Engineering & Computer Science (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The embodiment of the application provides a display panel, a manufacturing method thereof and electronic equipment, wherein the manufacturing method of the display panel comprises the steps of providing a substrate and a first dielectric layer positioned on the substrate, forming a second dielectric layer on the first dielectric layer, wherein an opening penetrating through the second dielectric layer is formed in the second dielectric layer, the relative dielectric constant of the second dielectric layer is larger than that of the first dielectric layer, and etching the first dielectric layer along the opening by taking the second dielectric layer as a mask to form a groove in the first dielectric layer. By utilizing the characteristic that the second dielectric layer has a higher etching selection ratio relative to the first dielectric layer, the process difficulty is reduced and the yield of the display panel is improved while the groove with a high depth-to-width ratio is obtained.
Description
Technical Field
The embodiment of the application relates to the technical field of display, in particular to a display panel, a manufacturing method thereof and electronic equipment.
Background
With the increasing demand for pixel density (PPI) in display technology, in order to increase the aperture ratio, the sub-pixel structure may be advanced toward the height or depth direction, and thus a trench having a high aspect ratio needs to be formed in the display panel.
In view of the above-mentioned needs, the existing manufacturing process of display panels needs to be improved.
Disclosure of Invention
The application provides a display panel, a manufacturing method thereof and electronic equipment, which solve the problem that a groove with a high depth-to-width ratio is difficult to obtain in the display panel.
In order to solve the above problems, an embodiment of the present application provides a method for manufacturing a display panel, including: providing a substrate and a first dielectric layer positioned on the substrate; forming a second dielectric layer on the first dielectric layer, wherein an opening penetrating through the second dielectric layer is formed in the second dielectric layer, and the relative dielectric constant of the second dielectric layer is larger than that of the first dielectric layer; and etching the first dielectric layer along the opening by taking the second dielectric layer as a mask, and forming a groove in the first dielectric layer.
The second dielectric layer is used as a hard mask, and the high-selection-ratio characteristic of the first dielectric layer and the second dielectric layer is etched by utilizing an etching process, so that a groove with a high depth-to-width ratio can be obtained; in addition, due to the good insulativity of the second dielectric layer, the second dielectric layer does not need to be removed after etching is finished, and the second dielectric layer is reserved to be used as a part of the display panel, so that the process steps are saved, the process difficulty is reduced, and the yield of the display panel product is improved.
In addition, the etching is dry etching; preferably, the gas used for dry etching includes fluorocarbon gas; preferably, the process parameters of the dry etching include air pressure of 6-15 mT, power of 5-10 KW, fluorocarbon gas flow of 200-500 sccm and temperature of 10-20 ℃. The anisotropic etching of the first dielectric layer is realized by adopting dry etching, and the dry etching has high selectivity ratio to the second dielectric layer and the first dielectric layer, thereby being more beneficial to obtaining the morphology with high depth-to-width ratio.
In addition, the etching selection ratio of the dry etching to the first dielectric layer and the second dielectric layer is more than or equal to 30; preferably, the etching rate of the dry etching to the first dielectric layer isThe etching rate of the dry etching to the second dielectric layer is +.>The gas with higher etching selection ratio is selected for etching, which is more beneficial to forming the trench with high depth-to-width ratio.
In addition, the groove has a preset depth; before dry etching, the ratio of the preset depth to the thickness of the second dielectric layer is smaller than or equal to the etching selection ratio. Therefore, the second dielectric layer is prevented from being etched too early in the process of forming the groove, so that the first dielectric layer is prevented from being damaged, the quality of the display panel is ensured, and the production yield of products is improved.
In addition, forming a second dielectric layer on the first dielectric layer specifically includes: forming an initial layer on the first dielectric layer; forming a pattern layer on the initial layer; etching the initial layer by using the pattern layer until the first dielectric layer is exposed, wherein the remaining initial layer is used as a second dielectric layer; preferably, the patterned layer remains after the openings are formed. The pattern layer is reserved after the opening is formed, and can play a certain masking role in the process of etching the first dielectric layer, so that the loss of the second dielectric layer can be reduced, and the trench with high depth-to-width ratio formed by etching is further improved.
Correspondingly, the embodiment of the application also provides a display panel, which comprises: a substrate and a first dielectric layer positioned on the substrate; the second dielectric layer is positioned on the first dielectric layer, an opening is formed in the second dielectric layer, the opening penetrates through the second dielectric layer, and the relative dielectric constant of the second dielectric layer is larger than that of the first dielectric layer; a trench is formed in the first dielectric layer and is communicated with the opening.
In addition, the method further comprises the steps of: a conductive layer filling the trench and the opening; preferably, the conductive layer is further located on top of the second dielectric layer, preferably further comprising: and the third dielectric layer is positioned on the second dielectric layer and the conductive layer.
In addition, the ratio of the relative dielectric constant of the second dielectric layer to the relative dielectric constant of the first dielectric layer is greater than or equal to 4, and the material of the second dielectric layer comprises any one or more of zirconium oxide, hafnium oxide, titanium oxide, lanthanum oxide, strontium titanate, barium titanate, strontium zirconate or yttrium oxide.
Correspondingly, the embodiment of the application also provides electronic equipment, which comprises any display panel.
Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages:
forming a second dielectric layer on the first dielectric layer, wherein the dry etching process has a high etching selection ratio to the second dielectric layer and the first dielectric layer, so that a groove with a high depth-to-width ratio is formed conveniently, and the PPI of the display panel is improved; in addition, the second dielectric layer has good insulating effect, and can be used as part of the film layer of the display panel, that is, the second dielectric layer does not need to be removed after the groove is formed, so that the process steps are saved, the process difficulty is reduced, and the product yield of the display panel is improved.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise.
Fig. 1 to fig. 6 are schematic structural diagrams corresponding to each step of the method for manufacturing a display panel according to an embodiment of the application.
Detailed Description
As known from the background art, in order to achieve a higher pixel density, i.e. to include more display units in the same display panel area, obtaining a higher display resolution, how to obtain a trench with a high aspect ratio in the display panel is one of the difficulties faced at present.
In order to obtain a trench with a high aspect ratio, a hard Mask (Hark Mask) technology is generally adopted, for example, in a semiconductor process, a metal compound layer such as a TiN layer is generally adopted as a hard Mask for etching a dielectric layer, and etching is performed by utilizing a high selectivity ratio of the TiN layer to the dielectric layer. However, the TiN layer is made of a conductive material, and in order to avoid unnecessary electrical connection problems, a chemical mechanical polishing (Chemical Mechanical Polishing, CMP) technique is required to remove the entire TiN layer after forming the trench.
However, this additional process step of removing the entire TiN layer not only increases the process difficulty, but also easily causes process damage to other film layers, affecting the performance of the display panel; in addition, in the technical field of display, the substrate generally has a larger area, namely, the TiN layer to be removed has a larger area, so that the difficulty of removing the TiN layer by adopting a CMP process is high, the CMP process is easy to damage the dielectric layer, and the defect rate of the display panel is increased.
In order to solve the above problems, the present application provides a method for manufacturing a display panel, in which a second dielectric layer is formed on a first dielectric layer to be etched as a hard mask, and a trench with a high aspect ratio is formed in the first dielectric layer by using a high etching selectivity ratio of the second dielectric layer to the first dielectric layer, so as to help to improve performance of the display panel, such as improving pixel density of the display panel. The high etching selection ratio can easily realize the etching of the high aspect ratio groove, and the second dielectric layer has good insulating property, the second dielectric layer is not required to be removed after the groove is formed, the manufacturing process steps are reduced, the damage of the second dielectric layer to the first dielectric layer is reduced, and therefore the manufacturing yield of the display panel is improved.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, it will be understood by those of ordinary skill in the art that in various embodiments of the present application, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, the claimed technical solution of the present application can be realized without these technical details and various changes and modifications based on the following embodiments.
Fig. 1 to fig. 6 are schematic structural diagrams corresponding to each step of the method for manufacturing a display panel according to an embodiment of the application.
Referring to fig. 1, a substrate 101 is provided, and a first dielectric layer 102 is formed on the substrate 101.
In this embodiment, the display panel is applied to the technical field of flexible display as an example.
In this embodiment, the base 101 includes a carrier 11 and a substrate 12 disposed on the carrier 11. Wherein, the carrier 11 plays a supporting role in the subsequent process steps to prevent the substrate 12 or the first dielectric layer 102 from cracking; the carrier plate 11 is typically glass.
Accordingly, the substrate 12 includes at least one flexible substrate layer, which may be polyimide in material; the substrate 12 may also include an active layer on the flexible substrate layer, which may be amorphous silicon or polysilicon in material. It will be appreciated that the substrate 12 may also include gate structures and the like required for forming the drive transistor.
The material of the first dielectric layer 102 includes silicon nitride or silicon oxide. The first dielectric layer 102 may have a single-layer structure, for example, a single-layer silicon nitride or a single-layer silicon oxide; but may also be a stacked structure such as a stack of silicon nitride and silicon oxide. In this embodiment, the first dielectric layer 102 is exemplified as a single-layer structure.
It is understood that the first dielectric layer may also be other dielectric materials, such as silicon oxynitride or silicon oxycarbonitride.
Referring to fig. 2 and 3 in combination, a second dielectric layer 103 is formed on the first dielectric layer 102, and an opening 106 penetrating the second dielectric layer 103 is formed in the second dielectric layer 103.
The second dielectric layer 103 serves as a hard mask for subsequently etching the first dielectric layer 102 to form a trench. In this embodiment, the opening 106 exposes the first dielectric layer 102, and in the subsequent etching process, the second dielectric layer 103 is used as a mask to etch the first dielectric layer 102 along the opening 106, so as to form a trench in the first dielectric layer 102.
Specifically, the process steps of forming the second dielectric layer 103 include:
referring to fig. 2, an initiation layer 104 is formed on the first dielectric layer 102; forming a pattern layer 105 on the initial layer 104; referring to fig. 3, the second dielectric layer 103 is formed by etching the initial layer 104 using the pattern layer 105. Wherein the patterned layer 105 may be a patterned photoresist layer.
In this embodiment, the second dielectric layer 103 is formed on the first dielectric layer 102 by using an atomic layer deposition process, that is, the initial layer 104 is formed by using an atomic layer deposition process. The atomic layer deposition process has the characteristics of excellent three-dimensional conformality, large-area uniformity and the like, the atomic layer deposition process is utilized to form the initial layer 104, the film thickness of the initial layer 104 can be precisely controlled, the prepared initial layer 104 has good thickness uniformity and compactness, and accordingly the thickness uniformity and compactness of the second dielectric layer 103 are improved, so that the mask effect of the second dielectric layer 103 in the follow-up process is improved.
In this embodiment, after forming the opening 106, the pattern layer 105 is removed, exposing the top surface of the second dielectric layer 103.
In the subsequent process of etching the high aspect ratio trench, the pattern layer 105 can play a masking role within a certain time to protect the second dielectric layer 103, so that the loss of the second dielectric layer 103 can be reduced, and meanwhile, the pattern layer 105 is consumed in the subsequent trench forming process, so that in the embodiment, the pattern layer 105 is reserved after the opening 106 is formed, and the process cost is saved. It should be noted that, in other embodiments, after the opening 105 is formed, the pattern layer 105 may be remained, and the remained pattern layer 105 is consumed in the subsequent etching process to form the trench.
The cross-sectional shape of the opening 106 may be a regular shape, such as a circle, square, rectangle; the cross-sectional shape of the opening 106 may be irregular; in addition, the number of the openings 106 can be set reasonably according to actual requirements.
The relative permittivity of the second dielectric layer 103 is greater than the relative permittivity of the first dielectric layer 102. When the medium is applied with an electric field, induced charges are generated to weaken the electric field, and the ratio of the original applied electric field in vacuum to the electric field in the final medium is the relative dielectric constant (Relative Permittivity). The capacitor is made of the material to be measured, the capacitance of the capacitor is a first capacitance, the capacitance of the capacitor with the same size using vacuum as a medium is a second capacitance, and the ratio of the first capacitance to the second capacitance is the relative dielectric constant value of the material to be measured. In this embodiment, the ratio of the relative dielectric constant of the second dielectric layer 103 to the relative dielectric constant of the first dielectric layer 102 is greater than or equal to 4. For example, the material of the first dielectric layer 102 is silicon oxide, the relative dielectric constant of silicon oxide is typically 3.9, or the material of the first dielectric layer 102 is silicon nitride, the relative dielectric constant of silicon nitride is typically 7.7; the material of the second dielectric layer 103 is zirconia, and the relative dielectric constant of zirconia is typically 28.
Thus, the difference between the relative dielectric constant of the high-relative dielectric constant layer 103 and the relative dielectric constant of the first dielectric layer 102 is large, so that in the subsequent etching process, the etching rate of the second dielectric layer 103 by the etching process is much greater than that of the first dielectric layer 102. Thereby ensuring the formation of trenches having a high aspect ratio. In addition, as the relative dielectric constant of the material of the second dielectric layer is larger, after the subsequent forming of the groove, the second dielectric layer is not required to be removed by adopting an additional process, and the remaining second dielectric layer is reserved as a part of the display panel, so that the problem of high mask removal difficulty is solved, and the damage to other film layers caused by the mask removal process is avoided.
In this embodiment, the ratio of the relative dielectric constant of the material of the second dielectric layer 103 to the relative dielectric constant of the first dielectric layer 102 is greater than or equal to 4; the material of the second dielectric layer 103 may be any one or any combination of zirconium oxide, hafnium oxide, titanium oxide, lanthanum oxide, strontium titanate, barium titanate, strontium zirconate, or yttrium oxide. In this embodiment, the material of the second dielectric layer 103 is zirconia.
Referring to fig. 4, the first dielectric layer 102 is etched along the opening 106 with the second dielectric layer 103 as a mask, and a trench 107 is formed in the first dielectric layer 102.
In this embodiment, the aspect ratio of the trench is greater than or equal to 1.0, for example, 1.5, 2, 4, 6, 10. Where aspect ratio refers to the ratio between the depth and width of the trench 107.
The first dielectric layer 102 is etched using a dry etching process. The etching process has a high etching selectivity to the second dielectric layer 103 and the first dielectric layer 102. Specifically, in the process of etching the first dielectric layer 102, the etching difficulty of the second dielectric layer 103 is relatively high, and the etching rate is relatively low; conversely, the first dielectric layer 102 is relatively easy to etch, and the etching rate is fast, so that the trench 107 having a high aspect ratio can be obtained.
In the process of etching to form the trench 107, before the pattern layer 105 (refer to fig. 3) is consumed, the pattern layer 105 may also function as a mask, and as the etching time passes, the pattern layer 105 is consumed, the second dielectric layer 103 will function as an actual mask. In this embodiment, the thickness of the second dielectric layer 103 can be made relatively thinner due to the masking effect of the pattern layer 105, which is beneficial to reducing the overall thickness of the display panel. It will be appreciated that in other embodiments, the second dielectric layer may begin to act as an actual mask during the early stages of the etching process when the patterned layer is removed prior to forming the trench.
In this embodiment, the gas used in the dry etching process includes fluorocarbon gas, and the fluorocarbon gas has a high etching selectivity ratio to the second dielectric layer 103 and the first dielectric layer 102, which is beneficial to improving the performance of the formed trench. The etching gas may also include a certain amount of an oxidizing gas, such as oxygen.
In order to obtain a trench 107 having a better aspect ratio, the dry etching has an etching selectivity of 30 or more, for example, 40, 50, 60, 70, 80, to the first dielectric layer 102 and the second dielectric layer 103. The ratio of the etching rates of the second dielectric layer 103 and the first dielectric layer 102 by the etching process is an etching selection ratio. In this embodiment, the etching rate of the first dielectric layer 102 by dry etching is The etching rate of the second dielectric layer 103 by dry etching is +.>For example, the etching rate of the first dielectric layer is +.>The etching rate of the second dielectric layer is +.>The etch selectivity was 64.
Wherein the fluorocarbon gas comprises C 4 F 6 、C 4 F 8 、CHF 3 、CH 2 F 2 And CH (CH) 3 F, or any combination thereof.
In this embodiment, the process parameters of the dry etching include the air pressure of 6-15 mT, for example, 7mT, 9mT, 11mT, 14mT; the power is 5-10 KW, for example 6KW, 8KW and 9KW; the fluorocarbon gas flow rate is 200 to 500sccm, for example, 250sccm, 300sccm, 350sccm, 400sccm, 450sccm; the temperature is 10 to 20℃and is, for example, 12℃and 14℃and 17℃and 18℃and 19 ℃.
In addition, the trench 107 has a preset depth, and the ratio of the preset depth to the thickness of the second dielectric layer 103 is less than or equal to the etching selectivity before performing the dry etching, so that the second dielectric layer can be prevented from being consumed prematurely. That is, the thickness range of the second dielectric layer 103 before etching the first dielectric layer 103 may be determined according to the preset depth of the trench 107 and the etching selection ratio, so as to ensure that the second dielectric layer 103 can effectively function as a mask.
After the trench 107 is formed, the second dielectric layer 103 does not need to be removed, so that the second dielectric layer 103 is used as a part of the display panel, the problem that a mask used for etching the trench 107 is difficult to remove is solved, and the method is beneficial to improving the yield of the display panel while saving process steps and reducing process difficulty.
Referring to fig. 5, a conductive layer 108 is formed within the trench 107 (refer to fig. 4) and the opening 106 (refer to fig. 4), and the conductive layer 108 fills the trench 107 and the opening 106.
The conductive layer 108 may be a metal or a metal oxide. In this embodiment, the top of the conductive layer 108 is flush with the top of the second dielectric layer 103.
In other embodiments, the conductive layer top may also be higher than the second dielectric layer top, e.g., the conductive layer may also be on top of the second dielectric layer.
Referring to fig. 6, after the conductive layer 108 is formed, a third dielectric layer 109 is formed on the second dielectric layer 103 and on the conductive layer 108.
The third dielectric layer 109 covers the second dielectric layer 103 and the conductive layer 108.
In this embodiment, the conductive layer 108 is formed in the trench 107 (refer to fig. 4) as an example, and in other embodiments, other auxiliary components, such as a microphone or a camera, may be placed in the trench instead of the process step of forming the conductive layer.
It should be further noted that the subsequent steps may further include: the carrier plate 11 in the base 101 is removed.
In the method for manufacturing the display panel provided in this embodiment, the second dielectric layer 103 is formed on the first dielectric layer 102 as a hard mask for etching, and the etching process is used to form the trench 107 with a high aspect ratio by using the etching process to have a high etching selectivity ratio for the second dielectric layer 103 and the first dielectric layer 102. In the subsequent process, the second dielectric layer has good insulativity, does not need to be removed, can be reserved as a part of the display panel, avoids the damage of the first dielectric layer 103 caused by removing the hard mask, saves the process steps, reduces the manufacturing cost of the display panel, and improves the yield of the display panel.
Accordingly, an embodiment of the present application provides a display panel including: a substrate and a first dielectric layer positioned on the substrate; the second dielectric layer is positioned on the first dielectric layer; the second dielectric layer is provided with an opening, the opening penetrates through the second dielectric layer, and the relative dielectric constant of the second dielectric layer is larger than that of the first dielectric layer; a trench is formed in the first dielectric layer and is communicated with the opening. The display panel according to the embodiment of the present application will be described in detail with reference to the accompanying drawings.
Referring to fig. 6, in the present embodiment, a display panel includes: the substrate 101, the first dielectric layer 102 that is located on the substrate 101, and the second dielectric layer 103 that is located on the first dielectric layer 102, there is an opening (not labeled) on the second dielectric layer 103, the relative dielectric constant of the second dielectric layer is greater than the relative dielectric constant of the first dielectric layer, there is a slot (not labeled) in the first dielectric layer 102, and the slot is linked with the opening.
The display panel provided in this embodiment will be described in detail below with reference to the accompanying drawings.
The substrate 101 is another functional layer, such as a water-oxygen barrier layer, a barrier layer, or an active layer. The substrate 101 may be a single layer or a stack of multiple functional layers, for example, the substrate 101 may be a single active layer or a stack of a polyimide layer, a silicon oxide barrier layer, a polyimide layer, and an active layer in this order.
The first dielectric layer 102 is one or a combination of silicon nitride, silicon oxynitride, silicon carbonitride or silicon oxide.
Specifically, the first dielectric layer 102 may be a single layer of silicon nitride, or a single layer of silicon oxide, or a stack of silicon nitride and silicon oxide.
It is understood that the first dielectric layer may also be other dielectric materials, such as silicon oxynitride or silicon oxycarbonitride.
The relative permittivity of the second dielectric layer 103 is greater than the relative permittivity of the first dielectric layer 102. In this embodiment, the ratio of the relative dielectric constant of the second dielectric layer 103 to the relative dielectric constant of the first dielectric layer 102 is greater than or equal to 4. For example, the material of the first dielectric layer 102 may be silicon oxide or silicon nitride, and the material of the second dielectric layer 103 may be zirconium oxide.
The material of the second dielectric layer 103 may be any one or any combination of zirconia, hafnium oxide, titanium oxide, lanthanum oxide, strontium titanate, barium titanate, strontium zirconate, or yttrium oxide, for example, the second dielectric layer is a single layer of zirconia, or a stack of zirconia and hafnium oxide.
The cross-sectional shape of the openings and trenches may be regular, such as circular, square, rectangular; the cross-sectional shape of the opening may be an irregular shape; in addition, the number of the openings and the grooves can be reasonably set according to actual requirements.
In this embodiment, the preset aspect ratio of the trench is greater than or equal to 1.0. Therefore, the display panel has high aperture ratio, thereby being beneficial to improving the pixel density of the display panel and improving the display effect of the display panel.
Note that the trench 107 and the opening 106 may further have a conductive layer 108 therein, and the conductive layer 108 may fill the trench and the opening. In addition, an auxiliary component, such as a microphone or a camera, can be placed in the groove.
In other embodiments, the conductive layer may also be located on top of the second dielectric layer.
It should be further noted that, in other embodiments, the display panel may further include: a third dielectric layer 109 over the second dielectric layer 103 and the conductive layer 108.
The display panel provided by the embodiment has the advantages that the grooves have high depth-to-width ratio, so that the display panel has larger opening ratio, the corresponding display panel has high pixel density, and the display effect with higher resolution can be obtained. In addition, the second dielectric layer 103 is used as a part of the display panel, so that the process step of removing the second dielectric layer is omitted in the manufacturing process of the display panel, thereby having lower manufacturing cost and higher yield of the display panel.
It should be noted that, the display panel provided in this embodiment may be manufactured by the above-mentioned manufacturing method of the display panel.
Accordingly, an embodiment of the present application provides an electronic device, including the display panel described above. The electronic device may be any electronic device that needs a display function, such as a mobile phone, a tablet computer, and a display.
The electronic equipment provided by the embodiment of the application has high pixel density, is suitable for displaying high-resolution images and video files, and provides a real and fine display effect.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of carrying out the application and that various changes in form and details may be made therein without departing from the spirit and scope of the application. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the application, and the scope of the application is therefore intended to be limited only by the appended claims.
Claims (30)
1. A method of manufacturing a display panel, comprising:
providing a substrate and a first dielectric layer positioned on the substrate;
forming a second dielectric layer on the first dielectric layer, wherein an opening penetrating through the second dielectric layer is formed in the second dielectric layer, the relative dielectric constant of the second dielectric layer is larger than that of the first dielectric layer, and the second dielectric layer has an insulating characteristic;
etching the first dielectric layer along the opening by taking the second dielectric layer as a mask to form a groove in the first dielectric layer;
the depth-to-width ratio of the groove is larger than or equal to 1.0 so as to improve the pixel density of the display panel;
wherein, the second dielectric layer does not need to be removed after the trench is formed.
2. The method of manufacturing a display panel according to claim 1, wherein the etching is dry etching.
3. The method of manufacturing a display panel according to claim 2, wherein the gas used for the dry etching includes fluorocarbon gas.
4. A method of manufacturing a display panel according to claim 3, wherein the process parameters of the dry etching include: the air pressure is 6-15 mT, the power is 5-10 KW, the fluorocarbon gas flow is 200-500 sccm, and the temperature is 10-20 ℃.
5. The method according to claim 2, wherein an etching selectivity of the dry etching to the first dielectric layer and the second dielectric layer is 30 or more.
6. The method according to claim 5, wherein the etching rate of the first dielectric layer by the dry etching is 1500-4000 a/min; and the etching rate of the dry etching to the second dielectric layer is 50-70A/min.
7. The method of manufacturing a display panel according to claim 6, wherein the trench has a predetermined depth; and before the dry etching, the ratio of the preset depth to the thickness of the second dielectric layer is smaller than or equal to the etching selection ratio.
8. The method for manufacturing a display panel according to claim 1, wherein forming a second dielectric layer on the first dielectric layer specifically comprises: forming an initial layer on the first dielectric layer; forming a pattern layer on the initial layer; and etching the initial layer by using the pattern layer until the first dielectric layer is exposed, and taking the rest of the initial layer as the second dielectric layer.
9. The method of manufacturing a display panel according to claim 8, wherein the pattern layer remains after the opening is formed.
10. The method of manufacturing a display panel according to claim 1, further comprising, after forming the trench: and forming a conductive layer in the groove and the opening, wherein the conductive layer fills the groove and the opening.
11. The method of claim 10, wherein the conductive layer is further formed on top of the second dielectric layer.
12. The method of manufacturing a display panel according to claim 11, further comprising, after forming the conductive layer: and forming a third dielectric layer on the second dielectric layer and the conductive layer.
13. The method of claim 1, wherein the trench has an aspect ratio equal to 1.5.
14. The method of claim 1, wherein the trench has an aspect ratio equal to 2.
15. The method of claim 1, wherein the trench has an aspect ratio equal to 4.
16. The method of claim 1, wherein the trench has an aspect ratio equal to 6.
17. The method of claim 1, wherein the trench has an aspect ratio equal to 10.
18. A display panel, comprising:
a substrate and a first dielectric layer positioned on the substrate;
the second dielectric layer is positioned on the first dielectric layer, an opening is formed in the second dielectric layer, the opening penetrates through the second dielectric layer, the relative dielectric constant of the second dielectric layer is larger than that of the first dielectric layer, and the second dielectric layer has an insulating characteristic;
the first dielectric layer is internally provided with a groove which is communicated with the opening; the second dielectric layer is used as a hard mask for etching the first dielectric layer to form the groove;
the depth-to-width ratio of the groove is greater than or equal to 1.0 so as to improve the pixel density of the display panel.
19. The display panel of claim 18, further comprising: and the conductive layer fills the groove and the opening.
20. The display panel of claim 19, wherein the conductive layer is further on top of the second dielectric layer.
21. The display panel of claim 20, further comprising: and the third dielectric layer is positioned on the second dielectric layer and the conductive layer.
22. The display panel of claim 18, wherein a ratio of a relative permittivity of the second dielectric layer to a relative permittivity of the first dielectric layer is greater than or equal to 4.
23. A display panel according to claim 22, wherein the material of the second dielectric layer comprises any one or more of zirconia, hafnia, titania, lanthana, strontium titanate, barium titanate, strontium zirconate, or yttria.
24. The display panel of claim 18, wherein the trench has an aspect ratio equal to 1.5.
25. The display panel of claim 18, wherein the trench has an aspect ratio equal to 2.
26. The display panel of claim 18, wherein the trench has an aspect ratio equal to 4.
27. The display panel of claim 18, wherein the trench has an aspect ratio equal to 6.
28. The display panel of claim 18, wherein the trench has an aspect ratio equal to 10.
29. The display panel of claim 18, wherein an auxiliary component is disposed in the channel, the auxiliary component being a microphone or a camera.
30. An electronic device comprising a display panel as claimed in any one of claims 18-29.
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