TWI544543B - A manufacturing method of a semiconductor device, and a computer recording medium - Google Patents
A manufacturing method of a semiconductor device, and a computer recording medium Download PDFInfo
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- TWI544543B TWI544543B TW101106866A TW101106866A TWI544543B TW I544543 B TWI544543 B TW I544543B TW 101106866 A TW101106866 A TW 101106866A TW 101106866 A TW101106866 A TW 101106866A TW I544543 B TWI544543 B TW I544543B
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- 239000004065 semiconductor Substances 0.000 title claims description 45
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000007789 gas Substances 0.000 claims description 73
- 238000000034 method Methods 0.000 claims description 65
- 238000012545 processing Methods 0.000 claims description 64
- 230000008569 process Effects 0.000 claims description 63
- 229920002120 photoresistant polymer Polymers 0.000 claims description 53
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 23
- 229920005591 polysilicon Polymers 0.000 claims description 23
- 238000001020 plasma etching Methods 0.000 claims description 15
- 230000006870 function Effects 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 5
- 229910052732 germanium Inorganic materials 0.000 claims description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 5
- 239000001307 helium Substances 0.000 claims description 5
- 229910052734 helium Inorganic materials 0.000 claims description 5
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 5
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 5
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 230000007246 mechanism Effects 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- 238000009966 trimming Methods 0.000 description 25
- 239000010410 layer Substances 0.000 description 14
- 230000004048 modification Effects 0.000 description 12
- 238000012986 modification Methods 0.000 description 12
- 238000005530 etching Methods 0.000 description 9
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 description 5
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000010030 laminating Methods 0.000 description 4
- 238000002407 reforming Methods 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000003507 refrigerant Substances 0.000 description 2
- 239000013049 sediment Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910003902 SiCl 4 Inorganic materials 0.000 description 1
- VQYPKWOGIPDGPN-UHFFFAOYSA-N [C].[Ta] Chemical compound [C].[Ta] VQYPKWOGIPDGPN-UHFFFAOYSA-N 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910000420 cerium oxide Inorganic materials 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 230000003750 conditioning effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000005001 laminate film Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
本發明係關於一種半導體裝置的製造方法及電腦記錄媒體。 The present invention relates to a method of fabricating a semiconductor device and a computer recording medium.
以往於半導體裝置之製程中，係使得電漿作用於半導體晶圓等基板來施行蝕刻、成膜等處理以進行電漿處理。如此之半導體裝置之製程，例如在NAND型快閃記憶體之製程中，已知有對於由介電係數不同之2種膜(例如絕緣膜與導電膜)所交互積層而得之多層膜進行電漿蝕刻與罩體之修整(trimming)，來形成階梯狀構造(例如參見專利文獻1)。 Conventionally, in a process of a semiconductor device, plasma is applied to a substrate such as a semiconductor wafer to perform etching, film formation, or the like to perform plasma processing. In the process of such a semiconductor device, for example, in a process of a NAND-type flash memory, it is known to electrically charge a multilayer film obtained by alternately laminating two kinds of films having different dielectric coefficients (for example, an insulating film and a conductive film). The slurry etching and trimming of the cover are performed to form a stepped structure (see, for example, Patent Document 1).
專利文獻1 日本特開2009-170661號公報 Patent Document 1 Japanese Patent Laid-Open Publication No. 2009-170661
如上述般，從介電係數不同的2種膜(例如絕緣膜與導電膜)所交互積層而得之多層膜來形成階梯狀構造之半導體裝置之製程中，存在有製程數變多造成製造效率惡化、且因為沉積物的影響等而難以形成多段良好形狀的階梯狀構造的問題。 As described above, in the process of forming a semiconductor device having a stepped structure from a multilayer film in which two types of films having different dielectric coefficients (for example, an insulating film and a conductive film) are alternately laminated, there are cases in which the number of processes is increased to cause manufacturing efficiency. It is difficult to form a multi-staged stepped structure due to the influence of deposits and the like.
本發明係因應於上述以往之情事所得者，其目的在於提供一種可高效率形成多段良好形狀之階梯狀構 造的半導體裝置的製造方法及電腦記錄媒體。 The present invention has been made in view of the above-mentioned conventional circumstances, and an object thereof is to provide a stepped structure capable of forming a plurality of good shapes with high efficiency. A method of manufacturing a semiconductor device and a computer recording medium.
本發明之半導體裝置的製造方法之一樣態係一種半導體裝置的製造方法，係對於包括由具有第1介電係數的第1膜與具有不同於該第1介電係數之第2介電係數的第2膜所交互積層而得之多層膜、以及位於該多層膜上層而發揮蝕刻光罩功能的光阻層之基板進行蝕刻，來形成階梯狀構造；其特徵在於具有下述製程：第1製程，係以該光阻層為光罩來對該第1膜進行電漿蝕刻；第2製程，係使得該光阻層暴露於含氫電漿中；第3製程，係對該光阻層進行修整；以及第4製程，係以藉由該第3製程經過修整之光阻層以及於該第1製程經過電漿蝕刻後之該第1膜為光罩來蝕刻該第2膜；並藉由反覆進行該第1製程至該第4製程以使得該多層膜成為階梯狀構造。 The manufacturing method of the semiconductor device of the present invention is a method of manufacturing a semiconductor device including a first film having a first dielectric constant and a second dielectric constant different from the first dielectric constant. The multilayer film obtained by alternately laminating the second film and the substrate of the photoresist layer which functions as an etching mask function on the upper layer of the multilayer film are etched to form a stepped structure, and are characterized by having the following process: the first process The first film is plasma-etched with the photoresist layer as a mask; the second process is such that the photoresist layer is exposed to the hydrogen-containing plasma; and the third process is performed for the photoresist layer. And the fourth process, wherein the second film is etched by using the photoresist layer that has been trimmed by the third process and the first film that has been plasma-etched in the first process as a photomask; The first process to the fourth process are repeated to make the multilayer film have a stepped structure.
依據本發明，可提供一種可高效率形成多段良好形狀之階梯狀構造的半導體裝置的製造方法及電腦記錄媒體。 According to the present invention, it is possible to provide a method of manufacturing a semiconductor device and a computer recording medium which can form a stepped structure having a plurality of stages of good shape with high efficiency.
以下，針對本發明之實施形態參見圖式來說明。圖1係顯示實施形態之半導體裝置的製造方法所使用之電漿處理裝置之構成。電漿處理係具有以氣密構成而在電性上呈接地電位之處理室1。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. Fig. 1 is a view showing the configuration of a plasma processing apparatus used in a method of manufacturing a semiconductor device according to an embodiment. The plasma processing system has a processing chamber 1 which is electrically sealed and electrically grounded.
此處理室1係呈圓筒狀，例如由表面形成有陽極氧化皮膜之鋁等所構成。於處理室1內設有載置台2， 將做為被處理基板之半導體晶圓W加以大致水平載置。此載置台2係兼做為下部電極，由例如鋁等導電性材料所構成，經由絕緣板3而支撐於導體之支撐台4。此外，於載置台2上之外周部分以包圍半導體晶圓W之周圍的方式設有形成為環狀之聚焦環5。 The processing chamber 1 has a cylindrical shape and is made of, for example, aluminum or the like having an anodized film formed on its surface. a mounting table 2 is disposed in the processing chamber 1 The semiconductor wafer W as a substrate to be processed is placed substantially horizontally. The mounting table 2 also serves as a lower electrode and is made of a conductive material such as aluminum, and is supported by the support base 4 of the conductor via the insulating plate 3. Further, a focus ring 5 formed in a ring shape is provided on the outer peripheral portion of the mounting table 2 so as to surround the periphery of the semiconductor wafer W.
載置台2經由第1匹配箱11a而連接第1高頻電源10a，且經由第2匹配箱11b而連接第2高頻電源10b。從第1高頻電源10a對載置台2供給既定頻率(例如100MHz)之高頻電力。另一方面，從第2高頻電源10b對載置台2供給比第1高頻電源10a來得低之既定頻率(例如13.56MHz)之高頻電力。 The mounting table 2 is connected to the first high-frequency power source 10a via the first matching box 11a, and is connected to the second high-frequency power source 10b via the second matching box 11b. The high frequency power of a predetermined frequency (for example, 100 MHz) is supplied to the mounting table 2 from the first high frequency power supply 10a. On the other hand, the second high-frequency power source 10b supplies high-frequency power of a predetermined frequency (for example, 13.56 MHz) lower than that of the first high-frequency power source 10a to the mounting table 2.
另一方面，對向於載置台2在上方使得淋灑頭16和載置台2呈平行對向來設置，此淋灑頭16處於接地電位。從而，此等淋灑頭16與載置台2係以一對之對向電極(上部電極與下部電極)來發揮功能。 On the other hand, the opposing head 2 is placed above the shower head 16 and the mounting table 2 in parallel, and the shower head 16 is at the ground potential. Therefore, the shower head 16 and the mounting table 2 function as a pair of counter electrodes (upper electrode and lower electrode).
於載置台2之上面設有用以靜電吸附半導體晶圓W之靜電夾6。此靜電夾6係和絕緣體6b之間介設電極6a而構成，於電極6a連接著直流電源12。此外藉由從直流電源12對電極6a施加直流電壓，而利用庫倫力等來吸附半導體晶圓W。 An electrostatic chuck 6 for electrostatically adsorbing the semiconductor wafer W is provided on the upper surface of the mounting table 2. The electrode 6a is interposed between the electrostatic chuck 6 and the insulator 6b, and the DC power source 12 is connected to the electrode 6a. Further, by applying a DC voltage to the electrode 6a from the DC power source 12, the semiconductor wafer W is adsorbed by Coulomb force or the like.
於載置台2之內部形成有未圖示之冷媒流路，可於其中循環適宜的冷媒來控制溫度。此外，於載置台2連接有用以對半導體晶圓W內面側供給氦氣體等背側氣體(內面側熱傳氣體)之背側氣體供給配管30a,30b，從背側氣體供給源31對半導體晶圓W之內 面側供給背側氣體。此外，背側氣體供給配管30a係用以對半導體晶圓W之中央部供給背側氣體，背側氣體供給配管30b係用以對半導體晶圓W之周緣部供給背側氣體。藉由如此之構成，可將半導體晶圓W控制在既定溫度。此外，於聚焦環5之外側下方設有排氣環13。排氣環13係通過支撐台4而和處理室1導通著。 A refrigerant flow path (not shown) is formed inside the mounting table 2, and an appropriate refrigerant can be circulated therein to control the temperature. In addition, the back side gas supply pipes 30a and 30b for supplying the back side gas (inner surface side heat transfer gas) such as helium gas to the inner surface side of the semiconductor wafer W are connected to the mounting table 2, and the back side gas supply source 31 is provided. Within the semiconductor wafer W The back side gas is supplied to the face side. Further, the back side gas supply pipe 30a is for supplying the back side gas to the central portion of the semiconductor wafer W, and the back side gas supply pipe 30b is for supplying the back side gas to the peripheral portion of the semiconductor wafer W. With such a configuration, the semiconductor wafer W can be controlled at a predetermined temperature. Further, an exhaust ring 13 is provided below the outer side of the focus ring 5. The exhaust ring 13 is electrically connected to the processing chamber 1 through the support table 4.
於處理室1之頂壁部分，對向於載置台2而設置之淋灑頭16係於其下面設有多數的氣體釋出孔18，且於其上部設有氣體導入部16a。此外，於其內部形成有空間17。於氣體導入部16a連接有氣體供給配管15a，於此氣體供給配管15a之另一端係連接有用以供給電漿蝕刻用氣體(蝕刻氣體)等之處理氣體供給系統15。 In the top wall portion of the processing chamber 1, the shower head 16 provided to the mounting table 2 is provided with a plurality of gas discharge holes 18 on the lower surface thereof, and a gas introduction portion 16a is provided on the upper portion thereof. Further, a space 17 is formed inside thereof. The gas supply pipe 15a is connected to the gas introduction portion 16a, and the other end of the gas supply pipe 15a is connected to a process gas supply system 15 for supplying a plasma etching gas (etching gas).
從處理氣體供給系統15所供給之氣體係經由氣體供給配管15a、氣體導入部16a而到達淋灑頭16內部之空間17，從氣體釋出孔18朝半導體晶圓W被釋出。 The gas system supplied from the processing gas supply system 15 reaches the space 17 inside the shower head 16 via the gas supply pipe 15a and the gas introduction portion 16a, and is released from the gas release hole 18 toward the semiconductor wafer W.
於處理室1之下部形成有排氣埠19，於此排氣埠19連接著排氣系統20。可藉由使得設置於排氣系統20之真空泵作動來將處理室1內減壓至既定真空度。另一方面，於處理室1之側壁設有開閉半導體晶圓W之搬出入口的閘閥24。 An exhaust port 19 is formed at a lower portion of the processing chamber 1, and the exhaust port 19 is connected to the exhaust system 20. The inside of the processing chamber 1 can be depressurized to a predetermined degree of vacuum by actuating a vacuum pump provided in the exhaust system 20. On the other hand, a gate valve 24 that opens and closes the carry-out port of the semiconductor wafer W is provided on the side wall of the processing chamber 1.
另一方面，於處理室1之周圍以同心圓狀配置著環磁石21。此環磁石21係由上側環磁石21a以及配置 於此上側環磁石21a下側之下側環磁石21b所構成，於載置台2與淋灑頭16之間的空間形成既定磁場。此環磁石21係可藉由未圖示之馬達等旋轉機構來旋轉。 On the other hand, the ring magnet 21 is arranged concentrically around the processing chamber 1. This ring magnet 21 is composed of the upper ring magnet 21a and the configuration The lower ring magnet 21b is formed on the lower side of the upper ring magnet 21a, and a predetermined magnetic field is formed in the space between the mounting table 2 and the shower head 16. This ring magnet 21 can be rotated by a rotating mechanism such as a motor (not shown).
上述構成之電漿處理裝置係藉由控制部60來統籌控制其動作。此控制部60係具備有：程序控制器61，係具有CPU，對電漿處理裝置之各部進行控制；使用者介面部62；以及記憶部63。 The plasma processing apparatus of the above configuration is controlled by the control unit 60 to coordinate the operation. The control unit 60 includes a program controller 61 having a CPU for controlling each unit of the plasma processing apparatus, a user interface 62, and a memory unit 63.
使用者介面部62係由製程管理者為了管理電漿處理裝置而進行指令輸入操作之鍵盤、將電漿處理裝置之運轉狀況予以視覺化顯示之顯示器等所構成。 The user interface 62 is composed of a keyboard for command input operation for managing the plasma processing device, a display for visually displaying the operation state of the plasma processing device, and the like.
於記憶部63儲藏有配方，此配方係儲存了利用程序控制器61之控制以實現在電漿處理裝置所實行之各種處理的控制程式(軟體)或處理條件數據等。此外，視必要性依據來自使用者介面部62之指示等而從記憶部63叫出任意配方而於程序控制器61實行，藉此，於程序控制器61之控制下以電漿處理裝置進行所希望之處理。此外，控制程式、處理條件數據等配方可利用被儲藏在電腦可讀取之電腦記錄媒體(例如硬碟、CD、軟碟、半導體記憶體等)等之狀態下者，或是也可從其他裝置例如經由專用配線而隨時傳送以線上利用。 A recipe is stored in the memory unit 63, and the recipe stores control programs (software), processing condition data, and the like that are controlled by the program controller 61 to implement various processes performed by the plasma processing apparatus. Further, depending on the necessity, an arbitrary recipe is called from the memory unit 63 in accordance with an instruction from the user interface 62, etc., and is executed by the program controller 61, whereby the plasma processing apparatus performs the control under the control of the program controller 61. Hope to deal with. In addition, recipes such as control programs and processing condition data may be stored in a computer-readable computer recording medium (for example, a hard disk, a CD, a floppy disk, a semiconductor memory, etc.), or may be other The device is transmitted at any time, for example, via dedicated wiring for use on the line.
其次，針對以上述構成之電漿處理裝置來對半導體晶圓W進行電漿蝕刻之順序做說明。首先，開放閘閥24，使得半導體晶圓W以未圖示之搬送機械人等經由未圖示之加載互鎖室來搬入處理室1內，而載置於 載置台2上。之後，使得搬送機械人退避到處理室1外，關閉閘閥24。然後，以排氣系統20之真空泵來經由排氣埠19對處理室1內進行排氣。 Next, a procedure for plasma etching the semiconductor wafer W by the plasma processing apparatus having the above configuration will be described. First, the gate valve 24 is opened, and the semiconductor wafer W is carried into the processing chamber 1 via a load lock chamber (not shown) via a transfer locker (not shown). On the mounting table 2. Thereafter, the transport robot is evacuated to the outside of the processing chamber 1, and the gate valve 24 is closed. Then, the inside of the processing chamber 1 is exhausted via the exhaust port 19 by a vacuum pump of the exhaust system 20.
當處理室1內成為既定真空度後，對處理室1內從處理氣體供給系統15導入既定處理氣體，將處理室1內保持在既定壓力例如13.3Pa(100mTorr)，於此狀態下從第1高頻電源10a、第2高頻電源10b對載置台2供給高頻電力。此時，從直流電源12對靜電夾6之電極6a施加既定直流電壓，半導體晶圓W乃因庫倫力等被吸附至靜電夾6。 When the inside of the processing chamber 1 is a predetermined degree of vacuum, a predetermined processing gas is introduced into the processing chamber 1 from the processing gas supply system 15, and the inside of the processing chamber 1 is maintained at a predetermined pressure, for example, 13.3 Pa (100 mTorr), and in this state, the first processing is performed. The high-frequency power source 10a and the second high-frequency power source 10b supply high-frequency power to the mounting table 2. At this time, a predetermined DC voltage is applied from the DC power source 12 to the electrode 6a of the electrostatic chuck 6, and the semiconductor wafer W is adsorbed to the electrostatic chuck 6 by Coulomb force or the like.
於此情況下，藉由如上述般對下部電極之載置台2施加高頻電力，會於上部電極之淋灑頭16與下部電極之載置台2之間形成電場。另一方面，於上部電極之淋灑頭16與下部電極之載置台2之間會因藉由環磁石21形成有磁場，故於半導體晶圓W所存在之處理空間會因為電子之遷移而產生磁控放電，半導體晶圓W會因所形成之處理氣體的電漿作用而被施以既定電漿處理。 In this case, by applying high-frequency power to the mounting table 2 of the lower electrode as described above, an electric field is formed between the shower head 16 of the upper electrode and the mounting table 2 of the lower electrode. On the other hand, since the magnetic field is formed by the ring magnet 21 between the shower head 16 of the upper electrode and the mounting table 2 of the lower electrode, the processing space existing in the semiconductor wafer W is generated by the migration of electrons. For magnetron discharge, the semiconductor wafer W is subjected to a predetermined plasma treatment due to the plasma action of the formed process gas.
然後，一旦既定電漿處理結束，乃停止高頻電力之供給以及處理氣體之供給，以和上述順序為相反的順序將半導體晶圓W從處理室1內搬出。 Then, when the predetermined plasma processing is completed, the supply of the high-frequency power and the supply of the processing gas are stopped, and the semiconductor wafer W is carried out from the processing chamber 1 in the reverse order to the above-described order.
其次，針對本發明之半導體裝置的製造方法之一實施形態，參見圖2、圖3來說明。圖2係示意顯示本實施形態之被處理基板的半導體晶圓W之截面構成，係顯示本實施形態之製程，圖3係顯示本實施形 態之製程之流程圖。 Next, an embodiment of a method of manufacturing a semiconductor device of the present invention will be described with reference to Figs. 2 and 3 . Fig. 2 is a cross-sectional view showing the semiconductor wafer W of the substrate to be processed according to the embodiment, showing the process of the embodiment, and Fig. 3 showing the embodiment. Flow chart of the process.
如圖2(a)所示般，於半導體晶圓W之最上部係形成有被圖案化成為既定形狀而發揮光罩功能的光阻膜200。此光阻膜200之厚度係設定在例如5μm程度。於光阻膜200之下側形成有做為絕緣膜之二氧化矽(SiO2)膜201a，於二氧化矽膜201a之下側形成有做為導電膜之多晶矽膜(經摻雜之多晶矽膜)202a。 As shown in FIG. 2( a ), a photoresist film 200 that is patterned into a predetermined shape and functions as a mask is formed on the uppermost portion of the semiconductor wafer W. The thickness of the photoresist film 200 is set to, for example, about 5 μm. A ruthenium dioxide (SiO 2 ) film 201a as an insulating film is formed on the lower side of the photoresist film 200, and a polycrystalline ruthenium film (doped polysilicon film) as a conductive film is formed on the lower side of the ruthenium dioxide film 201a. ) 202a.
此外，於多晶矽膜202a之下側形成有二氧化矽膜201b，於二氧化矽膜201b之下側形成有多晶矽膜202b。如此般，二氧化矽膜201與多晶矽膜202交互積層而構成積層膜210。積層膜210之積層數例如二氧化矽膜201為32層、多晶矽膜202為32層，合計64層等。 Further, a ruthenium dioxide film 201b is formed on the lower side of the polysilicon film 202a, and a polysilicon film 202b is formed on the lower side of the ruthenium dioxide film 201b. In this manner, the ruthenium dioxide film 201 and the polysilicon film 202 are alternately laminated to form the buildup film 210. The number of layers of the build-up film 210 is, for example, 32 layers of the ruthenium dioxide film 201 and 32 layers of the polysilicon film 202, and a total of 64 layers or the like.
此外，於本實施形態，係以二氧化矽(SiO2)膜與多晶矽膜(經摻雜之多晶矽膜)所積層而得之積層膜為例來說明，但在積層膜方面可適用於具有第1介電係數之第1膜與具有有別於第1介電係數之第2介電係數的第2膜所積層之構造的積層膜。更具體而言，可適用於例如由二氧化矽膜與氮化矽膜所積層而構成之積層膜、由多晶矽膜與經摻雜之多晶矽膜所積層而構成之積層膜等。 Further, in the present embodiment, a laminated film obtained by laminating a cerium oxide (SiO 2 ) film and a polycrystalline germanium film (doped polycrystalline germanium film) is exemplified, but it is applicable to a laminated film. A laminated film having a structure in which a first film having a dielectric constant is laminated with a second film having a second dielectric constant different from the first dielectric constant. More specifically, it can be suitably applied to, for example, a laminated film composed of a layer formed of a hafnium oxide film and a tantalum nitride film, a laminated film composed of a polycrystalline tantalum film and a doped polycrystalline germanium film, and the like.
從圖2(a)所示之狀態，首先，以光阻膜200為光罩，將二氧化矽膜201a加以電漿蝕刻成為圖2(b)之狀態(圖3所示製程301)。此電漿蝕刻處理係使用例如CF4+CHF3等處理氣體之電漿來進行。 From the state shown in Fig. 2(a), first, the photoresist film 200 is used as a mask, and the ruthenium dioxide film 201a is plasma-etched into the state of Fig. 2(b) (the process 301 shown in Fig. 3). This plasma etching treatment is carried out using a plasma of a processing gas such as CF 4 +CHF 3 .
其次，為了將因為電漿蝕刻所產生之沉積物，尤其是沉積於光阻膜200側壁部的沉積物220加以去除而進行沉積物去除處理成為圖2(c)之狀態(圖3所示製程302)。此沉積物去除處理係使用例如O2+CF4等處理氣體電漿來進行。 Next, in order to remove the deposits generated by the plasma etching, particularly the deposits 220 deposited on the sidewall portions of the photoresist film 200, the deposit removal process becomes the state of FIG. 2(c) (the process shown in FIG. 3) 302). This deposit removal treatment is carried out using a treatment gas plasma such as O 2 +CF 4 .
其次，對光阻膜200上面進行改質處理(熟化)，於光阻膜200上面形成改質膜200a，成為圖2(d)之狀態(圖3所示製程303)。此改質處理(熟化)係藉由將光阻膜200暴露於含氫之電漿中來進行。 Next, the upper surface of the photoresist film 200 is subjected to a reforming treatment (aging), and a modified film 200a is formed on the upper surface of the photoresist film 200 to be in the state of FIG. 2(d) (process 303 shown in FIG. 3). This modification treatment (curing) is performed by exposing the photoresist film 200 to a hydrogen-containing plasma.
其次，進行光阻膜200之修整處理，擴大光阻膜200之開口面積。亦即，使得光阻膜200下側之二氧化矽膜201a之一部分露出，成為圖2(e)之狀態(圖3所示製程304)。此修整處理係使用例如O2+N2等處理氣體電漿來進行。 Next, the trimming process of the photoresist film 200 is performed to enlarge the opening area of the photoresist film 200. That is, a portion of the ceria film 201a on the lower side of the photoresist film 200 is exposed to be in the state of FIG. 2(e) (process 304 shown in FIG. 3). This conditioning treatment is carried out using a treatment gas plasma such as O 2 + N 2 .
其次，以光阻膜200以及部分露出之二氧化矽膜201a為光罩，將二氧化矽膜201a下側之多晶矽膜202a加以電漿蝕刻而成為圖2(f)之狀態(圖3所示製程305)。此電漿蝕刻處理係使用例如HBr+SF6+He等處理氣體電漿來進行。 Next, the photoresist film 200 and the partially exposed ceria film 201a are used as a mask, and the polysilicon film 202a on the lower side of the ceria film 201a is plasma-etched to be in the state of FIG. 2(f) (FIG. 3) Process 305). This plasma etching treatment is performed using a processing gas plasma such as HBr + SF 6 + He.
藉由上述製程來形成第一段之階梯形狀。之後，使得從上述二氧化矽膜201之電漿蝕刻到多晶矽膜202之電漿蝕刻的製程反覆實施既定次數(圖3所示製程306)，形成既定段數之階梯狀構造。 The step shape of the first segment is formed by the above process. Thereafter, the plasma etching process from the plasma etching of the above-described ceria film 201 to the polysilicon film 202 is repeated for a predetermined number of times (the process 306 shown in FIG. 3) to form a stepped structure having a predetermined number of stages.
如上述般，於本實施形態，在進行多晶矽膜202之電漿蝕刻的前一製程進行光阻膜200之修整處理。 此乃由於，於剛進行完多晶矽膜202之電漿蝕刻之後，光阻膜200側壁等沉積物之沉積量增大，不容易進行光阻膜200之修整之故。 As described above, in the present embodiment, the trimming process of the photoresist film 200 is performed in the previous process of performing plasma etching of the polysilicon film 202. This is because, after the plasma etching of the polysilicon film 202 is completed, the deposition amount of the deposits on the sidewalls of the photoresist film 200 is increased, and the trimming of the photoresist film 200 is not easy.
例如，若於二氧化矽膜201之電漿蝕刻後，其次進行多晶矽膜202之電漿蝕刻，之後再進行光阻膜200之修整，則由於在光阻膜200側壁等處，起因於多晶矽膜202之蝕刻的沉積物沉積量增大，而不容易進行光阻膜200之修整。 For example, after the plasma etching of the ruthenium dioxide film 201, the plasma etching of the polysilicon film 202 is performed next, and then the photoresist film 200 is trimmed, since it is caused by the polysilicon film on the sidewall of the photoresist film 200 or the like. The deposit of the etched deposit of 202 is increased, and the trimming of the photoresist film 200 is not easy.
相對於此，如本實施形態般，藉由在進行多晶矽膜202之電漿蝕刻的前一製程來進行光阻膜200之修整處理，可更容易地在短時間進行大量之修整。 On the other hand, as in the present embodiment, by performing the trimming process of the photoresist film 200 in the previous process of plasma etching of the polysilicon film 202, it is possible to more easily perform a large amount of trimming in a short time.
此外，於形成階梯狀構造下一段之際，由於係在多晶矽膜202之電漿蝕刻後實施二氧化矽膜201之電漿蝕刻與沉積物去除製程，故同樣可更容易於短時間進行大量之修整。 In addition, when the lower stage of the stepped structure is formed, since the plasma etching and deposit removal process of the ruthenium dioxide film 201 is performed after the plasma etching of the polysilicon film 202, it is also easier to carry out a large amount in a short time. trim.
此外，於本實施形態，由於係在修整處理前進行光阻膜200上面之改質處理，故於修整處理之際，可抑制修整光阻膜200上面之量。從而，於修整處理中，光阻膜200之膜厚減少(圖2(e)所示y)受到抑制，而光阻膜200之水平方向之修整量(圖2(e)所示x)變多，可減低修整比y/x。 Further, in the present embodiment, since the modification treatment of the upper surface of the photoresist film 200 is performed before the trimming process, the amount of the upper surface of the photoresist film 200 can be suppressed during the trimming process. Therefore, in the trimming process, the film thickness of the photoresist film 200 is reduced (y is shown in Fig. 2(e)), and the trimming amount of the photoresist film 200 in the horizontal direction (x shown in Fig. 2(e)) is changed. More, can reduce the trim ratio y / x.
在實施例方面，使用圖1所示構造之電漿處理裝置，如圖2所示般，對於做為絕緣膜之二氧化矽膜與做為導電膜之多晶矽膜所交互積層而得之積層膜以下述處理條件進行處理，而形成階梯狀構造。 In the embodiment, a plasma processing apparatus having the configuration shown in FIG. 1 is used, as shown in FIG. 2, a laminated film obtained by laminating a ceria film as an insulating film and a polysilicon film as a conductive film. The treatment was carried out under the following processing conditions to form a stepped structure.
(二氧化矽膜之蝕刻) (etching of ruthenium dioxide film)
處理氣體：CF4/CHF3=175/25sccm Processing gas: CF 4 /CHF 3 =175/25sccm
壓力：16.0Pa(120mTorr) Pressure: 16.0Pa (120mTorr)
高頻電力(高頻率之高頻/低頻率之高頻)：500W/200W High frequency power (high frequency high frequency / low frequency high frequency): 500W/200W
(沉積物去除) (sediment removal)
處理氣體：O2/CF4=150/350sccm Processing gas: O 2 /CF 4 =150/350sccm
壓力：26.6Pa(200mTorr) Pressure: 26.6Pa (200mTorr)
高頻電力(高頻率之高頻/低頻率之高頻)：1500W/0W High frequency power (high frequency high frequency / low frequency high frequency): 1500W/0W
(光阻膜之改質) (modified of photoresist film)
處理氣體：H2/He=300/500sccm Processing gas: H 2 /He=300/500sccm
壓力：2.66Pa(20mTorr) Pressure: 2.66Pa (20mTorr)
高頻電力(高頻率之高頻/低頻率之高頻)：300W/0W High frequency power (high frequency high frequency / low frequency high frequency): 300W/0W
(光阻膜之修整) (repair of photoresist film)
處理氣體：O2/N2=300/75sccm Processing gas: O 2 /N 2 =300/75sccm
壓力：33.3Pa(250mTorr) Pressure: 33.3Pa (250mTorr)
高頻電力(高頻率之高頻/低頻率之高頻)：500W/0W High frequency power (high frequency high frequency / low frequency high frequency): 500W/0W
(多晶矽膜之蝕刻) (etching of polysilicon film)
處理氣體：HBr/SF6/He=400/70/200sccm Processing gas: HBr/SF 6 /He=400/70/200sccm
壓力：6.66Pa(50mTorr) Pressure: 6.66Pa (50mTorr)
高頻電力(高頻率之高頻/低頻率之高頻)：0W/500W High frequency power (high frequency high frequency / low frequency high frequency): 0W/500W
反覆實施上述製程複數次之後，對半導體晶圓W以電子顯微鏡放大觀察的結果，確認形成了良好形狀之階梯狀構造。 After repeating the above-described process several times, the semiconductor wafer W was observed by an electron microscope, and it was confirmed that a stepped structure having a good shape was formed.
此外，上述修整製程中之修整比(y/x)為0.7程度。另一方面，做為比較例，針對於修整製程前未進行光阻改質之情況下測定修整比(y/x)之結果為1.6程度。從而，確認了藉由如本實施例般進行光阻改質，可大幅改善修整比。此外，之所以如上述般在光阻之改質上使用H2/He之混合氣體做為處理氣體，乃因若使用H2之單一氣體進行光阻改質，則改質效果會過高，修整製程中之修整會變得困難，而藉由加入He氣體可抑制光阻之改質效果。 Further, the trimming ratio (y/x) in the above trimming process is about 0.7. On the other hand, as a comparative example, the result of measuring the trim ratio (y/x) in the case where the photoresist modification was not performed before the trimming process was 1.6 degrees. Thus, it was confirmed that the photoresist modification was carried out as in the present embodiment, and the trimming ratio was greatly improved. In addition, as described above, the mixed gas of H 2 /He is used as the processing gas in the modification of the photoresist, because if the single gas of H 2 is used for the photoresist modification, the modification effect is too high. The trimming process in the trimming process becomes difficult, and the modification effect of the photoresist can be suppressed by adding He gas.
此外，於光阻改質之製程所能使用之He/H2之流量比，考慮到改質效果與修整容易度，可在大概0~10%之範圍來調整。此外，壓力可使用1.33~6.66Pa(10~50mT)之範圍，雖壓力愈高則修整比愈佳，但和光阻層側壁之粗糙程度呈取捨(trade off)關係。再者，有助於電漿生成之高頻電力的功率可使用200~500W之範圍，功率愈高則修整比愈佳，但和光阻層側壁之粗糙程度呈取捨關係。 In addition, the flow ratio of He/H 2 which can be used in the process of photoresist modification can be adjusted in the range of approximately 0 to 10% in consideration of the effect of reforming and the ease of trimming. In addition, the pressure can be used in the range of 1.33 to 6.66 Pa (10 to 50 mT). The higher the pressure, the better the trim ratio, but the trade-off relationship with the roughness of the sidewall of the photoresist layer. Furthermore, the power of the high-frequency power contributing to the plasma generation can be in the range of 200 to 500 W. The higher the power, the better the trim ratio, but the roughness of the sidewall of the photoresist layer is a trade-off relationship.
此外，上述修整製程中x方向之修整量，於反覆進行上述製程複數次之際，從第1次到第10次為300nm程度而維持在大致一定。另一方面，未進行沉積物去除之比較例，第1次之x方向修整量為220nm程度，第10次則降低至180nm程度。從而，確認了 藉由如本實施例般進行沉積物去除，可增加x方向之修整量，且即使反覆進行複數次製程也可得到穩定之x方向的修整量。 In addition, the trimming amount in the x direction in the above-described trimming process is maintained at substantially constant from the first time to the tenth time at a level of 300 nm when the above-described process is repeated plural times. On the other hand, in the comparative example in which the deposit removal was not performed, the trimming amount in the x-direction of the first time was about 220 nm, and the thickness was reduced to about 180 nm in the tenth time. Thus, confirmed By performing deposit removal as in the present embodiment, the amount of trimming in the x direction can be increased, and a stable trimming amount in the x direction can be obtained even if a plurality of processes are repeatedly performed.
於上述光阻膜200上面之改質處理，在處理氣體方面雖使用了H2氣體與He氣體之混合氣體，惟處理氣體亦可使用H2氣體與He氣體與含矽氣體(例如SiF4氣體、SiCl4氣體等)之混合氣體。當使用如此之混合氣體之情況，除了以H2氣體之作用來改質光阻，並可於光阻表面形成矽酸碳等塗布層，藉此可減少修整比(y/x)。 In the reforming process on the photoresist film 200, a mixed gas of H 2 gas and He gas is used for the processing gas, but the H 2 gas and the He gas and the helium containing gas (for example, SiF 4 gas) may be used as the processing gas. , a mixed gas of SiCl 4 gas, etc.). When such a mixed gas is used, in addition to the modification of the photoresist by the action of H 2 gas, a coating layer such as tantalum carbon can be formed on the surface of the photoresist, whereby the trim ratio (y/x) can be reduced.
圖4中顯示了以縱軸為修整比(y/x)、橫軸為SiF4氣體流量而調查了SiF4氣體流量與修整比之關係的結果。此外，於此情況之光阻膜200之上面改質處理係以下述條件進行。 Fig. 4 shows the results of examining the relationship between the SiF 4 gas flow rate and the dressing ratio with the vertical axis as the trim ratio (y/x) and the horizontal axis as the SiF 4 gas flow rate. Further, the above-described reforming treatment of the photoresist film 200 in this case was carried out under the following conditions.
處理氣體：H2/He/SiF4=100/700/XXsccm Processing gas: H 2 /He/SiF 4 =100/700/XXsccm
壓力：20.0Pa(150mTorr) Pressure: 20.0Pa (150mTorr)
高頻電力(高頻率之高頻/低頻率之高頻)：300W/300W High frequency power (high frequency high frequency / low frequency high frequency): 300W/300W
如圖4所示般，確認了當SiF4氣體之流量從0增加到20sccm，則修整比會對應於SiF4流量而降低。此外，為了得到降低修整比之效果，必須流經一定程度量之SiF4氣體。另一方面，若SiF4氣體流量過多雖修整比會降低，但光阻膜之修整速度會降低，而為了得到所希望之修整量的處理時間則會變長。因此，SiF4氣體之流量相對於H2氣體之流量比(SiF4氣體流量/H2 氣體流量)設定在5~30%之範圍內為佳，設定為10~20%之範圍內為更佳。 As shown in Fig. 4, it was confirmed that when the flow rate of the SiF 4 gas was increased from 0 to 20 sccm, the trim ratio was lowered corresponding to the SiF 4 flow rate. Further, in order to obtain the effect of lowering the trim ratio, it is necessary to flow a certain amount of SiF 4 gas. On the other hand, if the flow rate of the SiF 4 gas is too large, the trimming ratio is lowered, but the dressing speed of the photoresist film is lowered, and the processing time for obtaining the desired trim amount becomes long. Thus, SiF 4 gas flow rate of H 2 gas flow rate with respect to the ratio of (SiF 4 gas flow rate / H 2 gas flow rate) is set in a range of preferably 5 to 30%, more preferably set to within a range of 10 to 20% .
此外，於上述實施形態以及實施例乃針對積層膜210係由做為絕緣膜之二氧化矽(SiO2)膜201a等與做為導電膜之多晶矽膜(經摻雜之多晶矽膜)202a等所構成之情況做了說明。但是，如前述般，亦可適用於介電係數不同的2種膜，例如適用於由二氧化矽膜與氮化矽膜所積層構成之積層膜、由多晶矽膜與經摻雜之多晶矽膜所積層構成之積層膜等。 Further, in the above-described embodiments and examples, the buildup film 210 is made of a ruthenium dioxide (SiO 2 ) film 201a or the like as an insulating film, and a polysilicon film (doped polysilicon film) 202a as a conductive film. The situation of the composition is explained. However, as described above, it is also applicable to two types of films having different dielectric constants, for example, a laminated film composed of a layer of a hafnium oxide film and a tantalum nitride film, a polycrystalline tantalum film and a doped polycrystalline germanium film. A laminate film or the like which is laminated.
於此情況，關於沉積物去除、光阻上面之改質、光阻之修整可和上述實施例同樣地進行。此外，關於蝕刻，針對二氧化矽膜、多晶矽膜以及經摻雜之多晶矽膜能和上述實施例同樣地進行。關於氮化矽膜之蝕刻可使用例如CH2F2、CHF3、CF4、CH3F等氣體系。更具體而言，例如能以下述條件來進行氮化矽膜之蝕刻。 In this case, the removal of the deposit, the modification of the photoresist, and the trimming of the photoresist can be carried out in the same manner as in the above embodiment. Further, regarding the etching, the ruthenium dioxide film, the polysilicon film, and the doped polysilicon film can be carried out in the same manner as in the above embodiment. As the etching of the tantalum nitride film, for example, a gas system such as CH 2 F 2 , CHF 3 , CF 4 or CH 3 F can be used. More specifically, for example, etching of a tantalum nitride film can be performed under the following conditions.
處理氣體：CF4/CHF3=25/175sccm Processing gas: CF 4 /CHF 3 =25/175sccm
壓力：16.0Pa(120mTorr) Pressure: 16.0Pa (120mTorr)
高頻電力(高頻率之高頻/低頻率之高頻)：500W/200W High frequency power (high frequency high frequency / low frequency high frequency): 500W/200W
此外，本發明不限定於上述實施形態以及實施例，可作各種變形。例如，電漿處理裝置不限定於圖示之平行平板型之下部雙頻施加型，亦可使用例如對上部電極與下部電極分別施加高頻之類型的電漿處理裝置、對下部電極施加單頻之高頻電力之類型的電漿 處理裝置等各種電漿處理裝置。 Further, the present invention is not limited to the above-described embodiments and examples, and various modifications can be made. For example, the plasma processing apparatus is not limited to the parallel flat type lower double frequency application type shown in the drawing, and for example, a plasma processing apparatus of a type that applies a high frequency to the upper electrode and the lower electrode, and a single frequency to the lower electrode may be used. Plasma of the type of high frequency power Various plasma processing devices such as processing devices.
200‧‧‧光阻膜 200‧‧‧Photoresist film
201‧‧‧二氧化矽膜 201‧‧‧2O2 film
202‧‧‧多晶矽膜 202‧‧‧ Polysilicon film
210‧‧‧積層膜 210‧‧‧ laminated film
W‧‧‧半導體晶圓 W‧‧‧Semiconductor Wafer
圖1係示意顯示本發明之一實施形態所使用之電漿處理裝置之概略構成圖。 Fig. 1 is a schematic block diagram showing a plasma processing apparatus used in an embodiment of the present invention.
圖2係示意顯示本發明之一實施形態之半導體晶圓截面之概略構成圖。 Fig. 2 is a schematic block diagram showing a cross section of a semiconductor wafer according to an embodiment of the present invention.
圖3係顯示本發明之一實施形態之製程的流程圖。 Figure 3 is a flow chart showing a process of an embodiment of the present invention.
圖4係顯示SiF4之流量與修整比例之關係圖。 Figure 4 is a graph showing the relationship between the flow rate of SiF 4 and the trim ratio.
200‧‧‧光阻膜 200‧‧‧Photoresist film
201a~201h‧‧‧二氧化矽膜 201a~201h‧‧‧2O2 film
202a~202h‧‧‧多晶矽膜 202a~202h‧‧‧ Polysilicon film
210‧‧‧積層膜 210‧‧‧ laminated film
220‧‧‧沉積物 220‧‧‧Sediment
W‧‧‧半導體晶圓 W‧‧‧Semiconductor Wafer
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