KR100784868B1 - A Semiconductor Device and Method for Forming Thereof - Google Patents

Abstract

Provided are a selection transistor having an asymmetric gate electrode structure, a memory transistor having a floating gate having an approximately 'ㅗ' shape, and a method of forming the same. The gate electrode portion of the selection transistor adjacent to the memory transistor has a substantially 'cross' cross-section, and the gate electrode portion of the selection transistor opposite to the memory transistor has a substantially box-shaped cross section. When opening the region in which the memory transistor is formed to form the floating gate of the memory transistor in a 'ㅗ' shape, the region in which the selection transistor is formed is closed.

Flash memory, floating gates, coupling ratios, loading effects

Description

A semiconductor device and method for forming thereof

1 is a schematic plan view of a NAND flash memory device according to an embodiment of the present invention.

2 is an enlarged view of a portion indicated by reference numeral 90 of FIG. 1, that is, an enlarged portion of a boundary between a first region 10 in which a memory transistor is formed and a second region 20 in which a selection transistor is formed.

3 to 8 are cut along the lines II ′, II-II ′, III-III ′, IV-VI ′, V-V ′, and VI-VI ′ of FIG. 2, respectively. It is a cross section of the time.

9A is a view schematically illustrating a cross section of the floating gate electrode when cut along the control gate extension direction according to an exemplary embodiment.

9B is a perspective view illustrating an arrangement of a floating gate electrode according to an exemplary embodiment of the present invention.

10 is a cross-sectional view schematically illustrating a NAND flash memory device according to an embodiment of the present invention.

11 to 16 are diagrams for describing a method of forming a NAND flash memory device according to an embodiment of the present invention.

19 is a view illustrating a memory transistor of a flash memory device according to another embodiment of the present invention.

20 schematically shows a flash memory device according to another embodiment of the present invention.

21 schematically shows a flash memory device according to another embodiment of the present invention.

22A to 22H are cross-sectional views illustrating a method of manufacturing a NAND flash memory device according to an embodiment of the present invention.

23A and 23B are cross-sectional views illustrating a method of manufacturing a NAND flash memory according to another embodiment of the present invention.

24A and 24B are cross-sectional views illustrating a method of manufacturing a NAND flash memory device according to still another embodiment of the present invention.

25A to 25E are cross-sectional views illustrating a method of manufacturing a NAND flash memory according to another embodiment of the present invention.

26A and 26B are cross-sectional views illustrating a method of manufacturing a NAND flash memory according to another embodiment of the present invention.

27A through 27E are diagrams for describing a floating gate forming method of a flash memory device, according to another exemplary embodiment.

28A to 28C are diagrams for describing a floating gate forming method of a flash memory device, according to another exemplary embodiment.

TECHNICAL FIELD The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a nonvolatile memory and a method for manufacturing the same.

Memory semiconductor devices are classified into volatile memory devices and nonvolatile memory devices depending on whether power is required to maintain stored information. Volatile memory devices, such as DRAM and SRAM, have a high operating speed, but have a limitation in that a power supply is required to maintain information. In contrast, nonvolatile memory devices, such as flash memory, have no such limitation, and thus are widely used in portable electronic devices, which are rapidly increasing in recent years.

For example, a flash memory device includes a memory cell that functions to store information and a device related thereto such as a selection transistor, a driving transistor, and the like. As a memory cell of a flash memory device, a memory transistor having a structure similar to that of a typical transistor is widely used. The memory transistor includes a gate stacked structure in which a tunneling insulating film, a floating gate, an insulating film between gates, and a control gate are sequentially stacked on the channel region, and impurity junction regions on both sides thereof. Floating gates of adjacent memory transistors are electrically isolated from each other, and each floating gate functions as a memory. For example, control gates of a plurality of memory transistors arranged in a row direction are connected to each other to function as word lines. Flash memory devices can be classified into NAND and NOA types according to the arrangement of memory transistors having such a structure. In the NAND flash memory device, a selection transistor is connected to the memory transistor. For example, gates of the selection transistors arranged in the row direction are connected to each other to form a selection line.

In order to reduce the price of the semiconductor device, it is necessary to improve the degree of integration, but the improvement of the degree of integration causes various technical difficulties in the manufacturing process of the semiconductor device. In particular, the improvement in density entails reducing the spacing between adjacent word lines, which makes it difficult to improve the structure and characteristics of the nonvolatile memory. For example, a nonvolatile memory device having a control gate electrode and a floating gate electrode should have a sufficiently large coupling ratio for fast and effective operation, but a reduction in the spacing between the word lines is due to this coupling ratio. Make it difficult to secure

In addition, the width of the word line and the interval between adjacent word lines is smaller than the width of the word line and the selection line and the distance between the selection line and the word line, so that a loading effect occurs in the etching process to form the selection line. The active region of the substrate to be subjected to etching may be damaged.

In addition, an increase in the degree of integration of the memory device may cause a so-called short channel effect accompanied by a decrease in the channel length of the selection transistor. For example, the channel doping concentration is relatively low in the vicinity of the center region of the channel region, so that punchthrough is more likely to occur. In addition, the possibility of punch-through occurs in the memory transistor adjacent to the selection transistor.

Embodiments of the present invention provide a semiconductor device and a method of manufacturing the same that can alleviate at least one or more of the above-mentioned problems.

In an embodiment, a semiconductor device may include a first gate formed on an active region of a substrate defined by device isolation layer patterns; A first insulating film formed between the first gate and the active region; And a first impurity region and a second impurity region formed in the active regions on both sides of the first gate, wherein the cross-sectional shape of the first portion of the first gate adjacent to the first impurity region and the second impurity region are included. Cross-sectional shapes of the second portion of the first gate adjacent to the impurity region are different from each other.

In this embodiment, the cross-section of the first portion of the first gate may have a substantially 'ㅗ' shape, and the second portion of the first gate may have a box shape.

In an exemplary embodiment, a NAND flash memory device may include: a selection transistor formed on an active region of a substrate defined by device isolation layer patterns; And a plurality of memory transistors formed on the active region and connected in series to the selection transistor, wherein each of the selection transistor and the memory transistor are sequentially formed on the active region and the first gate and the first gate, respectively. And a stacked gate structure comprising a second insulating film and a second gate, wherein a cross section of the first gate of the memory transistor and a cross section of the first portion of the first gate of the select transistor adjacent to the memory transistor are substantially the same. The cross-sectional shape of the second portion of the first gate of the selection transistor opposite to the memory transistor is different from the cross-sectional shape of the first portion of the first gate of the selection transistor.

In an embodiment, a method of forming a semiconductor device includes: forming a first insulating layer and a first conductive layer pattern on an active region of a substrate defined by device isolation layer patterns; Etching lower portions of the device isolation layer patterns to form lowered device isolation layer patterns covering side surfaces of the lower pattern portion of the first conductive layer pattern; Etching the upper pattern portion of the first conductive layer pattern protruding upward from the lower surface of the lower device isolation layer patterns in a lateral direction to form a narrowed upper pattern portion narrower than the lower pattern portion of the first conductive layer pattern; Patterning a first conductive layer pattern having the lower pattern portion and the narrowed upper pattern portion to form a first portion patterned from the lower pattern portion and the upper pattern portion and a first conductive layer adjacent to the device isolation layer patterns; Forming a first gate having two portions; The method may include forming first and second impurity regions adjacent to the first and second portions of the first gate, respectively.

A method of forming a NAND flash memory device according to an embodiment of the present invention may include: forming a first insulating film and a first conductive film pattern on an active region of a substrate defined by device isolation film patterns extending in a first direction; Etching the device isolation layer patterns of the first region in which the memory transistor of the substrate is to be formed in a downward direction to form lower device isolation layer patterns covering the side surface of the lower pattern portion of the first conductive layer pattern; Etching the upper pattern portion of the first conductive layer pattern protruding upward from the lower surface of the lower device isolation layer patterns in a lateral direction to form a narrowed upper pattern portion narrower than the lower pattern portion of the first conductive layer pattern; Forming a second insulating film and a second conductive film on the device isolation layer patterns, the lower device isolation layer patterns, and the first conductive layer pattern; The second conductive film, the second insulating film, and the first conductive film are patterned to extend in the first area in a second direction crossing the first direction from the second conductive film, thereby lowering the active area and the lowered area. And forming a floating gate of the memory transistor from the control gate of the memory transistor passing through the device isolation layer patterns, the gate insulating layer of the memory transistor from the second insulating layer, and the lower and upper pattern portions of the first conductive layer pattern. have.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the present invention to those skilled in the art. In the drawings, the thicknesses of films and regions are exaggerated for clarity. In addition, where the film is said to be 'on' another film or substrate, it may be formed directly on the other film or substrate, or a third film may be interposed therebetween.

In the drawings, the size of an element or the relative size between elements may be somewhat exaggerated for a clearer understanding of the present invention. In addition, the shape of the elements shown in the drawings may be somewhat changed by variations in the manufacturing process. Accordingly, the embodiments disclosed herein are not to be limited to the shapes shown in the drawings unless specifically stated, it should be understood to include some variation. For example, terms such as "substantially" or "approximately" used to describe the shape of an element herein should be understood to refer to a form in which an element includes process acceptable variations.

The present invention relates to a semiconductor device and a method of manufacturing the same, and an embodiment of the present invention will be described using a NAND flash memory device as an example. The NAND flash memory device of the present invention includes a plurality of memory cells and a selection transistor associated therewith. The selection transistor functions to transfer or block an operating voltage required for the operation of the NAND flash memory device to the memory transistor. As a memory cell, a description will be given by taking a memory transistor showing a stacked gate structure as an example. The stacked gate structure of the memory transistor includes a floating gate insulated by the substrate (or channel region) and the tunneling insulating layer and a control gate insulated from the floating gate by the gate insulating film. At least two distinctive threshold voltages of the memory transistors due to the transfer of charge from the substrate to the floating gate through the tunneling insulating film or in the opposite direction by applying an appropriate operating voltage to the substrate, source, drain and control gate. In this state, the information can be stored.

The gate structure of the select transistor is similar to the stacked gate structure of the memory transistor in that it has a floating gate and a control gate, but the stacked gate structure of the memory transistor in that the floating gate and the control gate are electrically connected to each other by a butting contact or the like. Is different from In an exemplary embodiment of the present disclosure, the 'floating gate' of the selection transistor may be referred to as the 'first gate' and the 'control gate' of the selection transistor may be referred to as the 'second gate'.

A predetermined number, for example, 16, 32, ..., 2 ^m memory transistors may be connected in series to form a memory string. A first select transistor and a second select transistor are connected in series to the first and last memory transistors of the memory string, respectively. A bit line may be connected to the first select transistor and a common source line may be connected to the second select transistor.

1 is a schematic plan view of a NAND flash memory device according to an embodiment of the present invention. Referring to FIG. 1, a NAND flash memory device memory transistor according to an embodiment of the present invention and a select transistor related thereto are included. For convenience of explanation, in the following description of the exemplary embodiment, the region 10 in which the memory transistor is formed is referred to as a “first region”, and the region 20 in which the selection transistor is formed is referred to as a “second region”. do.

A plurality of device isolation layer patterns 40 extending in a row are disposed on the semiconductor substrate 30 to define an active region 50 extending in a first direction therebetween. The memory transistor is formed on the active region of the first region 10, and the selection transistor is formed on the active region of the second region 20. N memory transistors are connected in series to each of the active regions extending in the first direction in the first region 10 to form a memory string. The control gates of the plurality of memory transistors arranged in each column are connected to each other to form corresponding word lines WL0 to WLn. Alternatively, control gates of a plurality of memory transistors arranged in each column may be connected to the same word line.

In the second region 20, a select transistor is formed to be connected to the memory transistor of the first region 10. For example, a first select transistor (string select transistor) is connected to the first memory transistor of each memory string, and a second select transistor (ground select transistor) is connected in series to the last memory transistor. Second gates of the first selection transistors arranged in a row in the second region 20 are connected to each other to form a first selection line (or a string selection line SSL). The second gates of the second selection transistors arranged in a row in the second region 20 are connected to each other to form a second selection line (or a ground selection line GSL). In each of the selection transistors, the first electrode and the second electrode are electrically connected to each other by the butting contact 70.

In the semiconductor substrate 30, a complex structure including a string select line SSL and a ground select line GSL and a plurality of word lines WL0 to WLn therebetween is repeatedly arranged in mirror symmetry. The common source line CSL is positioned between the adjacent second select lines GSL, and an operating voltage applied to the ground select line according to on / off of the second select transistor, for example, 0 volt is applied to the source / source of the memory transistor. Delivered to the drain. The bit line contact DC is positioned in each of the active regions between the adjacent first selection lines SSL, and the bit line is electrically connected to each bit line contact DC. The operating voltage applied to the bit line is applied to the source / drain of the memory transistor depending on the on / off of the first selection transistor.

In FIG. 1, the reference numeral 60 indicated by the dotted line includes the first region 10 and a portion of the second region 20 adjacent to the first region, which is the region 60 (hereinafter referred to as the '' gate region '). Cross-sections of the first gate of the selection transistor and the floating gate of the memory transistor formed in FIG. In addition, for convenience of description, the region 80 except for the 'ㅗ' type gate region 60 in the second region 20 will be referred to as a "box type gate region".

2 is an enlarged view of a portion indicated by reference numeral 90 of FIG. 1, that is, an enlarged portion of a boundary between a first region 10 in which a memory transistor is formed and a second region 20 in which a selection transistor is formed. Referring to FIG. 2, the select transistor 100 includes a gate stacked structure formed by the first gate 130 and the second gate 170 electrically connected to each other, and an impurity region 191S / D formed in active regions at both sides of the gate stacked structure. ) And an impurity region 193S / D. On the other hand, the memory transistor 200 has a gate stacked structure of the floating gate 230 and the control gate 270 insulated from each other by the gate insulating film, and the impurity region 193S / D and the impurity region formed in the active regions on both sides thereof. (291S / D).

The floating gate 230 of the memory transistor 200 and the first gate 130 of the selection transistor 100 have different structures. The first gate 130 of the selection transistor 100 may be divided into a first portion 135 representing a structure similar to the floating gate 230 of the memory transistor 200 and a second portion 137 representing another structure. have. The first portion 135 of the first gate 130 is positioned adjacent to the memory transistor 200, that is, adjacent to the impurity region 193S / D. The second portion 137 of the first gate 130 is positioned adjacent to the bit line contact DC opposite to the memory transistor 200, that is, adjacent to the impurity region 191S / D.

3 to 9 will be described in more detail with respect to the selection transistor and the memory transistor according to an embodiment of the present invention.

FIG. 3 shows the isolation layer 40 and active in the box-shaped gate region 80 of the second region 20 to show a cross section of the second portion 137 of the first gate 130 of the select transistor 100. It is sectional drawing when it cuts in the direction passing through the area | region 50 (I-I 'line | wire) of FIG. FIG. 4 shows the isolation layer 40 in the 'ㅗ' shaped gate region 60 of the second region 20 to show a cross section of the first portion 135 of the first gate 130 of the select transistor 100. And a cross section taken in the direction passing through the active region 50 (line II-II 'of FIG. 2). FIG. 5 illustrates the isolation layer 40 in the butting contact region 70 of the second region 20 to show an electrical connection between the first gate 130 and the second gate 170 of the select transistor 100. And a cross section taken along the direction passing through the active region 30 (line III-III 'of FIG. 2).

Referring to FIG. 3, the second portion 137 of the first gate 130 of the selection transistor 100 has a box shape. However, referring to FIG. 4, the first portion 135 of the first gate 130 of the select transistor 100 may have an approximately 'ㅗ' shape. The first portion 135 of the first gate 130, for example, is continuous from the horizontal portion 131 and the horizontal portion 131 and extends above the substrate 30 and is narrower than the horizontal portion 131. It may be divided into a vertical portion 133. In this specification, in particular, the horizontal portion 131 of the floating gate of the memory transistor may be referred to as a lower conductive pattern, and the vertical portion 133 may be referred to as an upper conductive pattern. The first insulating layer 110 is positioned between the first gate 130 of the selection transistor 100 and the active region 50 of the substrate. Referring to FIG. 5, the first gate 130 and the second gate 170 are electrically connected to each other through a predetermined region (butting contact region) of the second insulating layer 150.

3 and 5, in the box-shaped gate region 80 of the second region 20, an upper surface of the device isolation layer 40 adjacent to the second portion 137 of the first gate 130 may have a first surface. It is substantially the same height as the top surface of the second portion 137 of the gate 130. That is, in the second region 20, the device isolation layer 40 covers most of the side surfaces of the second portion 137 of the first gate 130. However, referring to FIG. 4, the upper surface of the isolation layer 40 adjacent to the first portion 135 of the first gate 130 may be formed in the gate region 60 of the second region 20. The height is substantially the same as the upper surface of the horizontal portion 131 of the one part 135. The device isolation layer having a relatively high height in the box-type gate region 80 prevents the active region from being etched in the process of patterning the gate.

FIG. 6 is a direction through the device isolation layer 40 and the active region 50 in the first region 10 to show the cross section of the floating gate 230 of the memory transistor 200 (IV-IV ′ line of FIG. 2). It is sectional drawing when cut in). Referring to FIG. 6, the floating gate 230 of the memory transistor 200 has an approximately 'ㅗ' shape. For example, the floating gate 230 may be divided into a horizontal portion 231 and a vertical portion 233 continuous from the horizontal portion 231 and extending above the substrate 30 and narrower than the horizontal portion 231. Can be. The tunneling insulating layer 210 is positioned between the floating gate 230 and the active region 50. The floating gate 230 and the control gate 270 are insulated from each other by the gate insulating film 250 sandwiched therebetween. The upper surface of the isolation layer 40 adjacent to the floating gate 230 has a height substantially equal to the upper surface of the horizontal portion 231 of the floating gate 230.

In some embodiments, the height of the device isolation layer formed in the box-type gate region 80 of the second region 20 may be greater than that of the device isolation layer formed in the first region 10 and the 'ㅗ' -type gate region 60 of the second region. While maintaining higher than the height, the height of the device isolation layer may be variously changed. For example, the height of the isolation layer 40 in the first region 10 may be lower than the height of the active region 50 or higher than the upper surface of the horizontal portion 231 of the floating gate 230. May be

The first insulating layer 110 of the selection transistor and the tunneling insulating layer 210 of the memory transistor may be formed from the same layer. For example, the first insulating film 110 and the tunneling insulating film 210 may be formed of a silicon oxide film having a thickness of 20 to 200 Å, but are not limited thereto. The first insulating film 110 and the tunneling insulating film 210 may be formed of a metal insulating film having a high dielectric constant. The first gate 130 of the selection transistor and the floating gate 230 of the memory transistor may be formed from the same film. For example, the first gate 130 and the floating gate 230 may be formed of silicon. Similarly, the second gate 170 of the selection transistor and the control gate 270 of the memory transistor may be formed from the same film. For example, the second gate 170 and the control gate 270 may be formed of one of silicon, silicide, and gold attribute materials or a combination thereof. The second insulating film 150 of the selection transistor and the gate insulating film 250 of the memory transistor may be formed from the same film. For example, the second insulating film 150 and the gate insulating film 250 may be formed by sequentially depositing a silicon oxide film having a thickness of 30 to 80 GPa, a silicon nitride film having a thickness of 50 to 150 GPa, and a silicon oxide film having a thickness of 30 to 100 GPa. Can be.

7 and 8 are cross-sectional views of the memory transistor and the selection transistor when cut in the direction in which the active region 50 extends (V-V 'line of FIG. 2 and VI-VI' line of FIG. 2, respectively). 7 and 8, the selection transistor 100 includes an asymmetrical impurity region 191S / D and an impurity region 193S / D. Here, the impurity region is asymmetrical includes that the doping concentrations of the two impurity regions, the depth from the substrate surface, and the like are different from each other. The second portion 137 than the impurity region 193S / D adjacent to the first portion 135 of the first gate 130 of the select transistor 100, that is, the impurity region 193S / D adjacent to the memory transistor 200. ), The doping concentration of the impurity region 191S / D adjacent to (ie, the impurity region 191S / D adjacent to the drain contact DC) is relatively high and the junction depth is relatively deep.

Since the impurity region 193S / D adjacent to the memory transistor 200 has a relatively low doping concentration and a shallow junction depth, channel hot electrons generated in the channel region under the memory transistor 200 during a memory device operation are performed. Electron or gate-induced drain leakage current (GIDL) can be minimized. On the other hand, the impurity region 191S / D adjacent to the drain contact DC has a relatively high doping concentration and a deep junction depth, thereby minimizing the junction leakage current, thereby improving the breakdown voltage characteristic. In addition, a silicide film having good characteristics may be formed in the impurity region 191S / D adjacent to the drain contact DC.

In addition, the channel doping concentrations of the channel region under the first portion 135 and the second portion 137 of the first gate 130 of the selection transistor 100 may be different from each other. For example, the channel doping concentration under the first portion 135 of the first gate 130 is higher than the channel doping concentration under the second portion 137. This is because the second portion 137 has a box shape and is relatively thick, and thus the first portion 135 has a 'ㅗ' shape and has a relatively thin horizontal portion 131. It is possible to appropriately adjust the doping concentration of the channel region below (135). Since the channel doping concentration can be adjusted in this manner, it is possible to suppress the occurrence of punchthrough of the selection transistor 100 due to the high integration of the device. For example, the doping concentration may be increased by implanting impurity ions into the channel region beneath the thin horizontal portion 131 by an ion implantation process. Since the floating gate 230 of the memory transistor 200 also includes a horizontal portion 231, the doping concentration of the channel region can be easily adjusted through the horizontal portion 231 by an ion implantation process.

A memory transistor according to an exemplary embodiment of the present invention will be described in more detail with reference to FIGS. 9A, 9B, and 10. 9A schematically shows a cross section of the floating gate electrode when cut along the control gate extension direction (row), and FIG. 9B is a perspective view showing the arrangement of the floating gate electrode. In FIG. 9B, four floating gate electrodes are illustrated for convenience of description.

Referring to FIG. 9A, the floating gate electrode 230 according to the present exemplary embodiment includes a horizontal portion 231 and a vertical portion 233. In this embodiment, the horizontal portion 231 and the vertical portion 233 are formed from the same film quality. The vertical portion 233 protrudes from the upper surface of the horizontal portion 231. Width (w ₂₎ of the vertical portion 233 is smaller than the width (w ₁₎ of the horizontal portion 233, the thickness (h ₂₎ of the vertical portion 233 is a thickness (h ₁₎ of the horizontal portion 231 Greater than On the other hand, the cross-sectional area (S ₂ = w ₂ xh ₂ ) of the vertical portion 233 given by the product of the width (w ₂ ) and the thickness (h ₂ ) is horizontal given by the product of the width (w ₁ ) and the thickness (h ₁ ). It is larger than the cross-sectional area S ₁ = w ₁ xh ₁ of the portion 231.

The width w ₁ of the horizontal portion 231 may be formed to be as narrow as the photolithography process allows for a high integration semiconductor device. The thickness h ₁ of the horizontal portion 231 may be as thin as possible in order to minimize interference by horizontal portions adjacent to the row direction and / or horizontal portions adjacent to each other in the column direction. However, according to the present embodiment, the thickness h ₁ of the horizontal part 231 may be formed very thin because it depends on the thin film deposition process technology and the etching process. On the other hand, the width w ₂ of the vertical portion 233 may be narrowly formed to increase the distance between the vertical portions adjacent in the row direction. According to the present exemplary embodiment, the width w ₂ of the vertical portion 233 may be adjusted to a desired width by appropriately adjusting an etching condition, for example, an etching time. The cross-sectional area (S ₂ = w ₂ xh ₂ ) of the vertical portion 233 is larger than the cross-sectional area (S ₁ = w ₁ xh ₁ ) of the horizontal portion 231 and the width (w ₂ ) of the vertical portion 233. The width and thickness of the vertical portion 233 and the horizontal portion 231 are appropriately suited to satisfy the condition that the horizontal portion 231 is formed to be narrower than the width w ₁ . Can be set.

9B, effects and advantages of the floating gate electrode structure according to the present exemplary embodiment will be described. For the convenience of description, the four floating gate electrodes illustrated in FIG. 9B include the first floating gate electrode 230_1, the second floating gate electrode 230_2, the third floating gate electrode 230_3, and the fourth floating gate electrode ( 230_4). The first floating gate electrode 230_1 and the second floating gate electrode 230_2 are arranged in the first row, and the third floating gate electrode 230_3 and the fourth floating gate electrode 230_4 are arranged in the second row. The first floating gate electrode 230_1 and the third floating gate electrode 230_3 are arranged in the first column, and the second floating gate electrode 230_2 and the fourth floating gate electrode 230_4 are arranged in the second column.

First, interference by adjacent floating gate electrodes in the row direction will be described. According to the present exemplary embodiment, the cross section of the floating gate electrode includes a horizontal portion 231 and a vertical portion 233, for example, to form a “ㅗ” shape. Thus, the distance d ₃ between two vertical portions 233_1 and 233_2 of the first and second floating gate electrodes 230_1 and 230_2 adjacent in the row direction is the distance d between the two horizontal portions 231_1 and 231_2. _Since it increases to ₂ ), the interference between adjacent floating gate electrodes is reduced.

In addition, since the thickness h _{1 of the} horizontal portions can be made very thin, the overlapping area S ₃ between two adjacent horizontal portions 231_1 and 231_2 in the row direction is very small, although the distance d ₂ between them is small. Even close to the interference can be almost ignored. Meanwhile, two vertical portions 233_1 and 233_2 adjacent in the row direction have a large thickness h ₂ for a high coupling ratio, and a large overlapping area S ₄ is formed between the two vertical portions 233_1 and 233_2. However, since the distance d ₃ between the adjacent vertical portions 233_1 and 233_2 has increased, the interference does not increase. As described above, the thinner the width w _{2 of the} vertical portion is formed, the distance d ₃ between the two vertical portions 233_1 and 233_2 increases, thereby reducing the interference by adjacent vertical portions in the row direction.

The interference by adjacent floating gate electrodes in the column direction will now be discussed. Interference caused by the first floating gate electrode 230_1 and the third floating gate electrode 230_3 adjacent in the column direction may result in an opposing area S ₁ = w ₁ xh ₁ between the horizontal parts and an opposing area S ₂ between the vertical parts. = w ₂ xh ₂ ), depending on the sum S _TOTAL . Since the width w ₂ of the upper conductive pattern is formed narrow, the interference between adjacent floating gates in the column direction is reduced.

The shape of the floating gate electrode 230 described with reference to FIGS. 9A and 9B is merely illustrative for the purpose of describing the present invention, and there may be some form of variation in the manufacturing process. Accordingly, the shape of the floating gate electrode of the present embodiment should not be limited from the form schematically illustrated in FIGS. 9A and 9B and the description thereof, and should be understood to include allowable variations in the manufacturing process. For example, any film or element described as having a smooth surface may have a surface that is somewhat rugged than such a form. Likewise, any film or element described as having a flat surface may have a surface that is somewhat softer and rugged than its shape. In addition, any film or element described as having vertical sidewalls may have sidewalls that are somewhat inclined than such shapes. For example, although the surface of the floating gate electrode, ie, the horizontal portion and the vertical portion, is schematically illustrated in FIGS. 9A and 9B as being flat, it may have a somewhat smooth surface or a somewhat uneven surface. 9A and 9B, the side surfaces of the floating gate electrode, that is, the side portions of the horizontal portion and the vertical portion are shown to be vertical, but may be slightly inclined. For example, the width of the vertical portion may increase as it moves away from the substrate. In addition, the width of the horizontal portion may increase as the distance from the substrate.

An example of such various types of floating gate electrodes will be described with reference to FIG. 10. Referring to FIG. 10, the top surface of the horizontal portion 231 ′ of the floating gate electrode 230 ′ is inclined. The side surface of the vertical portion 233 'is not formed vertically but is formed to be inclined. The floating gate electrode as shown in FIG. 10 shows a somewhat crushed form from the shape of the floating gate electrode as shown in FIGS. 9A and 9B, but basically shows a "ㅗ" shape. The width w ₂ of the vertical portion described with reference to FIGS. 9A and 9B is such that the side of the vertical portion 233 'is inclined at the floating gate electrode 230' as shown in FIG. In the case of non-uniformity, it can be understood to indicate its maximum width (reference symbol w ₂ ′ in the figure). The width w ₁ of the horizontal portion described with reference to FIGS. 9A and 9B is such that the upper surface of the horizontal portion 231 'is inclined at the floating gate electrode 230' as shown in FIG. 10. In the case where the width becomes inconsistent, it may be understood to indicate the maximum width (reference symbol w ₁ ′ in the drawing).

As described above, the maximum width w ₁ ′ of the horizontal portion 231 ′ is larger than the maximum width w ₂ ′ of the vertical portion 233 ′, and the cross-sectional area S ₁ of the horizontal portion 231 ′ is vertical ( 233 ') is larger than the cross-sectional area S ₂ . The maximum width w ₁ ′ of the horizontal portion 231 ′ may be 1.5 to 2.5 times the minimum width w ₃ ′ of the vertical portion.

Various variations of the floating gate shape of the memory transistor described with reference to FIGS. 9A, 9B, and 10 may also appear in the first portion of the first gate of the selection transistor.

Hereinafter, a method of forming a NAND flash memory device according to an embodiment of the present invention will be described with reference to FIGS. 11 through 16. Referring to FIG. 11, the device isolation process is performed to define the active regions 500 by the device isolation layer pattern 400 extending in the column (y-axis) direction on the substrate 300 and on each of the active regions 500. The first insulating film 600 and the first conductive film pattern 700 are formed. The first conductive layer pattern 700 is formed on the active region 500 in a self-aligned manner by the device isolation layer pattern 400. Specifically, for example, an insulating film and a conductive film for the first insulating film 600 and the first conductive film pattern 700 are formed on the substrate 300. Some thicknesses of the conductive film, the insulating film, and the substrate are etched using a mask for defining the device isolation region. As a result, the active region 500 is defined in the substrate 300, and the first insulating layer 600 and the first conductive layer pattern 700 are formed on the active region 500 in a self-aligned manner. The isolation layer pattern 400 is formed by filling an insulating material in the region removed by etching. The method of forming the device isolation layer pattern 400 in the region removed by etching may be performed by performing a planarization process such as physicochemical polishing or etch back after performing an insulating material deposition process.

The first conductive layer pattern 700 is used as the first gate of the selection transistor and as the floating gate of the memory transistor. For example, the first conductive layer pattern 700 may be formed of silicon. The first insulating film 600 is used as a gate insulating film of a selection transistor and is used as a tunneling insulating film of a memory transistor. The first insulating film 600 may be formed of a silicon oxide film having a thickness of 20 to 200 microseconds, but is not limited thereto. It may be formed as.

Referring to FIG. 12, a mask 800 exposing a first region of the substrate 300 and simultaneously exposing a portion of a second region adjacent to the first region, that is, exposing a 'ㅗ' shaped gate region may be first. It is formed on the conductive film pattern 700 and the device isolation film 400. The mask 800 may be formed of a material having an etching selectivity with respect to the first conductive layer pattern 700 and the device isolation layer pattern 400, for example, silicon nitride. Here, the mask 800 exposes not only the first region but also a portion of the second region, so that the first portion of the first gate of the selection transistor formed in the second region has a 'ㅗ' shape.

Referring to FIG. 13, the thickness of the device isolation layer pattern 400 of the 'ㅗ' -type gate region, which is not protected by the mask 800, is removed so that its upper surface is lower than that of the first conductive layer pattern 700. The true device isolation layer pattern 410 is formed. The lower device isolation layer pattern 410 exposes the side surface of the first conductive layer pattern 700.

Referring to FIG. 14, the width of the first conductive layer pattern 700 protruding upward from the upper surface of the lowered isolation layer pattern 410 is etched in the lateral direction. The narrowed first conductive layer pattern portion 710 protruding above the lowered isolation layer pattern 410 is used as a vertical portion of the 'ㅗ' type gate. The first conductive pattern portion 730 covered by the device isolation layer pattern 410 lowered below the narrowed first conductive layer pattern 710 is used as a horizontal portion of the 'ㅗ' type gate. For example, wet etching using an etching solution may be used as the lateral etching of the first conductive layer pattern 700. In addition, dry etching using an etching gas may also be used. When wet etching is used, the etching solution contains NH ₄ OH.

Referring to FIG. 15, the mask 800 is removed to expose the device isolation layer pattern 400 and the first conductive layer pattern 700 of the box-shaped gate region of the second region.

Referring to FIGS. 16 and 17, after forming the second insulating film 900 and the second conductive film 1000, the gate extends in a row (x-axis) to define a control gate of the memory transistor and a second gate of the selection transistor. Masks 1100a and 1100b are formed.

Referring to FIG. 18, the second conductive layer 1000, the second insulating layer 900, and the first conductive layer pattern 700 are etched using the gate masks 1100a and 1100b as an etch mask, thereby stacking gates of a memory transistor. The structure and the stacked gate structure of the select transistor are formed. The gate stacked structure of the memory transistor includes a floating gate formed from a first conductive film pattern, a gate interlayer insulating film formed from a second insulating film, and a control gate formed from a second conductive film. The stacked gate structure of the selection transistor includes a first gate formed from the first conductive film pattern, a gate interlayer insulating film formed from the second insulating film, and a second gate formed from the second conductive film.

 According to the present embodiment, since the device isolation film 400 in the second region where the selection transistor is formed is relatively thicker than the lower device isolation film 410 in the first region where the memory transistor is formed, forming the stacked gate structure. It is possible to prevent the active region from being etched due to the loading effect in the second region during the etching process. For example, when the thickness of the device isolation layer is substantially the same in the first region and the second region, the substrate of the second region may be etched due to the loading effect in the etching process for forming the stack gate. Because memory transistors are densely formed in the first region and select transistors are relatively dense and sparse in the second region, the etching is relatively well performed in the second region and thus the substrate is damaged in the second region. You can get However, according to an exemplary embodiment of the present invention, the device isolation layer of the second region may be thicker than the device isolation layer, thereby preventing the substrate from being etched. That is, according to the present embodiment, the thick device isolation layer of the second region serves as an etch stop layer.

The electrical connection between the first gate and the second gate in the selection transistor may be made by butting contact or the like. For example, after the second insulating film 900 is formed, the second insulating film is patterned to expose the first conductive film in the second region where the memory transistor is to be formed, or the second insulating film is removed after the second insulating film is removed from the second region. do. Accordingly, the first gate and the second gate are electrically connected to each other.

The ion implantation process is performed to form source / drain regions for the memory transistor and the selection transistor. An ion implantation process may be selectively performed in the source / drain regions of the selection transistor adjacent to the drain contact. Additional ion implantation processes for the source / drain regions may use ion implantation processes for high concentration source / drain regions for transistors in the peripheral circuit region.

Hereinafter, the memory transistor will be described in more detail. 19 is a diagram illustrating a memory transistor of a flash memory device according to another embodiment of the present invention. Referring to FIG. 19, a plurality of device isolation layer patterns 120 may be disposed on the semiconductor substrate 100 to define the active region 102. The active region 102 is defined between adjacent device isolation patterns. The gate insulating layer 140 is formed on the active region 102, and the floating gate electrode 192 is disposed on the gate insulating layer 140. The floating gate electrode 192 includes a lower conductive pattern 155 and an upper conductive pattern 170. The width w ₁ of the lower conductive pattern 155 is wider than the width w ₂ of the upper conductive pattern 170. Accordingly, the cross section of the floating gate electrode 192 is an inverted phase (or "ㅗ" shape) of the letter "T" as shown. The gate insulating film pattern 194 and the control gate electrode 196 are disposed on the floating gate electrode 192. The control gate electrode 196 crosses the active region 102 and the device isolation layer pattern 120. The control gate electrode 196, the inter-gate insulating layer pattern 194, and the floating gate electrode 192 form a stacked gate structure 190 of the memory transistor.

The gate insulating film 140 is preferably a silicon oxide film having a thickness of 20 to 200 Å. A metal insulating film having a high dielectric constant may be used. The lower conductive pattern 155 may be polycrystalline silicon, and the upper conductive pattern 170 may be formed of one or a combination of polycrystalline silicon, silicide, and a metallic material. The gate insulating film pattern 194 may be a silicon oxide film having a thickness of 30 to 80 GPa, a silicon nitride film having a thickness of 50 to 150 GPa, and a silicon oxide film having a thickness of 30 to 100 GPa. The control gate electrode 196 may be formed of at least one of polycrystalline silicon, silicide, and a metallic material, or a combination thereof.

According to the present embodiment, the width w ₁ of the lower conductive pattern 155 is wider than the width of the top surface of the active region 102 or the width of the gate insulating layer 140. In addition, the upper surface of the device isolation layer pattern 120 between the adjacent lower conductive patterns 155 may be lower than the upper surface of the active region 102. Accordingly, the lower surface of the gate insulating layer pattern 194 or the control gate electrode 196 may also be lower than the upper surface of the active region 102 between adjacent lower conductive patterns 155. As such, when the control gate electrode 196 is lower than the upper surface of the active region 102, the opposing area between the control gate electrode 196 and the floating gate electrode 192 increases. In addition, the control gate electrode 196 may block interference between adjacent floating gate electrodes in the row direction, for example, capacitive coupling formed by adjacent gate electrodes.

The increase in the opposing area between the control gate electrode and the floating gate electrode increases the coupling ratio CR, which represents the efficiency with which the voltage applied to the control gate electrode 196 is transferred to the floating gate electrode 192. In addition, according to the present embodiment, the opposing area between the control gate electrode 196 and the floating gate electrode 192 is increased without increasing the height of the floating gate electrode 192 (eg, without increasing the cross-sectional area). Can be increased. As described above, according to the recessed structure of the upper surface of the device isolation layer pattern 120, the flash memory device of the present exemplary embodiment may have an increased opposing area.

In addition, since the cross section of the floating gate electrode 192 according to the present exemplary embodiment has a substantially '대략' shape, an opposing area between adjacent floating gate electrodes in the column direction is reduced. As shown, if the width and thickness of the lower conductive pattern 155 are w ₁ and h ₁ , respectively, and the width and thickness of the upper conductive pattern 170 are w ₂ and h ₂ , respectively, In comparison, the decreasing cross-sectional area of the 'ㅗ' shaped floating gate electrode 192 of the present invention is (w ₁ -w ₂ ) × h ₂ . The reduction of the cross-sectional area of the floating gate electrode leads to the reduction of the interference effect by the adjacent floating gate electrode in the column direction, and the reduction of the interference effect is a process margin that can increase the surface area of the floating gate electrode. ) Can be further provided, thereby increasing the coupling ratio. The floating gate electrode according to the present embodiment enables the increase of the surface area for determining the coupling ratio while maintaining the maximum cross-sectional area required for suppressing the interference effect.

According to the present embodiment, the cross-sectional area w ₁ x h1 of the lower conductive pattern 155 is at least twice the cross-sectional area w ₂ xh ₂ of the upper conductive pattern 170, and the width w1 of the lower conductive pattern 155 is provided. ) Is wider than the width w ₂ of the upper conductive pattern 170. A gate structure of a nonvolatile memory device according to various embodiments of the present disclosure will be described in more detail in connection with the following manufacturing methods.

20 schematically shows a flash memory device according to another embodiment of the present invention. Similar to the floating gate electrode of FIG. 19, the floating gate electrode 192 includes a lower conductive pattern 155 and an upper conductive pattern 170, and the width of the upper conductive pattern 170 is the width of the lower conductive pattern 155. Narrower than For example, the floating gate electrode 192 has a stepped side surface. However, in the nonvolatile memory device of the present exemplary embodiment, the floating gate electrode 192 is automatically aligned on the active region 102. For example, the width of the lower conductive pattern 155 of the floating gate electrode 192 is substantially the same as the width of the upper surface of the active region 102. For example, when two films deposited in a semiconductor manufacturing process are sequentially patterned using one etching mask, the two patterns formed may have substantially the same width. In addition, an upper surface of the isolation layer pattern 120 substantially coincides with an upper surface of the lower conductive pattern 155 of the floating gate electrode 192. In addition, in the present exemplary embodiment, the cross-sectional area of the upper conductive pattern 170 is larger than the cross-sectional area of the lower conductive pattern 155.

21 schematically shows a flash memory device according to another embodiment of the present invention. Unlike the flash memory device illustrated in FIG. 20, in the flash memory device of FIG. 20, a device isolation layer pattern 125 having a spacer shape is formed on side surfaces of the lower conductive pattern 155 and the gate insulating layer 140. The upper surface of the device isolation layer pattern 120 is lower than the upper surface of the active region 102.

22A to 22H are cross-sectional views illustrating a method of manufacturing a NAND flash memory according to an embodiment of the present invention. Referring to FIG. 22A, a trench mask pattern 110 is formed on a semiconductor substrate 100. The trench mask pattern 110 may include a pad oxide layer pattern 112 and a mask nitride layer pattern 114 that are sequentially stacked. The semiconductor substrate 100 is etched using the trench mask pattern 110 as an etching mask to form the trench 105 defining the active regions 102.

The trench mask pattern 110 may further include a silicon oxide layer (eg, a medium temperature oxide layer (MTO)) and an anti-reflection layer stacked on the mask nitride layer pattern 114. In addition, the types, thicknesses, and stacking order of the films constituting the trench mask pattern 110 may be variously modified. Forming the trench 105 may include anisotropically etching the semiconductor substrate 100 using an etch recipe having an etch selectivity with respect to the trench mask pattern 110. Although the sidewalls of the trench 105 are shown to be inclined in the drawing, the inner wall of the trench 105 may be vertically formed according to a process. In addition, a portion where the sidewalls and the bottom of the trench meet each other may exhibit a smooth curve.

Referring to FIG. 22B, after forming the isolation material for filling the trench 105, the trench 105 is etched by etching the isolation material for the device isolation until the upper surface of the trench mask pattern 110 is exposed. The device isolation layer pattern 120 surrounding the trench mask pattern 110 is formed while filling.

According to this embodiment, the insulating material for device isolation is preferably a silicon oxide film, a polycrystalline silicon film, an epitaxial silicon film and a porous insulating film may be used together. In addition, a thermal oxide film (not shown) may be formed on the inner wall of the trench 105 to etch damage caused during the etching of the semiconductor substrate 100 before forming the isolation material for device isolation. In addition, a liner layer may be further formed to block impurities from penetrating into the active regions 102. The liner film may be a silicon nitride film.

The etching of the isolation material for the device isolation may include a chemical mechanical polishing (CMP) process using a slurry having an etch selectivity with respect to the trench mask pattern 110, which may be a dry or wet front etch. May be used.

Referring to FIG. 22C, the trench mask pattern 110 is removed to form a gap region 130 exposing the top surface of the active region 102. In more detail, the forming of the gap region 130 may be performed by removing the mask nitride layer pattern 114 by using a wet etching recipe having an etching selectivity with respect to the device isolation layer pattern 120, and then forming the gap region 130 on the semiconductor substrate 100. Removing the pad oxide layer pattern 112 using a wet etch recipe having an etch selectivity with respect to it.

Meanwhile, the exposed sidewall of the device isolation layer pattern 120 may be etched to a predetermined thickness in the step of removing the pad oxide layer pattern 112. Accordingly, the width of the gap region 130 becomes wider than the width of the active region 102. According to the present exemplary embodiment, since the device isolation layer pattern 120 is made of the same material as the pad oxide layer pattern 112 (ie, the silicon oxide layer), the gap region 130 may be expanded without a separate process. In addition, the widening of the gap region 130 may not only allow the floating gate electrode of the nonvolatile memory to have an increased width, but also damage the gate insulating layer in a subsequent process of recessing the top surface of the device isolation layer pattern 120. This can be avoided, which can be seen from the description with reference to FIG. 20G.

The gate insulating layer 140 is formed on the exposed top surface of the active region 102. The gate insulating layer 140 is preferably a silicon oxide film formed through a thermal oxidation process. A metal insulating film having a high dielectric constant may be used. The gate insulating layer 140 may have a thickness of 20 to 200 μm.

Referring to FIG. 22D, after forming a conductive material for the lower conductive pattern of the floating gate to fill the extended gap region 130, the floating conductive material is etched until the upper surface of the device isolation layer pattern 120 is exposed. do. Accordingly, conductive gap fill patterns 150 may be formed on the active region 102 to fill the gap region 130. At this time, the width of the conductive gap fill pattern 150 is greater than the width of the active regions 102 due to the width expansion of the gap region 130 described above. As will be more clearly understood from the description to be made later, the width of the conductive gap fill pattern 150 determines the width of the floating gate electrode, so that the width of the floating gate electrode can be formed larger than the width of the active region.

The conductive gap fill pattern 150 filling the gap region 130 is preferably a polycrystalline silicon film formed through a chemical vapor deposition process. Forming the conductive gap fill pattern 150 may include planar etching using an etching recipe having an etch selectivity with respect to the device isolation layer pattern 120. For example, such planarization etching may use a chemical-mechanical polishing process, in which the slurry used may provide a large etching characteristic (ie, large etching selectivity) of the polycrystalline silicon with respect to the etching rate of the silicon oxide film. It is preferable that it is a substance.

Referring to FIG. 22E, the upper surface of the conductive gapfill pattern 150 is etched in the 'ㅗ' -type gate region by using an etching recipe having an etch selectivity with respect to the device isolation layer pattern 120, thereby lowering the gap region 130. A lower conductive pattern 155 remaining in the gap is formed. In this case, the depth at which the conductive gap fill pattern 150 is etched is smaller than the depth of the gap region 130. Accordingly, the lower conductive pattern 155 remains under the gap region 130, and the sidewalls of the device isolation layer pattern 120 are exposed. As a result, the thickness of the lower conductive pattern 155 (h ₁ of FIG. 19) is smaller than the depth of the gap region 130.

The mold layer 160 is conformally formed on the lower conductive pattern 155. The mold layer 160 is formed of a material having an etching selectivity with respect to the lower conductive pattern 155. For example, the mold layer 160 may be one of a silicon nitride film, a silicon oxynitride film, a silicon oxide film, and a metal nitride film. The stack thickness of the mold film 160 is preferably controlled precisely because it is a process parameter that determines the shape of the floating gate according to the present invention (as will be described in more detail below). To this end, the template film 160 may be low pressure chemical vapor deposition or atomic layer deposition techniques. In addition, since the etch depth of the conductive gapfill pattern 150 and the exposed sidewall height of the gap region 130 are process parameters that affect the shape of the floating gate, they are also preferably controlled precisely.

Referring to FIG. 22F, the mold layer 160 is anisotropically etched until the upper surface of the lower conductive pattern 155 is exposed. Accordingly, a mold spacer 165 is formed on the sidewall of the device isolation layer pattern 120 to cover the upper edge of the lower conductive pattern 155. Subsequently, after the upper conductive layer is formed on the entire surface of the resultant mold spacer 165, the upper conductive layer is etched until the upper surface of the device isolation layer pattern 120 is exposed. Accordingly, an upper conductive pattern 170 is formed between the mold spacers 165 to contact the lower conductive pattern 155. The pair of lower conductive patterns 155 and the upper conductive patterns 170 in contact with each other constitute the floating gate pattern 180 according to the present invention.

The cross-sectional shape of the floating gate pattern 180 is in the form of 'ㅗ' as shown. The cross-sectional shape of the floating gate pattern 180 is determined by the height and width of the lower conductive pattern 155 and the height and width of the upper conductive pattern 170. Accordingly, as described above, 1) the height difference between the device isolation layer pattern 120 and the upper surfaces of the active region 102, 2) the width of the gap region 130, and 3) the stack of the mold layer 160. The thickness and 4) the etching depth of the upper conductive film may be precisely controlled.

As described above, since the upper conductive pattern 170 is formed using the mold spacer 165 as a mold, the upper conductive pattern 170 is automatically aligned with the center of the lower conductive pattern 155. Further, according to the present invention, the lower conductive pattern 155 may have a thickness sufficient to prevent the problem of exposing the active region 102 in an etching process for separating the control gate electrode and the floating gate electrode in the active region extension direction. Have For example, the thickness of the lower conductive pattern 155 may be at least thicker than the width of the upper conductive pattern 170.

Meanwhile, the upper conductive film for the upper conductive pattern 170 may be one of polycrystalline silicon film, silicide film, and metal film, or a combination thereof, and may be formed by chemical vapor deposition and epitaxial growth. In addition, the etching of the upper conductive layer may use a chemical-mechanical polishing technique, wherein the slurry used may have an etching selectivity with respect to the device isolation layer pattern 120 or the mold spacer 165.

Referring to FIG. 22G, the exposed upper surface of the device isolation layer pattern 120 is etched using the upper conductive pattern 170 and the lower conductive pattern 155 as an etching mask. According to the present exemplary embodiment, the upper surface of the device isolation layer pattern 120 is recessed through this etching process to lower the upper surface of the active region 102 between the adjacent lower conductive patterns 155 (as shown).

According to this embodiment, the mold spacer 165 may be removed while the device isolation layer pattern 120 is recessed. Accordingly, as illustrated, the upper surface of the lower conductive pattern 155 is exposed except for the region in contact with the upper conductive pattern 170. Here, the mold spacer 165 may be removed through an additional process.

Meanwhile, since the width of the lower conductive pattern 155 is wider than the width of the active region 102 thereunder, the etching of the active region 102 and the gate insulating layer 140 is performed in the recessing of the device isolation layer pattern 120. Damage can be prevented. Considering that the step of recessing the device isolation layer pattern 120 is performed until the upper surface of the device isolation layer pattern 120 is lower than the upper surface of the active region 102, this preventive effect is obvious. As described above, in order to prevent such etching damage, a process of extending the width of the gap region 130 is required.

Referring to FIG. 22H, a stacked gate structure 190 is formed on a result of the recessed top surface of the device isolation layer pattern 120. The stacked gate structure 190 includes a floating gate electrode 192, a gate insulating film pattern 194, and a control gate electrode 196 that are sequentially stacked.

In the forming of the stacked gate structure 190, a gate insulating film and a control gate conductive film are sequentially formed on the entire surface of the recessed upper surface of the device isolation layer pattern 120, and then the control gate conductive film, the gate insulating film, and Patterning the floating gate pattern 180. As a result, the control gate electrode 196 is formed to cross the adjacent active region 102 and the device isolation layer pattern 120, and the adjacent floating gate electrodes 192 are electrically separated from each other in the extending direction of the active region. The gate insulating film pattern 194 may be a silicon oxide film having a thickness of 30 to 80 GPa, a silicon nitride film having a thickness of 50 to 150 GPa, and a silicon oxide film having a thickness of 30 to 100 GPa.

In the above-described embodiment, the portion 165r of the mold spacer 165 may not be removed, which will be described with reference to FIGS. 23A and 23B. The mold spacer 165r that is not removed as described above removes the possibility of the lower conductive pattern 155 being etched in the etching process for the stacked gate structure. After the process is performed with reference to FIGS. 22A to 22F, the exposed upper surface of the device isolation layer pattern 120 is etched using the upper conductive pattern 170 and the lower conductive pattern 155 as an etching mask. A portion of the mold spacer 165 is then removed to form the mold spacer 165r remaining on the lower conductive pattern 155 as shown in FIG. 23A. Referring to FIG. 23B, after forming the gate insulating film and the conductive film for the control gate electrode, the word line 190 is formed by patterning the conductive film for the control gate electrode, the gate insulating film, and the floating gate pattern 180. Form. At this time, the remaining mold spacer 165r prevents the lower conductive pattern 155 from being etched.

According to the above embodiments, the floating gate electrode 192 is formed of a lower conductive pattern 155 and an upper conductive pattern 170 formed through separate processes. However, the upper conductive pattern 170 and the lower conductive pattern 155 may be formed of a single conductive film or the same film quality as shown in FIGS. 24A and 24B.

In the present exemplary embodiment, a mask pattern for defining the upper conductive pattern 170 may be formed on the conductive gap fill pattern (see 150 of FIG. 22D) of the exemplary embodiment described with reference to FIGS. 22A through 22D without any separate process for forming the upper conductive layer. 200). The mask pattern 200 may be formed in a 'ㅗ' type gate region. After the processes described with reference to FIGS. 22A through 22D are performed, a mask pattern 200 is formed on the conductive gap fill pattern 150. Using the mask pattern 200 as an etching mask, the conductive gap fill pattern 150 is etched to a predetermined depth as shown in FIG. 24A to form the lower conductive pattern 155 and the upper conductive pattern 170. The lower and upper conductive patterns 155 and 170 formed as described above have the same structure as the above-described embodiments except that they are formed of a single layer.

The mask pattern 200 is preferably a photoresist pattern formed using a photo process, and includes various material films (eg, silicon nitride film, silicon oxide film, and silicon oxynitride film) having etch selectivity with respect to the conductive gap fill pattern 150. Etc.). Meanwhile, considering that the mask pattern 200 defines the upper conductive pattern 170, the mask pattern 200 has a narrower width than the lower conductive pattern 155. In order to realize such a small width, the forming of the mask pattern 200 may use a method of forming a sacrificial pattern having a predetermined width on the gap fill pattern 150 and then reducing the width by isotropically etching it. have.

As shown in FIG. 24B, the mask pattern 200 is removed to expose the top surface of the floating gate pattern 180. The process after removing the mask pattern 200 is the same as the above-described embodiments.

In example embodiments, the device isolation layer pattern is formed before the floating gate pattern. In contrast, the embodiments to be described with reference to FIGS. 25A to 25E and 26A to 26B are distinguished from the previous embodiments in that the floating gate pattern is formed before the device isolation layer patterns. On the other hand, in order to avoid duplicate description, the description of the above embodiments will be omitted.

Referring to FIG. 25A, a gate insulating layer 140, a floating gate pattern 210, and a trench mask pattern 110 that are sequentially stacked on a predetermined region of the semiconductor substrate 100 are formed. The semiconductor substrate 100 is etched using the trench mask pattern 110 as an etching mask to form the trench 105 defining the active region 102. Subsequently, the isolation layer 119 filling the trench 105 is formed on the resultant product on which the trench 105 is formed.

Referring to FIG. 25B, the device isolation layer 119 is etched until the sidewall of the trench mask pattern 110 is exposed, thereby forming the device isolation layer pattern 120 filling the trench 105. Forming the device isolation layer pattern 120 may planarize etching the device isolation layer 119 until the trench mask pattern 110 is exposed, and thereafter, the device isolation layer pattern 120 may be approximately equal to an upper surface of the floating gate pattern 210. And etching the upper surface of the separator pattern 120.

Referring to FIG. 25C, the exposed trench mask pattern 110 isotropically etched to form a mask pattern 115 having a width smaller than that of the floating gate pattern 210. In the forming of the mask patterns 115, a method of wet etching having etch selectivity with respect to the device isolation layer patterns 120 and the floating gate pattern 210 may be used. In this case, the mask pattern 115 is automatically aligned with the top of the floating gate pattern 210, and the top edges of the floating gate patterns 210 are exposed.

 Referring to FIG. 25D, the exposed top surface of the floating gate pattern 210 is etched to a predetermined depth using the mask pattern 115. This process is the same as the embodiment described above with reference to FIG. 5A. As a result, the etched floating gate pattern 180 has a reverse phase cross section of a 'T' having a narrow width of the upper conductive pattern 170 compared to the lower conductive pattern 155. Thereafter, the exposed top surfaces of the device isolation layer patterns 120 are recessed to the height of the top surface of the gate insulating layer 140.

 Referring to FIG. 25E, a gate insulating film and a control gate conductive film covering the upper surface of the floating gate pattern 180 are formed. Thereafter, these are patterned to form a word line 190 across the active region 102. Forming the word line 190 is the same as the embodiments described above.

25A to 25E, the spacers are formed on the sidewalls of the trench mask pattern 110 and are recessed on the top surface of the device isolation layer pattern 120 after the steps described with reference to FIG. 25B. An area may be formed and an example thereof will be described with reference to FIGS. 26A and 26B. In this case, since the shape of the spacer is transferred to the device isolation layer pattern 120, the device isolation layer pattern 120 may be formed lower than the top surface of the active region 102 without exposing the gate insulating layer 140.

Referring to FIGS. 26A and 26B, the step of recessing the device isolation layer pattern 120 (see FIG. 23D) may be performed to a depth where the gate insulating layer 140 is not exposed. Subsequently, after forming the spacer insulating film 220 conformally forming the floating gate pattern 180 on the resultant product, the spacer insulating film 220 is anisotropic until the upper surface of the upper conductive pattern 170 is exposed. Etch it. In this case, the spacer insulating layer 220 may be at least one selected from a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a metal nitride film.

Accordingly, the buffer insulating layer pattern 230 is formed on the lower conductive pattern 155, and the buffer spacer 240 is formed on the sidewall of the lower conductive pattern 155. A gate insulating film and a control gate conductive film are formed on the resulting buffer insulating film pattern 230 and the buffer spacer 240. In this case, the device isolation layer pattern 120 is recessed to have a lower upper surface than the floating gate pattern 180 between the buffer spacers 240. Thereafter, they are patterned to form a word line 190 across the active regions 102. Forming the word line 190 is the same as the embodiments described above. As a result, the buffer insulating layer pattern 230 is interposed between the upper surface of the lower conductive pattern 155 and the lower surface of the gate insulating layer pattern 194.

27A through 27E are diagrams for describing a floating gate forming method of a flash memory device, according to another exemplary embodiment. Referring to FIG. 27A, a gate insulating layer 140, a floating gate pattern 210, and a mask pattern 110 are formed on the semiconductor substrate 100, and a trench 105 for device isolation is formed. The substrate 100 under the floating gate pattern 210 becomes the active region 102. In more detail, a thin film deposition process may be performed to form a gate insulating film and a floating gate conductive film, for example, about 50 to 100 angstroms thick on the substrate 100, and the trench 105 may be formed on the conductive film for the floating gate. To form a mask pattern 110 defining a. Using the mask pattern 110 as an etching mask, the floating gate conductive film, the gate insulating film, and a portion of the substrate are etched to form the floating gate pattern 210, the gate insulating film pattern 140, and the active region 102. do. That is, the gate insulating layer pattern 140 and the floating gate pattern 210 are formed on the active region 102 in a self-aligned manner. Here, a trench 105 exposing side surfaces of the floating gate pattern 210, the gate insulating layer pattern 140, and the active region 102 is defined.

For example, the floating gate pattern 210 may be formed of polysilicon, and the thickness of the floating gate pattern 210 may be formed to an appropriate thickness in consideration of a coupling ratio and interference. The mask pattern 110 may be formed of a material having an etching selectivity with respect to silicon and an oxide layer, for example, a silicon nitride layer.

Referring to FIG. 27B, the mask pattern 110 is formed to fill the trench 105 for device isolation, for example, to cover side surfaces of the active region 102, the gate insulating layer pattern 140, and the floating gate pattern 210. After forming the device isolation insulating film on the ()) to form a device isolation film 115 by performing an etching process for the device isolation insulating film until the mask pattern 110 is exposed. The etching process for the insulating film for device isolation may use, for example, a chemical mechanical polishing process or an etch back process.

The upper surface of the floating gate pattern 210 is exposed by removing the exposed mask pattern 110 with reference to FIG. 27C. Since the mask pattern 110 is formed of a material having an etching selectivity with respect to the floating gate pattern 210 and the device isolation layer 115, the mask pattern 110 may be selectively removed.

Referring to FIG. 27D, a portion of the device isolation layer 115 is etched so that the side surface of the floating gate pattern 210 is exposed in the gate region. As a result, the device isolation layer pattern 120 having the upper surface lower than the upper surface of the floating gate pattern 210 is formed. The floating gate pattern 210 may be divided into a portion 155 (hereinafter referred to as a 'lower pattern portion') and an uncovered portion 130 (hereinafter referred to as an 'top pattern portion') covered by the device isolation layer pattern 120. have. The lower pattern portion 155 of the floating gate pattern 210 covered by the device isolation layer pattern 120 becomes the lower conductive pattern 155 of the floating gate electrode. The upper pattern portion 130 exposed by the etching of the device isolation layer 115 among the floating gate patterns 210 is used for the upper conductive pattern of the floating gate electrode.

In this case, the order of removing the mask pattern 110 and removing a part of the device isolation layer 115 is not important, and it may be any of the first.

Referring to FIG. 27E, the upper pattern portion 130 of the floating gate pattern 210 protruding above the upper surface of the device isolation layer pattern 120 is etched to form the upper conductive pattern 170 of the floating gate electrode. Here, the upper conductive pattern 170 having a width w ₂ narrower than the width w ₁ of the upper pattern portion 130, that is, having a width narrower than the width w ₁ of the lower conductive pattern 155 is formed. Is formed. As a result, the floating gate pattern 180 having the lower conductive pattern 155 and the upper conductive pattern 170 narrower than the lower conductive pattern 155 is formed. For etching the upper pattern portion 130, for example, wet etching using an etching solution may be used. In addition, dry etching using an etching gas may also be used. When wet etching is used, the etching solution contains NH ₄ OH. When using the etching solution, the upper surface as well as the side of the upper pattern portion 130 may be etched. Therefore, the thickness of the initial floating gate pattern 210 is determined in consideration of the upper surface etching of the upper pattern portion 130.

Meanwhile, the side surface of the lower conductive pattern 155 is covered by the device isolation layer pattern 120 to be protected from etching, but depending on the process, the edge of the upper surface may be etched to some extent. In addition, depending on the process, the side surface of the upper conductive pattern 170 may be a vertical, inclined, flat surface, or somewhat uneven surface. In addition, the lower conductive pattern 155 and the upper conductive pattern 170 may have a smooth curved shape where the lower conductive pattern 155 and the upper conductive pattern 170 meet each other.

After forming the insulating layer for the gate insulating film and the conductive layer for the control gate electrode, the control gate conductive film, the gate insulating film and the floating gate pattern 182 are patterned to form a floating gate electrode 192 separated in units of cells. Next, the control gate electrode 194 is formed. The control gate electrode 196 is formed to cross the device isolation layer pattern 120 and the active region 102, and the floating gate electrode 192 is positioned at the intersection of the control gate electrode 196 and the active region 102. .

According to the method described with reference to FIGS. 27A to 27E described above, the floating gate electrode is self-aligned on the active region. For example, the width of the lower conductive pattern of the floating gate electrode is formed to be substantially the same as that of the active region.

In the above-described method described with reference to FIGS. 27A through 27E, after forming the trench 105 and before forming the device isolation layer, thermal oxidation may be performed to heal damage of the etching process for forming the trench. In this case, thermal oxidation may also proceed at the edge of the active region 102 such that the gate insulating film at the edge of the active region 102 may be formed relatively thicker than in other regions.

In the method described with reference to FIGS. 27A to 27E, the upper surface of the upper pattern portion 130 of the floating gate pattern 210 may be prevented from being etched. One method for this may include adjusting the order of the removal process of the mask pattern 110 and the etching process of the device isolation layer 115 in the above-described method. For example, an etching process may be performed on the upper pattern portion 130 of the floating gate pattern 210 without removing the mask pattern 110 from the upper surface of the floating gate pattern 210. This will be described with reference to FIGS. 28A to 28C.

The floating gate pattern 210, the gate insulating layer 140, the mask pattern 110, and the device isolation layer 115 are formed by performing the processes described with reference to FIGS. 27A through 27B. Referring to FIG. 28A, a portion of the isolation layer 115 is etched so that the side surface of the floating gate pattern 210 is exposed in the 'ㅗ' -type gate region, thereby forming a device having a lower top surface or a lower top surface of the floating gate pattern 210. The separator pattern 120 is formed. Here, the upper surface of the floating gate pattern 210 is covered by the mask pattern 110.

Referring to FIG. 28B, the side surface of the upper pattern portion 130 of the exposed floating gate pattern 210 is etched to reduce its width to form the upper conductive pattern 170. In the present exemplary embodiment, unlike the method described with reference to FIGS. 27 to 27E, the upper surface of the upper pattern portion 130 is not etched.

Referring to FIG. 28C, the mask pattern 110 is removed. In the case of the method described with reference to FIGS. 27A to 27E, etching may be performed on the upper surface of the upper pattern part, so that an edge of the upper surface of the upper conductive pattern may be formed in a somewhat smooth curved shape. Since the etching of the upper surface of the negative portion is not performed, the edge of the upper surface of the upper conductive pattern may be formed slightly angled than the upper conductive pattern by the method described with reference to FIGS. 27A to 27E.

According to the present invention, a cross section of the gate of the selection transistor has a box shape and a 'ㅗ' shape. Therefore, it is possible to implement a selection transistor having improved punch-through characteristics and leakage current characteristics.

According to the present invention, when the floating gate of the memory transistor is formed in a 'ㅗ' shape, a part of the gate of the selection transistor is also formed in a 'ㅗ' shape, so that the active transistor is formed in the region where the selection transistor is formed in the patterning process for the control gate. The area can be prevented from being etched.

According to the present invention, the cross section of the floating gate electrode is made inverted in the 'T' shape. Accordingly, since the cross-sectional area of the floating gate electrode can be reduced, the interference effect of adjacent word lines can be minimized. Since the reduction of the interference effect creates a process margin that can increase the surface area of the floating gate electrode, the floating gate electrode according to the present invention can increase the coupling ratio without increasing the interference effect. As a result, the nonvolatile memory device according to the present invention can overcome the problem of reduction of electrical interference and coupling ratio due to high integration.

According to the present invention, the cross section of the floating gate electrode exhibits a 'T' reversed phase to increase the distance between the upper conductive patterns of adjacent floating gate electrodes in the control gate extension direction, and to the adjacent floating gate electrodes in the control gate extension direction. Can reduce interference.

Other features, advantages, or effects of the present invention will be apparent from the accompanying drawings and the related embodiments.

So far I looked at the center of the preferred embodiment (s) for the present invention. Those skilled in the art will appreciate that the present invention can be implemented in a modified form without departing from the essential features of the present invention. Therefore, the disclosed embodiments should be considered in descriptive sense only and not for purposes of limitation. The scope of the present invention is shown not in the above description but in the claims, and all differences within the equivalent range will be construed as being included in the present invention.

Claims (20)

A first gate formed on the active region of the substrate defined by the device isolation layer patterns; A first insulating film formed between the first gate and the active region; And, A first impurity region and a second impurity region formed in the active regions on both sides of the first gate, The cross-sectional shape of the first portion of the first gate adjacent to the first impurity region and the cross-sectional shape of the second portion of the first gate adjacent to the second impurity region are different from each other. The method according to claim 1, When cut in a direction passing through the active region and the device isolation patterns, the cross-section of the first portion of the first gate is in a 'ㅗ' shape, and the second portion of the first gate is in a box shape. The method according to claim 2, And the concentration of the first impurity region is lower than that of the second impurity region. The method according to claim 2, And a channel doping concentration of the substrate under the first portion of the first gate is higher than a channel doping concentration of the substrate under the second portion of the first gate. The method according to claim 2, A second insulating film formed on the first gate; A second gate electrically connected to the first gate through the second insulating film; And, And a memory gate including a tunneling insulating layer, a floating gate, an inter-gate insulating layer, and a control gate, which are sequentially formed on the active region away from the first gate. The method according to claim 5, And a cross section of the first gate having a '절단' shape when cut in a direction passing through the active region and the device isolation patterns. The method according to claim 6, The height of the device isolation layer pattern adjacent to the floating gate of the memory gate relative to the substrate surface is lower than the height of the device isolation layer pattern adjacent to the first gate. The method according to claim 6, The first gate and the floating gate are formed from the same film, The insulating film between the second insulating film and the gate is formed from the same film, And the second gate and the control gate are formed from the same film. The method according to claim 6, And a top surface of the device isolation layer pattern adjacent to the floating gate has the same height as a top surface of the horizontal portion '-' of the floating gate having a 'ㅗ' shape. A selection transistor formed on the active region of the substrate defined by the device isolation layer patterns; And A plurality of memory transistors formed on the active region and connected in series with the selection transistor, Each of the selection transistor and the plurality of memory transistors includes a stacked gate structure including a first insulating film, a first gate, a second insulating film, and a second gate, which are sequentially formed on the active region, The cross section of the first gate of the memory transistor and the cross section of the first portion of the first gate of the select transistor adjacent to the memory transistor exhibit the same shape, and the second portion of the first gate of the select transistor opposite the memory transistor. And a cross-sectional shape of the first portion of the first gate of the selection transistor is different from each other. The method according to claim 10, When cut in the direction passing through the active region and the device isolation layer patterns, a cross-section of the first gate of the memory transistor is in a 'ㅗ' shape, and a second portion of the first gate of the selection transistor is in a box shape. . The method according to claim 11, The height of the device isolation layer pattern adjacent to the first gate of the memory transistor based on the substrate surface is lower than the height of the device isolation layer pattern adjacent to the first gate of the selection transistor. The method according to claim 11, And a top surface of the device isolation layer pattern adjacent to the first gate of the memory transistor has the same height as a top surface of the horizontal portion '−' of the first gate having a 'ㅗ' shape of the memory transistor. The method according to claim 11, And a concentration of an impurity region adjacent to a first portion of the first gate of the selection transistor is lower than a concentration of an impurity region adjacent to the second portion of the first gate of the selection transistor. The method according to claim 11, And a channel doping concentration of the substrate under the first portion of the first gate of the selection transistor is higher than the channel doping concentration of the substrate under the second portion of the first gate of the selection transistor. Forming a first insulating film and a first conductive film pattern on an active region of the substrate defined by the device isolation film patterns; Etching lower portions of the device isolation layer patterns to form lowered device isolation layer patterns covering side surfaces of the lower pattern portion of the first conductive layer pattern; Etching the upper pattern portion of the first conductive layer pattern protruding upward from the lower surface of the lower device isolation layer patterns in a lateral direction to form a narrowed upper pattern portion narrower than the lower pattern portion of the first conductive layer pattern;  Patterning a first conductive layer pattern having the lower pattern portion and the narrowed upper pattern portion to form a first portion patterned from the lower pattern portion and the upper pattern portion and a first conductive layer adjacent to the device isolation layer patterns; Forming a first gate having two portions; And, Forming a first impurity region and a second impurity region adjacent to the first and second portions of the first gate, respectively. The method according to claim 16, Before forming the first gate, forming a second insulating film on the first conductive film pattern having the lower pattern portion and the narrowed upper pattern portion; And, And forming a second conductive film through the second insulating film on the first gate to be electrically connected to the first conductive film.  And patterning the first conductive film to form a second gate from the second conductive film electrically connected to the first gate by patterning the second conductive film and the second insulating film. The method according to claim 17, When the second conductive layer, the second insulating layer, and the first conductive layer are patterned to form a second gate electrically connected to the first gate and the first gate, A floating gate having a cross-sectional shape in a 'ㅗ' shape from the lower pattern portion and the upper pattern portion of the first conductive layer on the active region away from the first gate, from the second insulating layer to the gate insulating layer and the second conductive layer; And forming a gate. Forming a first insulating film and a first conductive film pattern on an active region of the substrate defined by device isolation film patterns extending in a first direction; Etching the device isolation layer patterns of the first region in which the memory transistor of the substrate is to be formed in a downward direction to form lower device isolation layer patterns covering the side surface of the lower pattern portion of the first conductive layer pattern; Etching the upper pattern portion of the first conductive layer pattern protruding upward from the lower surface of the lower device isolation layer patterns in a lateral direction to form a narrowed upper pattern portion narrower than the lower pattern portion of the first conductive layer pattern; Forming a second insulating film and a second conductive film on the device isolation layer patterns, the lower device isolation layer patterns, and the first conductive layer pattern; And, Patterning the second conductive layer, the second insulating layer, and the first conductive layer to extend the active region and the lowered device isolation layer in the first region in a second direction crossing the first direction from the second conductive layer; NAND comprising forming a control gate of the memory transistor passing through the patterns, an insulating film between the gate of the memory transistor from the second insulating film and a floating gate of the memory transistor from the lower pattern portion and the upper pattern portion of the first conductive film pattern. How to form a flash memory device. The method according to claim 19, Etching the device isolation layer patterns in the first region in which the memory transistors of the substrate are to be formed downwardly includes etching the device isolation layer patterns adjacent to a portion of the second region in which the selection transistors of the substrate are to be formed in a downward direction. To; Patterning the second conductive layer, the second insulating layer, and the first conductive layer may include: lowered device isolation layer patterns, device isolation layer patterns, and active regions extending in the second direction in the second region; And forming a first gate of the select transistor in an active region overlapping the second gate and the second gate of the select transistor passing through the second gate.

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