TWI300608B - Semiconductor device and method for forming the same - Google Patents

Description

1300608 IX. Description of the Invention: TECHNICAL FIELD The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a non-volatile memory device and a method of fabricating the same. [Prior Art] In general, a semiconductor memory device is classified into a volatile memory device and a nonvolatile memory device depending on whether or not it is required to supply power to retain the stored data. Volatile memory devices, such as Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM), have a fast speed of survival, but have the limitation of requiring power to retain data. Conversely, since non-volatile memory devices (such as flash memory devices) do not have this limitation, they are widely used in portable electronic devices where demand has increased in recent years. The ox, lyo, flash memory device includes a cell for storing data and a related device such as a selective transistor, a driving transistor or the like. The memory cells of the flash memory device mainly use a memory transistor similar to a typical transistor.鲈槿万徜 (10) The body of the electric body consists of a gate stack. The stacking structure on both sides of the gate stack structure is used to successively stack the upper edge of the L-gate layer and the floating-channel area. Can &quot; ' ° ^ interlayer insulation layer and - control gate to give one. (4) The floating one of the memory transistor: the main and the latch: 〆, 1 is electrically insulated, and each of the sub-gates is a memory of the memory transistor + a plurality of memories arranged in the direction The idleness is broken and connected to each other as a word line. According to the layout of the memory transistor with the above structure of H2311.doc 1300608, the flash memory device can be mainly classified into a NAND type flash memory device and a type of earning flash memory. Body device. For NAND type flash memory cleaving, a selection transistor is connected to the memory transistor, and for example, the gates of the selection transistors arranged in the column direction are connected to each other to thereby form a selection line. At the same time, in order to reduce the price of semiconductor devices, it is necessary to increase the degree of integration, which causes several technical difficulties in manufacturing semiconductor devices. In particular, with highly integrated semiconductor devices, the spacing between adjacent word lines is also shortened, which makes it difficult to improve the structure and characteristics of non-volatile memory devices: for example, although operating efficiently The non-volatile memory device having the control of the idle electrode and the oceanic gate electrode should have a high coupling ratio, but the shortening of the interval between the word lines makes it difficult to ensure this high coupling ratio. In addition, since the word line width and the interval between adjacent word lines are smaller than the selection line width and the interval between the selection line and the word line, the substrate active area where the selection line is to be formed may be attributed to The load effect (1〇ading effect) is damaged by etching. As the degree of integration of the memory device is increased, the channel length of the selected transistor is also reduced, which causes a short channel effect. For example, since the channel exchange concentration in the edge of the channel region is relatively higher than the channel doping concentration in the central portion, pJnchthrough is apt to occur. In addition, it is highly probable that punch-through occurs at the memory transistor adjacent to the selected transistor. [Description of the Invention] 1123H.doc 1300608 In the fourth embodiment of the present invention, the apparatus for extracting conductors includes: Ϊ::: on an active area of a substrate, wherein the active area is defined by a second pattern; a first insulating layer formed between the f-closed electrode and the active region; and the first and second impurity regions are formed on the active region on both sides of the (four)-idal pole to be adjacent to the a cross section of the second portion of the first gate electrode in the second impurity region: in the device isolation layer of the present invention, and the like; The first portion of the first gate is two: an inverted-T-shaped profile and the second portion of the first opening has a phase profile. In a specific embodiment, the present invention provides a m flash flash 1 m electret crystal formed on a substrate - wherein the action (4) is bounded by a device isolation layer pattern and a plurality of memory transistors, Formed on the active area, the:::solid memory electro-optic system is operatively connected in series to the selective transistor: two a-selective transistor and each of the plurality of memory transistors - (10) body stack structure The stacked closed-pole structure is configured by a first-insulation layer, a first-gate, and a second-second two-pole on the second region, wherein the memory transistor is a first, The surface shape of the ^1 is substantially the same as the cross-sectional shape of the first portion of the first opening electrode of the two transistors adjacent to the memory transistor, and the "selective transistor of the opposite side of the memory cell" The first gate 112311.doc 1300608 has a second portion having a different cross-sectional shape than the first portion. The first gate of X, the day-day is in the method of the present invention, and the method of manufacturing the semi-inductive layer and the plate is formed on the active region of the device. -Meng Fan [Guide layer pattern, in which the action area is transmitted by the device isolation layer, and only the middle part of the person is used for the hunting case - to form: the second layer of the device isolating the isolation layer map of the device荦t 兮篦 兮篦 / device isolation layer pattern, the lower device day q case covers one of the lower surface of the first conductive pattern; the remaining one of the first conductive layer pattern. One side is formed - narrowed above (four) 帛The side surface of the material (4) is shaped by the shape of the shape ρ, which is narrower than the width of the upper lower pattern, wherein the width of the first upper pattern is smaller than the width of the first upper pattern. Protruding and higher than the lower device isolation layer pattern; the pattern, the "lower pattern and the first conductive pattern of the narrowed upper pattern" to form a first gate having a first portion of eight knives and a second portion Extremely, the younger brother "" 仗 5 Hai lower pattern and pattern from the upper pattern: and a second a portion is patterned from the first layer of the isolation layer pattern adjacent to the device; and a first impurity region and a second impurity are formed adjacent to the first portion of the first gate and In a second embodiment of the present invention, the present invention provides a method for fabricating a D-flash memory device, the method comprising: forming a first insulating layer and a region on a substrate: an active region a first conductive layer pattern, wherein the region is defined by a device isolation layer pattern extending in a first direction; the substrate is etched down to form a memory transistor portion 112311.doc 1300608A The layer is separated from the layer to form a lower device isolation layer. The lower portion of the first pattern is covered with one of the lower patterns of the first conductive pattern; ^. a, etch the The upper pattern of one of the first conductive layer patterns is also narrowed to the upper pattern, and the narrowed upper portion has a smaller visibility than the first value of the lower pattern of the first search pattern, wherein the first conductive pattern The pattern of the 4 Projecting a higher than the lower device isolation 曰 pattern; forming a second insulating layer and a second conductive layer on the device/disposing layer pattern, the lower device isolation layer pattern, and the Φ^ conductive layer pattern; Layering and patterning the second conductive layer, the second insulating layer, and the first conductive germanium, forming a gate of the memory transistor from the second conductive layer in the first region of the first phase, from the first The second insulating layer forms a gate interlayer insulating layer of the memory transistor and forms a 'moving gate' of the memory transistor from the first conductive layer, wherein the control gate of the memory transistor is vertical And extending in the second direction of the fourth direction and crossing the active area and the lower device isolation layer pattern. φ [Embodiment] Specific embodiments according to the present invention will now be described in detail, examples of which are illustrated in the accompanying drawings. However, the present invention is not limited to the specific embodiments described hereinafter and the specific embodiments are cited herein so that the scope and spirit of the invention can be easily and completely understood. In the drawings, the thickness of layers and regions is increased based on a clear understanding. It should also be understood that when a layer of claim is "located on another layer or substrate", it may be directly on the other layer or there may be intermediate layers between the layers. θ In the drawings, the relative sizes of the element sizes or components 112311.doc 1300608 may be somewhat exaggerated in order to more clearly illustrate the invention. In addition, the cuttings in the $, ..., I k process \, A, slightly modify the shape of the components depicted by the ® towel. 1. The specific examples that are not disclosed in the New Moons should not be considered as limited to the shape shown in the drawings, but should be considered to be modified to some extent, except in the specific references in the written book. For example, it should be understood that the terms used in the shape of the component (such as "substantially", "about", etc.) can be modified within the scope of allowable process changes. The words "column" and "row" are marked in two different directions, rather than indicating absolute horizontal or vertical direction. = or vice versa. Millennium is on the x-axis and the line is parallel to the y-axis. For ease of explanation, To describe the relationship between a component or feature relative to an eight component or feature as shown in the figure, space-relative terms such as "below", "square", "lower", "above", " In addition to the orientation depicted in the figure, the space above is used to cover different orientations of the device in use or in operation. For example, the component flip in the schema is described as Elements or features that are "below/or below" of other components or features are then oriented to be "above" other components or components. Therefore, the example Kodak ^^", Ding Yu fsheng 3 "below" can be Covers both "above and below" Orientation. The method can be used to orient the Han 90 or other orientations, and the pair of descriptions used herein are interpreted accordingly. The terminology used herein is for the purpose of describing particular embodiments, and is not intended to limit the invention. In this document, the singular form "a 112311.doc 1300608 child" is also intended to include the plural form, except as indicated. It should be further understood that when Fen is explicitly "contained" in other ways, it is used to describe the use of the words "including" and / or the components, components, components, components, components, components, components, components, components, components, components, components, components, components, components, components, components, components, components, components, components, components, components, components, components, components, components, components, components, components, components Grip from the next one or more in the other. (IV) </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; As far as 1 is concerned, since (for example) manufacturing, the change of body shape is expected;; 1 'from the shape of the diagram Λ PP ^ ^ ^ ^ The specific embodiment of the month should not be regarded as f: The specific area shape is not exemplified, but includes, for example, the shape deviation caused by &gt;. For example, an implanted region with a rectangular shape will typically have a circular or curved feature and/or an implant set divergence at its edge rather than a binary from the implanted region to the non-implanted region. </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the invention pertains. Terms such as those defined in commonly used dictionaries are to be interpreted as having meaning consistent with the meaning in the relevant technical background, and should not be interpreted in an idealized or excessively formal sense, except as expressly defined herein. SUMMARY OF THE INVENTION The present invention is directed to a semiconductor device and a method of fabricating the same, and in particular, a NAND flash memory device will be described as an example of a specific embodiment of the present invention. The NAND flash memory device of the present invention includes a plurality of memory cells and associated selection transistors. When the NAND flash memory device is operating, the transistor is selected to apply a desired operating voltage to a select transistor or to interrupt the operating voltage. As a memory cell, a memory transistor having a stacked gate structure will be described as an example. The stacked gate structure of the memory transistor includes a floating gate insulated from a substrate (a channel region) by a tunneling insulating layer; and a gate is controlled by a gate An interlayer insulating layer is insulated from the floating gate. When a suitable operating voltage is applied to the substrate, a source, a drain, and the control gate is charged from the substrate through the tunneling insulating layer to the floating gate &quot; or vice versa. By virtue of charge transfer, the memory transistor has at least two discernable threshold voltage levels corresponding to logic states. Although the gate structure of the select = male body is similar to the memory transistor because the selected transistor has a floating gate and a control gate, the floating gate and the control gate are selected to pass through, for example, butt contact. And electrically connected to each other, so the choice of the transistor is different from the memory transistor. In the specific embodiment, the "floating gate" of the transistor can be called the "five poles" and the control of the transistor is selected. The gate can be called the "second gate". ..., a predetermined number of memory transistors (for example, 16.6, 32..... ^. Hidden transistors) are connected in series to form a memory string. A first == crystal and a second selected transistor are connected to the memory string memory cell and the last memory cell. One bit line and — 112311.doc 13 1300608 The common source line can be respectively connected to the first selection transistor and the second selection transistor. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic plan view of a NAND_memory device in accordance with the present invention. Please see the picture! The NAND flash memory device includes a memory transistor and a selected electrical body operatively coupled to the memory transistor. For ease of explanation, in the following description of the specific embodiment of the present invention, the region 10 at which the memory transistor is formed is referred to as a "first region", and the region 20 at which the selective transistor is formed is referred to as a "second region". Area". A plurality of device isolation layer patterns 4A extending in a first direction (for example, column direction) I are disposed on a semiconductor substrate 30. The respective active areas 5〇 are defined between the isolation patterns 40 to extend in the first direction. The memory transistor is formed on the active region of the first region 1 , and the selective electro-optic body is formed on the active region of the second region 20. Herein, n memory transistors in each of the first regions 1 延伸 extending in the first direction are connected in series, thereby forming a memory string. The control gates of the plurality of memory transistors arranged in a second direction (e.g., the row direction) are connected to each other such that the word lines WL0 WL WLn are formed accordingly. Alternatively, the control gates of the plurality of memory transistors arranged in each row are connected to a word line. A 5 watt selection transistor is formed in the second region 20 to connect it to the 彳 彳 彳 transistor in the 苐 &amp; For example, a first selection transistor (string seiect transist) is connected to the first memory transistor of each serial memory string, and a second selection transistor ( A ground select transist is connected to 112311.doc -14- 1300608 2 the last memory transistor of each series of memory strings. The second gates of the first selection transistors arranged in the second region 20 are connected to each other to form a first selection line (or string selection line ssl. Further, the second region 20 is in the direction of the column Arranging the second one poles of the second selection transistors to be interconnected, thereby forming a second selection line (or ground selection line), wherein the first gate and the second gate of each selection transistor are selected herein The poles are electrically connected to each other through the butt contact 70. A plurality of word lines WL0 are arranged on the semiconductor substrate 30 in a mirror symmetrical and repeating manner with the string, the line selection SSL, and the #地 selection line being disposed therebetween. ~ WLn configured complex structure. A common source line CSL is arranged between the adjacent second selection line GSL, and according to the second selection of the electrical anode is turned on or off, one applied to the ground selection The operating voltage of line 〇sL (eg, 〇V) is forwarded to the source/drain of the memory transistor. One of the lines of contact DC is placed between each adjacent first line of choice SSL. In the zone, and the bit line is electrically connected to each bit line contact DC. A selection transistor is turned on or off, and an operating voltage applied to the bit line is applied to the source/drain of the memory transistor. A region 60 indicated by a dashed dotted line in FIG. 1 has the first region. 10 and a portion of the second region 20 adjacent to the first region 1 ,, wherein the region 60 is hereinafter referred to as an "inverted T-shaped gate region". Formed in the inverted τ-shaped gate region 6〇 The first gate of the selected transistor and the floating gate of the memory transistor respectively have an inverted T-shaped cross section. For convenience of explanation, an area of the second region 2 除 except the inverted T-shaped gate region 60 is hereinafter described. 80 is referred to as a "box-shaped gate region". Figure 2 is a partial enlarged view of a region 90 of Figure 1, which is in the first region where 112311.doc -15 - 1300608: a hidden body transistor is formed. The boundary region between the first region and the second region where the selective transistor is formed. Referring to FIG. 2, the selection transistor 1 includes a gate stack structure and is formed on both sides of the gate stack structure. Impurity regions 191S/D and 193S/D' on the active region, wherein the open-pole stack structure is electrically connected to the first gate 13〇 and the second The gate electrode 17 is configured. Meanwhile, the memory transistor 200 includes a gate stack structure and impurity regions 193S/D and 291S/D formed on the active regions at both sides of the closed-pole stack structure, wherein The idler stack structure is configured with a floating idler 23 and a control gate 270 insulated from the floating gate 230 by a free interlayer: edge layer.

The structure of the floating gate 23A of the memory transistor 200 is different from the structure of the first gate 13A of the selective transistor 100. In detail, the first gate 13A of the selected transistor 1〇〇 can be divided into two parts, one of which: a minute, a structure similar to the floating gate of the memory transistor (four) A portion 135, and another portion, is a second portion 137 that is structurally distinct from the floating gate 230. The first portion (1) of the first gate 13() is disposed adjacent to the memory transistor 'i.e., adjacent to the impurity region 193S/D. Conversely, the second portion m of the first gate 13A is arranged adjacent to the bit line contact DC (which is opposite the memory transistor 2〇〇) 'that is' adjacent to the impurity region 1 9 1 S/D. The selection of the transistor and the memory transistor in accordance with the present invention - a specific embodiment will be explained in more detail below with reference to Figs. The cross-sectional view shown in FIG. 3 is taken along the line of FIG. 2; that is, the device isolation layer (10) in the box-shaped gate that travels through the second region 20 and the (four) direction of the active region To show a cross-sectional view of the second portion 137 of the 112311.doc-16-Ϊ300608 first-gate 13〇 of the selected transistor (10). Figure 4 is a cross-sectional view taken along line Π-Π of Figure 2, that is, the device isolation layer 4 () in the inverted T-shaped gate region 6〇 traveling through the second region 2〇 And a predetermined direction ′ of the active region π to exhibit a cross-section ff1 of the first portion 135 of the first gate 13A of the selected transistor 1〇〇. The cross-sectional view shown in FIG. 5 is taken along the line of the fairy line of the ^, that is, the predetermined direction of the device isolation layer 40 and the action area 5〇 in the butt contact area 7〇 of the (4th). Exhibition

An electrical connection between the first gate 13Q of the select transistor (10) and the second open gate 70 is shown. Referring to Fig. 3, the first portion 137 of the first free transistor of the selection transistor 1 has a box-like shape. However, referring to Fig. 4, the first portion 135 of the first gate 130 of the selection transistor u) has a substantially inverted τ shape. For example, the first portion (3) of the first gate 13A can be divided into a horizontal portion 131 and a vertical portion 133 (which is connected to the horizontal portion 131 and extends upward relative to the substrate 3), wherein the vertical The width of the portion 133 is less than the width of the horizontal portion 131. A first insulating layer 110 is disposed between the first gate 13A of the select transistor 100 and the active region 5A. Referring to FIG. 5, the first closed pole 13 and the second (four) are electrically connected to each other through a predetermined area (ie, the butted contact area 7A) of the second insulating layer 150. Referring to FIG. 3 to FIG. 5, in the box-shaped gate region (9) of the second region 2, the top surface of the device isolation layer 4 adjacent to the second portion 137 of the first gate 13G The height is substantially equal to the height of the top surface of the second portion 137 of the first gate 13A. That is, in the second zone, the device isolation H2311.doc 1300608 layer covers most of the side surface of the second portion 4 of the first closed pole 13A. However, 'Please refer to FIG. 4', in the inverted gate region 60, the top surface height of the device isolation layer adjacent to the first portion 135 of the first gate 13A is substantially equal to the first - the top surface dimension of the horizontal portion i3i of the portion 135. The relatively high device isolation layer in the box-shaped gate region 8〇 prevents the active region from being damaged by the etch during the gate patterning process. The cross-sectional view shown in FIG. 6 is taken along the line of the fear line of FIG. 2, that is, the device isolation layer 4 in the first region H) and the action region predetermine the direction 'to show the A cross-sectional view of the floating electrode 23 of the memory transistor. Referring to Figure 6, the floating gate 230 of the memory transistor 2A has an inverted T-shaped cross section. For example, the read floating gate 230 can be cut into a horizontal portion 231 and a vertical portion M3 (which is connected to the horizontal portion 23 and extends upward relative to the substrate 3), wherein the vertical portion is 2% wide Less than the width of the horizontal portion 231. In this specification, the horizontal portion 231 and the vertical portion 233 of the floating gate of the memory transistor can be divided into a lower conductive pattern and an upper conductive pattern. - Between the (4) gate 230 and the action (4) with the insulating layer 21 穿. The floating gate 23 〇 and the inter-pole 270 are insulated from each other by a closed-layer interlayer insulating layer interposed therebetween. The height of the top surface of the device isolation layer 40 adjacent to the floating gate 23A is substantially equal to the height of the top surface of the horizontal portion 231 of the floating gate 230. The height X and k of the device isolation layer 40 can be modified in various aspects according to a specific embodiment, so that the U2311.doc 1300608 is disposed on the box-shaped closed region of the second region 2〇, and the isolation layer 40 is higher than The device isolation layer 40 is formed in the inverted T-shaped gate region 60. For example, the device isolation layer 4 is formed in the first region 10 such that it can be lower than the active region 50 or can be higher than the top surface of the horizontal portion 231 of the floating gate 230. The first insulating layer 110 of the selection transistor and the tunneling insulating layer 210 of the memory transistor may be formed from the same layer. For example, the first insulating layer 110 and the tunneling insulating layer 210 may be formed of a yttrium oxide layer having a thickness in the range of 20 angstroms to 200 angstroms. However, it is not limited to the above, so it can also be formed by a metal dielectric layer having a high dielectric constant. The first gate 130 of the selection transistor and the floating gate 230 of the memory transistor can be formed from the same layer. For example, the first gate 13 0 and the floating gate 230 can be formed by using a stone eve. Similarly, the second gate 170 of the selection transistor and the control gate 27 of the memory transistor can be formed from the same layer. For example, the second gate 17A and the control gate 270 can be formed of germanium, germanide, a metal material, or a combination thereof. The second insulating layer 150 of the remote selection transistor and the far gate interlayer insulating layer 250 of the memory transistor can be formed from the same layer. For example, the second insulating layer 150 and the gate interlayer insulating layer 25 may be a plurality of layers configured by the following layers: a layer of yttrium oxide having a thickness ranging from 3 angstroms to 8 angstroms; a tantalum nitride layer having a thickness in the range of 50 angstroms to 15 angstroms; and a yttria layer having a thickness in the range of 30 angstroms to 100 angstroms. 7 and 8 are cross-sectional views of the memory transistor and the selective transistor, respectively, taken along the direction in which the active region 5 〇 extends (ν_ν, and νι_vm in FIG. 2). Referring to Figures 7 and 8', the selected transistor 1 includes symmetrically formed impurity regions 112311.doc -19-1300608 191S/D and 193S/D. Herein, the doping concentration of the impurity region symmetry and/or the depth from the surface of the substrate may be different from the other impurity region. The doping concentration of the impurity region 19 adjacent to the second portion 137 (ie, adjacent to the drain contact DC) is higher than the junction depth is deeper than the first adjacent to the selected transistor The doping concentration and junction depth of the impurity region 193S/d of the first portion 135 of the gate 13 (i.e., adjacent to the memory transistor 2A). Since the impurity region 1938/〇 adjacent to the memory transistor 2 has a relatively low doping concentration and a shallow junction depth, it is possible to reduce the memory device operation in the memory transistor 2〇〇 The channel hot electron effect and/or the gate induced drain leakage (GIDL) effect generated in the channel region below. At the same time, since the impurity region 191S/D adjacent to the drain contact DC has a relatively high doping concentration and a deep junction depth, the junction leakage current can be minimized to improve the withstand voltage characteristics. Further, it is possible to form a vaporized layer having a suitable property on the impurity region 191 S/D adjacent to the drain contact DC. In addition, in the selection transistor 100, a channel doping concentration of a first portion of a channel region under the first portion 135 of the first gate 13A may be different from that at the first gate 13 The channel doping concentration of the second portion of the channel region below the second portion 137. For example, the channel doping concentration below the first portion 135 of the first gate 130 can be higher than the channel doping concentration below the second portion 137. That is, the second portion 137 may be thickly formed into a box shape, and conversely, since the first portion 135 has an inverted τ shape, it may be formed to be relatively thinner than the second portion 丨37. Therefore, 112311.doc -20-Ϊ300608 makes it possible to easily and appropriately control the doping concentration of the channel region under the first portion 丨3 5 . Since the channel doping concentration can be controlled, it is possible to suppress the penetration of the selective transistor 100 due to the integration of the device. For example, by implanting impurity ions into the 5 channel region through the horizontal portion m by an ion implantation process, the channel doping concentration of the channel region under the thin horizontal portion 13 1 can be increased. Since the floating gate 23 of the memory transistor 2 has the horizontal portion 23 1, it is possible to easily control the doping concentration of the channel region by the ion implantation process through the horizontal portion 231. . A memory transistor according to a specific embodiment of the present invention will hereinafter be described in more detail with reference to Figs. 9A, 9B and 10. Fig. 9A is a schematic cross-sectional view showing a floating gate as an example in the row direction (in the direction in which the control gate extends); and a perspective view showing the arrangement of the floating gate. For ease of explanation, only four floating gates are shown in FIG. Referring to FIG. 9A, a floating gate electrode 230 according to an exemplary embodiment of the present invention includes the horizontal portion 231 and the vertical portion 233. In this specific example, the horizontal portion 23 and the vertical portion 233 are formed from the same layer. The vertical portion 233 protrudes from a predetermined portion of the top surface of the horizontal portion 23A. The width w2 of the vertical portion 233 is smaller than the width W1 of the horizontal portion 231, and the thickness of the vertical portion 233 is larger than the thickness hl of the horizontal portion 23i. Meanwhile, the sectional area S2 of the vertical portion 233 is larger than the sectional area &amp;amp of the horizontal portion 231, where Sf%a! and S2 = W2Xh2. In order to embody a highly integrated semiconductor device, it is desirable to form a narrowest level of "Hai" 23 1 °. The preferred way is that the thickness of the horizontal portion 23 i is 112311.doc 1300608 may be small 'to minimize the difference between Interference between horizontal portions adjacent to each other in the ancient and J directions, and/or minimizing interference between horizontal portions adjacent to each other in the row direction, according to a specific embodiment of the present invention, the thickness of the horizontal portion h may depend on the thin film deposition process technology and (4) the process, so the horizontal portion 231 may be broken to be very thin. At the same time, the vertical portion plus can be formed as narrow as possible to increase the spacing between adjacent vertical portions. According to this specific embodiment, the condition (e.g., quotation time) is used to control the vertical portion plus the width W2 to have a desired width. The following condition is satisfied: the cross-sectional area of the vertical portion 233 is greater than the vertical axis. The cross-sectional area Si of the P-knife 233; and the width % of the vertical portion is smaller than the width w of the horizontal portion 231, it is possible to appropriately change the width and thickness of the vertical portion plus the horizontal portion 231 so that it is suitable for embodying A device with a coupling ratio and a high degree of integration. The effect or advantage of the floating interpole electrode in accordance with an embodiment of the present invention will be described in detail below with reference to FIG. 9B. For convenience of description, the four floating idle poles are not referred to as the first floating interpole electrode 23, the second floating gate electrode 9^Λ~2 brothers two kilograms of the gate electrode 230-3 and the fourth floating gate electrode 4 The first floating gate electrode 23〇—α the second floating gate electrode is disposed in the first column, and the third floating gate electrode 230_3 and the fourth floating gate electrode 230-4 are arranged. In the second column. The Lth floating 1 Φ·electrode 23G-1 and the third floating gate electrode 23Q-3 are arranged such that the second floating gate electrode 23〇2 and the fourth floating closed electrode 23〇 are disposed. The 4 series is arranged in the second row. First, the interference between 112331.doc -22- 1300608 will be proposed between the floating electrode electrodes adjacent to each other in the column direction. According to this embodiment, the profile of the floating gate electrode is configured with the horizontal portion 231 and the vertical portion 233. That is, the floating gate electrode has an inverted τ-shaped cross section. Therefore, the distance 4 between the vertical portion 231-3 of the first floating gate electrode 23 (L1 and the vertical portion 232-3 of the second floating gate electrode 23〇-2 is greater than the level The distance t between the portion 23 1 1 and the horizontal portion 231 - 2 makes it possible to reduce interference between adjacent floating gate electrodes. Further, since the horizontal portion can be formed as thin as possible, The facing area S3 between the two horizontal portions 231-1 and 231-2 adjacent to each other in the column direction is very small, so even if the distance ch between the horizontal portions 2"^ and 231 2 becomes short, it can be ignored. At the same time, although the vertical portions 233 - 1 and 231-2 adjacent to each other in the column direction have a large thickness ^ for a high coupling ratio, so as to face between the vertical portions 233 - 1 and 231-2 The area S4 becomes large, but since the length between the vertical portions 233-1 and 231-2 is sufficiently long, the interference is no longer increased. As described above, since the width of the vertical portion becomes small, The distance ds between the two vertical portions 233 - 1 and 231 - 2 is increased, which The interference between the vertical portions adjacent to each other in the column direction is now reduced. Hereinafter, interference between floating gate electrodes adjacent to each other in the row direction will be proposed. Between the first floating gate electrodes The interference between 230-1 and the third floating gate electrode 230-3 depends on the total facing area S^TAL, which is the facing area between the horizontal σ卩 points (s) = WiX h 】) plus the sum of the facing areas d=W2X h) between the vertical p-knife. In this paper, since the vertical portion has a narrow width W2, it can be reduced to be adjacent to each other in the column direction 112311.doc * 23 - 1300608 Interference between floating gates. Note that the floating gate electrodes 230 in Figures 9A and 9B are shown for ease of explanation, and thus the shape can be slightly modified in accordance with various manufacturing processes. It will be understood that the shape of the floating gate electrode of the specific embodiment is not limited to the shapes shown in FIGS. 9A and 9B and described above, but may be modified within the scope of allowable manufacturing process changes. For example, even if stated The layer or element has a soft surface, but it can have A little rough surface, and _ not a soft surface. Similarly, even if the layer or element is described as having a flat surface 'but it may have a somewhat soft and rough surface instead of a flat surface. Further 'even if the layer or element is described a vertical side wall, but which may have a slight sloping side wall. For example, although the figure schematically illustrates from 9B that the floating gate electrode has a flat surface, that is, the surface of the horizontal portion and the vertical portion are flat, it may have Soft or slightly rough surface. Further, although the side surfaces of the floating gate electrode (i.e., the side surfaces of the horizontal portion and the vertical portion) are depicted in Figs. 9A and 9B, they may be formed to be slightly tilted. In addition, the width of the vertical portion can be increased as it is further apart from the substrate. Similarly, the width of the horizontal portion can be increased as it is further apart from the substrate. Examples of various floating gate electrodes will be explained below with reference to FIG. Referring to Figure 10, the floating gate electrode 230, the horizontal portion 231, is formed such that its top surface is tilted. Further, the vertical portion 233 is formed to also have its side surface inclined. The floating gate electrode of Fig. 10 appears to be formed by rubbing Fig. 9A and the net moving electrode of the sinus, but it still has a substantially inverted shape. It can be understood that the floating gate electrode 23A shown in FIG. 10 has a side surface of the vertical portion 1123n.doc -24-1300608 23 3 which is opened so as to be slightly inclined so that the width of the vertical portion u3 varies with height. The width % of the vertical portion shown in Fig. 9AA9B corresponds to the maximum width % of the vertical portion 233. Similarly, the top surface of the horizontal portion 231 of the floating gate electrode 230 shown in FIG. 1A is inclined such that the width of the horizontal portion 231 varies with height, and the width of the horizontal portion shown in FIGS. 9A and 9B. % corresponds to the maximum width % of the horizontal portion 231. As described above, the maximum width % of the horizontal portion 231 is greater than the maximum width W2 of the vertical portion 233, and the cross-sectional area 8 of the horizontal portion 231 is larger than the cross-sectional area of the vertical portion 233 &amp; . The maximum width W! of the horizontal portion 231 may be 15 to 25 times larger than the maximum width w/ of the vertical portion 233. The various modifications of the floating gate shape of the memory transistor described with reference to Figures 9A, 9B and 1B are equally applicable to the selection of the first portion of the first gate of the transistor. Hereinafter, a method of manufacturing a NAND flash memory device according to a specific embodiment of the present invention will be described in detail with reference to FIGS. 11 through 18. Referring to the figure, a device isolation process is implemented to form a device isolation layer pattern 4〇〇 extending in a column direction (i.e., the y-axis) on a substrate 300. Thus, a number of active areas 5 界定 are defined by the device isolation layer pattern 400. A first insulating layer 600 and a first conductive pattern 700 are formed on the respective active regions $(9). The first conductive pattern 700 is self aligned on the active area 500. In detail, an insulating layer of the first insulating layer 6 及 and a conductive layer of the first conductive layer pattern 700 are formed on the slab 300. Thereafter, the conductive layer, the insulating layer, and a portion of the substrate 3 are etched to a predetermined thickness to define a skirt isolation 112311 .doc -25- 1300608 region. Therefore, the active area 500 is defined in the substrate 3, and the edge/edge layer 600 and the first conductive layer pattern 7 are self-aligned on the active area, and the edge material is filled into In the device isolation region, wherein the predetermined portion is removed by insect etching, thereby forming the device isolation layer pattern. In this paper, the isolation layer of the device can be formed. FIG. 4(10) is: after depositing the insulating material, performing a planarization process , such as chemical mechanical polishing (CMP) or etchback processes. For example, the first conductive pattern 700 (which is used to select a transistor: a gate and a floating gate of a memory transistor) can be formed using germanium. The first insulating layer _ (which is used as a gate insulating layer for selecting a transistor and a compliant insulating layer of a memory transistor) can be formed by an oxygen etch layer having a thickness ranging from 2 Å to 2 (9) Å. However, it is not limited to the above, so the first insulating layer _ can be formed by a metal dielectric layer having a high dielectric constant. The Fig. 12' is formed with a mask _ on the first conductive layer pattern and the device pattern to expose the inverted gate 3. That is: _0 simultaneously exposing the first region and the second region adjacent to the first region mask 8 can be used with respect to the first conductive pattern 7. . For example, the material of the etch selectivity of the device isolation layer pattern 4 can be obtained by using tantalum nitride. The cover _ exposes the portion of the second region and the first region becomes this =, The third layer of the selective transistor in the second region is formed into a shape having a collapsed shape. The portion of the &quot;Haidi is shown in Fig. 13, and the isolation layer pattern of the device is completely (they are not subjected to the inverted shape) 112311.doc -26- 1300608 to form a lower portion of a conductive pattern 700). A conductive layer pattern 700 = covered by the mask _ is partially removed from the layer pattern 410 (the top surface of which is lower than the second lower portion) The device isolation layer pattern 410 partially exposes the first side surface. Referring to FIG. 14, the exposed side surface of the first conductive pattern 100 is patterned by the width of the first conductive layer pattern 7'. Having a narrow width pattern: a first conductive layer pattern 710 (which is isolated from the lower device: the top surface of the ^ is protruded upward) is used as the vertical of the inverted T-shaped gate, and at the same time, the 6-th lower device isolation layer The remaining pass V pattern 730 surrounded by the pattern 41 is disposed in the narrowing A conductive layer pattern below is used as a horizontal portion of the inverted gate. For example, the fourth conductive layer pattern 7 can be implemented by using a predetermined (four) solution for the engraving process. The exposed side surface. Alternatively, the residual gas may be used for the dry (four) process. If the secret process is used, the etching solution contains NH4〇H. Referring to Figure 15, the mask 800 is removed to expose the The device isolation layer pattern 4 〇〇 and the first conductive layer pattern 700 in the 闸-shaped gate region of the second region. Referring to FIG. 16 and FIG. 17, a second insulating layer 9 〇〇 and a second portion are formed. After the conductive layer (9), a gate mask 1100a and 1 00b are formed to define a control gate of the memory transistor and a second gate of the selected transistor, wherein the gate masks 1100a and 1100b are in a column direction (ie, , X-axis) extension. Referring to FIG. 18, the second conductive layer 1 , the second insulating layer 900 and the first layer are etched by using the gate masks uooa and ii〇〇b as a mask. 112311.doc -27- 1300608 A conductive layer pattern 700, thereby forming a memory electron crystal a stacked gate structure of the body and a stacked gate structure of the selected transistor. The stacked gate and the gate of the memory transistor comprise: a floating gate formed by the first conductive layer pattern; formed by the second insulating layer a gate interlayer insulating layer; and a control gate formed by the second conductive layer. The stacked gate structure of the selected transistor includes: a first gate formed by the first V-layer pattern; and the second insulating layer a closed-cell interlayer insulating layer formed; and a second gate formed using the second conductive layer. According to a specific embodiment of the present invention, the device isolation layer 400 of the second region is formed at the place where the selective transistor is formed The thickness is relatively thicker than the thickness of the lower device isolation layer of the second region where the = memory cell is formed, and thus during the etching process for forming the stacked gate structure, it is possible to prevent attribution due to The loading effect in the region causes the active region to be damaged by the money: for example, if the device isolation layers of the first region and the second region have almost the same thickness, the etching process for forming the stacked gate structure is performed. May return Loading effect of the substrate in the second zone being damaged Yun moment. The reason is that the memory electro-crystal system is closely formed in the first region and the 4-selective electro-crystalline system is sparsely formed in the second region, and the substrate of the first region of the child can be damaged by etching. However, according to the specific embodiment of the invention, due to the thickness of the device isolation layer of the device isolation layer of the second region, it is possible to have an efficiency of etching damage, in other words, according to the present invention, The thick device isolation layer of the first region can be used as an etch stop layer. ^ One kilogram in the selection of the transistor, the electrical connection between the intermediate pole and the second pole can be achieved through a butt contact or the like. For example, after the 112311.doc -28-1300608 second insulating layer 900 is formed, the second insulating layer 9 is patterned so as to be exposed in the second region to form a memory transistor. And pre-determining the first conductive layer in the portion or forming the second conductive layer after removing the second insulating layer from the second region. Accordingly, the first gate and the second gate are electrically connected.

An ion implantation process is performed to form a memory transistor and a source/drain region of the selected transistor. The selective source/drain region of the selective transistor adjacent to the drain contact is selectively implemented - an additional ion implantation process. The additional ion implantation process for the gate/drain regions can be performed using an ion implantation process for the source/drain regions of the transistors in the peripheral circuitry. The memory transistor will be described in detail below. Figure 19 is a cross-sectional view showing a memory transistor of a flash memory device in accordance with another embodiment of the present invention. Referring to Fig. 19, a plurality of device isolation layer patterns 120 are disposed on the semiconductor substrate (10) to define an active region ι2 to define the active region 1〇2 between the layer patterns 120. . That is, the adjacent device is separated by a gate insulating layer 14

Formed on the active area 1 〇 2, and a floating gate electrode 192 is disposed on the gate insulating layer 140. The floating gate electrode 192 includes a lower conductive pattern 155 and an upper conductive pattern m. The width % of the lower conductive pattern 155 is greater than the width % of the upper conductive pattern 17A. Therefore, the floating gate electrode 192 has an inverted τ-shaped cross section. (4) On the floating interpole electrode μ, a gate interlayer insulating layer 丨94 and a control gate electrode 丨96 are disposed. The control gate electrode 196 crosses the active region 1〇2 and the device isolation layer pattern 12〇. The gate gate electrode 196, the gate interlayer insulating layer pattern 194, and the floating gate electrode 192 constitute a stacked gate structure of the memory transistor. 112311.doc -29- Bay 608 Preferably, the range of production = μ nail insulation layer 140 is used with a 20 angstroms to 200 angstroms of electricity, and the A - 1 fossil layer is shaped A, but A high dielectric pattern 155 can be used as the gate insulating layer 140. The lower conductive layer is formed by a plurality of germanium wafers, and the upper conductive pattern 170 may be made of a ruthenium compound, a metal material or a JL, and a human + γ may be used as a lower layer of insulation. The gate layer is up to 80 angstroms in the range of ^ / layer: - a layer of oxidized stone having an internal extent of 30; an nitridation of 50 angstroms to 150 angstroms; and - having 3. In the range of Å to 矣, the emulsified layer is emulsified. The gate electrode 196 can be formed by polycrystalline stone, bismuth, metal material or a combination thereof. «The invention Width % of the lower conductive layer pattern 155 It is larger than the width of the top surface of the "02" or the width of the gate insulating layer 14A. The top surface of the active spacer pattern 120 between the "I" and the lower conductive patterns 155 may be lower than the top surface of the active area (10). Accordingly, the bottom surface of the gate interlayer insulating layer pattern i 9 4 or the bottom surface of the control gate electrode i 9 6 may also be lower than the top surface of the active region 102 between the adjacent lower conductive patterns 155. . If the top surface of the control gate electrode 196 is lower than the top surface ' of the active region 1() 2, the facing area between the control interpole electrode 196 and the floating gate electrode 192 increases. In addition, the control gate electrode i96 prevents interference between floating gate electrodes adjacent in the column direction, for example, a capacitance between adjacent electrode electrodes. An increase in the area of the face between the control gate electrode and the floating gate electrode achieves an increase in the face ratio (CR) where the ratio of the ratio indicates that the voltage applied to the control gate electrode 196 is transferred 112311.doc -30-1300608 efficiency to the floating gate electrode 192. In addition, according to an embodiment of the present invention, it is not necessary to increase the height of the floating gate electrode 192 (for example, it is not necessary to increase the cross-sectional area), and it is still possible to increase the floating gate electrode 192 and the control electrode. The facing area between 196. As described above, the flash memory device of this embodiment can increase the facing area by the top surface concave structure of the device isolation layer pattern 120.

8. In addition, since the floating gate 192 has a substantially inverted τ-shaped cross section, the facing area between the floating gate electrodes adjacent to each other in the row direction is reduced: as shown, the lower conductive pattern 155 is assumed. The width and thickness are respectively shown as wjhl, and the width and thickness of the upper conductive pattern 17〇 are denoted as 2 and 1! 2, respectively, and the inverted floating gate of the present invention is compared with the box-shaped gate electrode. The cross-sectional area of the electrode 192 becomes (Wi_W2) x h2. Reducing the floating gate cross-sectional area reduces the interference effect between the floating closed-pole electrodes adjacent to each other in the row direction, and as a result, provides a process margin that increases the surface area of the floating idle electrode, and thus increases Make a big deal. The floating gate electrode of the embodiment of the present invention makes it possible to increase the maximum cross-sectional area of the surface area, wherein the surface area determines the filial mat ratio. According to a specific embodiment of the present invention, the cross-sectional area (WlXhl) of the lower conductive pattern 155 is larger than the cross-sectional area (W2Xh2) of the upper conductive pattern Γ, at least Ϊ: Ϊ1Τ is the width wi of the lower conductive pattern 155 is larger than the ^ Width of η170 W2° Hereinafter, a method of manufacturing a gate structure of a non-volatile memory device according to the present invention will be described in detail. 0 H2311.doc 1300608

20 is a cross-sectional view of a flash memory device in accordance with another embodiment of the present invention. Similar to the floating gate electrode of Fig. 19, the floating gate electrode 192 includes a lower conductive pattern 155 and an upper conductive pattern 17A, wherein the width of the upper conductive pattern 17'' is smaller than the width of the lower conductive pattern 155. For example, the floating gate electrode 192 has a stepped side surface. In the non-volatile memory device of this embodiment, the floating gate electrode 192 is self-aligned on the active region 1〇2. For example, the width of the lower conductive pattern 155 of the floating gate electrode 192 is substantially equal to the width of the top surface of the active region 102. For example, when two layers deposited during a semiconductor fabrication process are successively patterned by using an etch mask, the two patterns formed using the two layers may have the same width on the real f. Further, the top surface height of the device isolation layer pattern i 2 〇 is equal to the top surface height of the lower conductive pattern 155 of the floating interpole electrode m. Additionally, in a particular embodiment of the invention, the floating gate electrode 192 is formed such that the cross-sectional area of the upper conductive pattern 170 is greater than the cross-sectional area of the lower conductive pattern (5).

Figure 2 is a cross-sectional view of a flash memory device of an embodiment, not according to the present invention. In the embodiment of the present invention, the device isolation layer pattern 120 is formed by a spacer film, and the second conductive pattern 155 and the shihai gate insulating layer 14 are formed in two (10) patterns. On the surface of the side acoustic ridge, this is different from the flash memory device shown in FIG. In this paper, the top surface of the device isolation layer pattern 120 is relatively lower than the active area! The top surface of 〇2. The specific embodiment is used for manufacturing. Referring to FIG. 22A, a cross-sectional view of a method of NAND flash memory according to the present invention is shown in FIGS. 22A to 22H. H2311.doc-32-1300608 A trench mask pattern 110 is formed on a semiconductor substrate 100. The trench mask pattern 110 includes a pad oxide layer pattern 112 and a mask nitride layer pattern 114 stacked in sequence. Etching the semiconductor substrate 100 using the trench mask pattern 11 as an etch mask, thereby forming a trench 105 defining the active region 102. The trench mask pattern 110 may further include a stack A ruthenium oxide layer (for example, a medium temperature oxide (MT〇)) and an anti-reflection layer on the nitride pattern 114 are masked. Further, the types, thicknesses, and stacking order of the layers constituting the trench mask pattern no are variously changed. The process of forming the trenches 1〇5 may include etching the semiconductor substrate 1A in an anisotropic manner using an etching process having an etching selectivity with respect to the trench mask pattern. Although the side wall of the trench 105 is shown as being inclined, the sidewall of the trench 1〇5 has a vertical cross section according to the manufacturing process. In addition, the joint portion of the side wall and the bottom of the groove 105 may have a smooth curve. Referring to FIG. 22B, after forming an insulating layer for device isolation to fill the trench 105, the insulating material for device isolation is etched until the top surface of the trench mask pattern U0 is exposed, thereby forming a filling. The trench 105 and the device isolation layer pattern wo surrounding the trench pattern 11〇. According to a specific embodiment of the present invention, it is preferable that the insulating material for device isolation is formed using a ruthenium oxide layer, but it may be formed by polycrystalline shi, feldspar, porous insulating layer or the like. In addition, before forming the insulating material for device isolation, a thermal oxide layer (not shown) may be formed on the soil within the trench 〇5 for solving the etching of the semiconductor substrate (10). The resulting etching is damaged. In addition, a liner may be additionally formed to prevent impurities from penetrating through 112311.doc -33-1300608. The liner may be a tantalum nitride layer. The ruthless method is to use an etch process to etch the insulating material for device isolation by using a slurry having a pH of 1 相对 relative to the trench mask pattern. Alternatively, a dry or wet etch back process can be used. Referring to Figure 22C, the trench mask pattern i i 去除 is removed to form a gap region 13 曝 exposed to the top surface of the active region 102. In detail, forming the gap region 130 includes: removing the mask nitride pattern 114 by using a wet etching method having a φ etch selectivity with respect to the device isolation layer pattern 120; and using the semiconductor substrate 1 with respect to the semiconductor substrate 1 The pad oxide layer pattern 丨12 is removed by an etch selective wet money engraving process. At the same time, the exposed sidewalls of the device isolation layer pattern 120 can be etched to a predetermined thickness when the pad oxide layer pattern 丨12 is removed. Accordingly, the width of the edge gap region 130 becomes larger than the width of the active region i 〇2. According to a specific embodiment of the present invention, since the device isolation layer pattern 12 and the liner oxide layer pattern 112 are formed by the same material (ie, the oxidized stone layer), it is possible to enlarge the gap region 13 Width without the need to replenish the process. In addition, since the width of the gap region 130 is enlarged, the width of the floating gate electrode of the non-volatile device is also enlarged, and the factory f is used to make the top surface of the device isolation layer pattern 12 During the recessed and post-process, it is possible to prevent damage to a gate insulating layer. This will be described below with reference to Fig. 20G. A gate insulating layer 14 is formed on the exposed active region 1〇2. Preferably, the gate insulating layer 140 is formed by oxidation through a thermal oxidation process, but a high dielectric constant metal insulating layer may also be used. The gate 112311.doc -34- 1300608 pole insulating layer 140 may have a thickness in the range of 2 〇 to 2 〇〇. Referring to Fig. 22D, after forming a conductive material for the conductive pattern under the floating gate into the enlarged gap region 13, the conductive material is etched until the top surface of the device isolation layer pattern 120 is exposed. As a result, a conductive gap pattern 15A is formed on the active region 102 to fill the gap region 130. At this time, since the width of the gap region 13A has been enlarged, the width of the conduction gap pattern 15G is also larger than the width of the active region (10). However, as will be more clearly understood from the following description, the width of the conductive interstitial pattern 15? determines the width of the floating gate electrode. Therefore, it is possible to form the floating gate electrode such that the width of the floating gate electrode is larger than the width of the active region. In a preferred manner, the conductive interstitial pattern 15 filled in the gap region 13 is formed by polysilicon in the CMP process. Forming the conductive interstitial pattern includes planarizing a top surface of the conductive interstitial pattern 150 using a wet etch process having an etch selectivity with respect to the device isolation layer pattern 12A. For example, this flattening process can be implemented using a CMp process. At this time, it is preferable to use a predetermined material as the process &lt; mud, wherein the pre-m material has an etching characteristic for the etch rate of the yttrium oxide at the rate of the polycrystalline stone (ie, etching) Selective). Referring to FIG. 22E, the wet interstitial pattern having the (4) selectivity with respect to the device isolation layer pattern 12 is used, and the conductive interstitial pattern 15G' in the gate region is formed by the method to form a lower conduction. Pattern 155 (which is maintained below the gap region 130). At this time, the depth of the conductive interstitial pattern to be engraved is smaller than the depth of the gap region 13A. Accordingly, the lower conductive pattern 155 under the gap region 112311.doc - 35 - 1300608 no remains intact, and the sidewall of the spacer pattern 120 is partially exposed. As a result, the thickness of the lower conductive slab 155 (referred to as _9 is smaller than that of the intervening pattern 3G), and then formed on the lower conductive pattern 155 in an isomorphous manner. A material having a shape relative to the lower conductive pattern (5) is formed. For example, e, the mold layer W0 is formed by a tantalum nitride layer, a oxidized layer or a metal nitride layer. It is clearly understood that the preferred method is to precisely control the thickness of the mold layer 160. This is a process parameter that determines the shape of the floating gate in accordance with the present invention. For this purpose, low pressure CVD (LPCVD) or atomic layer deposition can be used. :a:d) The process is to form the "mold layer 16". In addition, it is also desirable to precisely control the depth of the conductive interstitial pattern 15G and the height of the gap region UG, because these two factors also affect the shape of the floating pole Referring to FIG. 22F, the mold layer (10) is left in an anisotropic manner, and the top surface of the lower conductive pattern 155 is exposed straight (four). Accordingly, a mold spacer 165' is formed to cover the lower conductive pattern 155. The top surface edge. Thereafter, at After the upper conductive layer is formed on the entire surface of the resultant structure in which the mold spacer 165 has been formed, the upper conductive layer is pasted until the top surface of the device isolation layer pattern 12A. As a result, the mold spacers 165 are An upper conductive pattern 17A is formed in contact with the lower conductive pattern 155. Here, in accordance with the present invention, one of the lower conductive patterns 155 and the upper conductive pattern 170 is in contact with each other to form a floating gate pattern 18''. The pole pattern 18 has an inverted T-shaped cross section, as shown in Fig. 22f. The cross-sectional shape of the floating gate pattern 180 is from the height H2311.doc -36-1300608 degrees and width of the lower conductive pattern 丨$5 and The height and width of the upper conductive pattern 170 are determined. Therefore, as described above, it is desirable to precisely control the following conditions: 丨) the height between the device isolation layer 120 and the top surface of the active region 1 () 2 The difference; 2) the width of the gap region 13〇; 3) the stack thickness of the mold layer 16〇; and the etching depth of the upper conductive layer.

As described above, since the upper conductive circle 17 is formed using the mold spacer 165 as a mold, the upper conductive pattern (7) is self-aligned in a central portion of the lower conductive pattern 155. Further, the thickness of the lower conductive pattern 155 according to the present invention prevents the active region 1 2 2 T from being exposed during the etching process for separating the floating idle electrode from the control gate electrode. For example, preferably, the lower conductive pattern 155 has a thickness at least greater than a width of the upper conductive pattern 17A. Meanwhile, the upper conductive layer for the upper conductive pattern (7) may be formed using a CVD process or a worm growth process using a polycrystalline compound, a metal layer, or a combination thereof. Alternatively, the (10) process can be used to carry out the etching of the upper conductive layer. The mud can have an etch selectivity with respect to the device isolation layer pattern 120 or the mold spacer 1 65. Referring to Figure 22G', the upper conductive pattern 17 is used and the lower conductive pattern 155 is used as an etch mask to etch the exposed top surface of the device isolation layer pattern (10). According to a specific embodiment of the present invention, the top surface of the device isolation layer pattern 12A is purely engraved through the process of the engraving such that the top surface becomes lower than the top of the active region (10) between adjacent lower conductive patterns 155. The surface is as shown in Fig. 22G. In accordance with an embodiment of the present invention, the mold spacer 165 can be removed when the device isolation layer pattern 12 is recessed 231 l.doc - 37 - 1300608. Therefore, as shown in Fig. 22G, the top surface of the lower conductive pattern 155 is exposed except for the area in contact with the upper conductive pattern 170. Alternatively, the mold spacer 165 can be removed by an additional process. At the same time, since the width of the lower conductive pattern 155 is wider than the underlying active region 102, it is possible to prevent the active region 102 and the gate insulating layer 14 from being etched during recessing of the device isolation layer pattern 12 damage. This prevention effect is apparent if the device isolation layer pattern 120 is recessed until the top surface of the device isolation acoustic pattern 120 becomes lower than the top surface of the active region 1〇2. As described above, it is necessary to enlarge the width of the gap region 130 to prevent etching damage. Referring to Fig. 22H, a stacked gate structure 19 is formed on the resultant structure in which the top surface of the device isolation layer pattern 12A is recessed. The stacked gate structure 190 is configured by a floating gate electrode 192, a gate interlayer insulating layer 194 and a control gate electrode 196 which are sequentially stacked. Forming the stacked gate structure 190 includes: forming an entire surface i of the resultant structure in which a top surface of the device isolation layer pattern (10) is recessed, sequentially forming a gate interlayer insulating layer and a control gate conducting layer; and patterning the The gate conductive layer, the gate interlayer insulating layer, and the floating gate pattern 180 are controlled. As a result, the control gate electrode 196 is formed to cross the adjacent active region and the device isolation layer pattern 12A, and the floating gate electrodes 192 are electrically connected to each other along the extending direction of the active region (10). insulation. The idle interlayer insulating layer pattern 194 may be a multi-tone pattern configured with the following layers: a oxidized stone layer pattern having a thickness ranging from 3 Å to 8 Å: 112311.doc -38- 1300608 a tantalum nitride layer pattern having a thickness in the range of 50 angstroms to 15 angstroms and a yttrium oxide layer pattern having a thickness in the range of 30 angstroms to 1 angstrom. In the specific embodiment of the present invention, the portion (10) of the mold spacer 165 can be removed, as will be described in detail with reference to Figure 2, Figure 2. "The remaining mold spacers 1 6 5 r, so that the hunting of the field "quote", the bucket»: the formation of the stack of gate structure during the etching process, the lower material pattern 155 is almost not damaged by (four). After the process of tf of FIG. 22F, the upper conductive pattern wo and the lower conductive pattern 155 are used as a money mask to engrave the exposed top surface of the device isolation layer pattern 120. Thereafter, the mode interval is removed. a portion of the object 165, thereby forming the remaining mode spacer on the lower conductive pattern 155. Referring to FIG. 23B, after forming a gate interlayer insulating layer and a conductive layer for controlling the gate electrode, The conductive layer, the interpolar layer I insulating layer and the floating closed-pole pattern (10) of the control gate electrode are patterned to form a word line 190. At this time, the remaining mode spacer acts to prevent The lower conductive pattern 155 is damaged by etching. According to a specific embodiment of the present invention, the floating gate electrode 192 is configured by the lower conductive pattern 155 and the upper conductive pattern 17A. Upper conductive pattern 170 and the The portion conductive pattern 155 can be formed from the same conductive layer or a layer of the same configuration, as shown in Figure 24a and in detail. The specific embodiments of Figures 24A and 24B are included in the foregoing specific embodiments of Figures 22 through 22d. A mask pattern 2 is formed on the conductive interstitial pattern (see reference numeral 150 of FIG. 22d), and a complementary process for forming the upper conductive pattern is not required, wherein the mask pattern defines the upper conduction pattern H2311 .doc -39- 1300608 case 170. The mask pattern 2 can be formed on the inverted τ gate region. After the processes of Figs. 22A to 22D are performed, the mask is formed on the conductive gap pattern 15 The pattern 20G is formed as an etch mask using the mask pattern as shown in FIG. 24A, and the conductive gap pattern 150 is etched to a predetermined depth, thereby forming the lower conductive pattern 155 and the upper conductive pattern i7Q. The structure of the upper conductive pattern 17 and the lower conductive pattern 155 in this embodiment is the same as that of the other specific embodiments except that it is formed from a single layer. Preferably, the mask pattern 2〇 The lanthanide is formed by a lithography process, but it can be formed using various materials such as nitridox, oxidized stone, and oxynitride arsenal. Meanwhile, the mask pattern 2 考虑 defines the upper conductive pattern 170 Therefore, the mask pattern 2 is narrower than the lower conductive pattern. To form the mask pattern with a narrow width, forming the mask pattern may include forming a predetermined width on the gap pattern 150. The sacrificial pattern is reduced by the isotropic etching process. As shown in Fig. 24B, the mask pattern 2 is removed to expose the top surface of the floating closed pattern 180. The mask is removed. The process after the pattern 2 is completely the same as the process of the foregoing specific embodiment, and thus the description thereof will be omitted herein. According to a specific embodiment as described above, the device isolation layer pattern is formed prior to the floating gate pattern. The following specific embodiment differs from the foregoing embodiment in that 'the floating closed-pole pattern is formed in advance before forming the device isolation layer pattern, which will be explained with reference to Figs. 25A to 25E and Figs. 26a to 26B. In this document, the descriptions described in the previous paragraph 112311.doc -40-1300608 will be omitted to avoid repetition. Referring to Fig. 25A, a gate insulating layer 140, a floating gate pattern 2 1 〇 and a trench mask pattern 110 are successively formed on a predetermined area of a semiconductor substrate 1 . The trench mask pattern 11 is used as an etch mask to engrave the ΔH semiconductor substrate 1 以 to form a trench 105 defining the active region 1. Thereafter, a device isolation layer 119 for filling the trench 105 is formed on the resultant structure in which a trench 1 〇 5 has been formed. Referring to Figure 25, the device isolation layer pattern 119 is etched until the sidewalls of the trench mask pattern 11 are exposed, thereby forming a device isolation layer pattern 120 to fill the trenches 105. Forming the device isolation layer pattern 12 may include: planarizing the device isolation layer 119 until the trench mask pattern 110 is exposed; and etching the top surface of the device isolation layer pattern 120 until its height is almost equal to the floating gate The top surface height of the pole electrode 2丨〇. Referring to FIG. 25C, the trench mask pattern no is anisotropically patterned to form a mask pattern ΐ5 narrower than the floating gate pattern 21〇.

Referring to FIG. 25D, the floating gate pattern is etched using a mask pattern 11 5 .

The pattern 180 has an inverted T-shaped profile, - the top is unresolved, / is not, which is exactly the same as (column. As a result, the floating gate of the worm is wherein the upper conductive pattern 170 is narrower than the H2311.doc 41 1300608 The lower conductive pattern 155. Thereafter, the top surface of the device isolation layer pattern 12 is recessed until it is twice the same as the top surface height of the gate insulating layer 14A. Referring to FIG. 25E, the floating gate Forming a gate interlayer insulating layer and a gate electrode conductive layer on the pattern such that the layers cover the top surface of the floating gate pattern 180. Thereafter, the closed interlayer insulating layer and the control gate are patterned The layer is formed to form a word line Φ 190 crossing the active area 1 〇 2. The formation of the lacquer word line 190 is identical to the previous embodiment. In the specific embodiment illustrated with reference to Figures 25A to 25E, in Figure 25B After the process is not completed, a spacer may be formed on the sidewall of the trench mask pattern 11 to form a recess on the top surface of the device isolation layer pattern 12A. And 26B are elaborated. In this case Since the shape of the spacer is transferred onto the device isolation layer pattern 120, it is possible to form the device isolation layer pattern 120 lower than the top surface of the active region 1〇2, and it is not necessary to expose the gate insulating layer 14A. • Referring to Figures 26A and 26B, the device isolation layer pattern 12 is recessed to a predetermined depth such that the gate insulating layer 14 is not exposed. Thereafter, an isomorphous formation is formed on the resulting structure. The insulating layer is spaced apart to cover the (four) gate pattern 180, and thereafter, is anisotropically etched: the insulating layer 220 is spaced apart until the top surface of the upper conductive pattern 170 is exposed. At this time, the spacer insulating layer 220 It may be selected from the group consisting of a ruthenium oxide layer, a tantalum nitride layer, a ruthenium oxynitride layer and a metal nitride layer to the + layer. y, "gogogo" forms a buffer and insulation on the lower conductive pattern 155. a layer pattern 112311.doc -42- 1300608 230, and a buffer spacer ', a 'after' on the sidewall of the lower conductive pattern 155, on the resulting structure in which the buffer insulating layer pattern 230 and the buffer spacer 240 have been formed ,form a gate interlayer insulating layer and a control gate conductive layer. Here, the top surface of the device isolation layer pattern 120 is lower than the top surface of the floating gate pattern 180 between the buffer spacers 24? The patterning process is performed to form a word line 19〇 crossing the active area 102. The word line 19 is formed in the same manner as in the previous embodiment. As a result, the buffer insulating layer pattern 230 is inserted into the lower conductive pattern. Between the top surface of 155 and the bottom surface of the gate interlayer insulating layer ι 94. Figures 27A through 27E are cross-sectional views showing a method for fabricating a floating gate of a NAND flash memory in accordance with another embodiment of the present invention. . Referring to Fig. 27A', a gate insulating layer 140, a floating gate pattern 210, and a mask pattern 11 are formed on a semiconductor substrate 1b, and then a trench 105 for device isolation is formed. The semiconductive substrate 100 below the floating gate pattern 21 turns into an active region 102. In detail, a thin film deposition process is performed on the semiconductor substrate 100 to form a gate insulating layer and a conductive layer for the floating gate, the thickness of which is in the range of about 50 angstroms to 100 angstroms. The mask pattern 110 is then formed on the conductive layer for the floating gate to define the trench 105. Thereafter, the mask pattern 11 使用 is used as a rice mask, the conductive layer for the floating gate, the insulating layer, and a portion of the semiconductor substrate 100, thereby forming the floating gate pattern 210, The gate insulating layer pattern 140 and the active region 102. That is, the polarity insulating layer pattern 140 and the floating gate pattern 210 are self-aligned on the active area 1〇2, 112311.doc -43 - 1300608. In this paper, the 兮, 巨, 、, 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 For example, the floating gate pattern 210 can be formed with a polysilicon. Since the thickness of the floating gate pattern 210 determines the height of the floating gate electrode, the floating idle pattern should have an appropriate thickness to take into account the ratio, the interference effect, and the like. The mask pattern 11 can be formed of a material having a selectivity with respect to the stone and the layer of the emulsion. For example, the mask pattern 110 can be formed using tantalum nitride. Referring to FIG. 27B, an insulating layer for device isolation is formed on the resultant structure to cover respective sidewalls of the active region, the dummy insulating layer pattern 14 and the floating gate pattern 2H to be filled for After the trenches 1〇5 of the device are isolated, the insulating layer for device isolation is engraved until the mask pattern u is exposed, thereby forming a device isolation layer 115. The etching process for disposing the isolation insulating layer can be performed by a cMp or an etch back process. The exposed mask pattern ιι〇 is removed with reference to Fig. 27C' to expose the top of the net moving pole pattern 21, and the top surface. Since the mask pattern 110 is provided, the material for etching the gate pattern 210 and the spacer isolation layer is etched 4, 110. Formed, the mask pattern can be selectively removed: the P-knife at the inverted gate 〇0 of the device isolation layer 115 is removed with reference to Figure 27D', such that the floating closed-pole pattern is exposed. Therefore, the top surface of the spacer pattern 120 is lower than the top surface of the case 21G. In this paper, the feed closed-pole diagram is formed by breaking the area covered by the device isolation layer pattern 112311.doc -44 - 1300608 155 (hereinafter referred to as the emperor 〇丨 pattern) and is not isolated by the device. The layer pattern 120 covers the area 1 3 〇 (below, - referred to as the upper pattern in the text). In the floating gate diagram

In the case of the TiO 2 , the lower pattern covered by the rr 里 rr--V isolation layer pattern 120 becomes the lower conduction pattern 155, &amp; ^ ” and the upper pattern 130 is used for an upper conduction of the floating gate electrode. The process of removing the mask pattern 110 by the shellfish, or the process of first performing the part of the device isolation layer 115 is not an important matter. The whistle map 27E 'etches the floating gate pattern 21〇 An upper pattern 130 (which is higher than the device isolation layer pattern 120) to form an upper conductive pattern 170 of the floating gate pattern. Here, the width (w2) of the upper conductive pattern 170 is narrower than the upper pattern 13〇 Width (%). In other words, the width (W2) of the upper conductive pattern 170 is smaller than the width (Wl) of the lower conductive pattern 155, and the lower conductive pattern 155 and the upper conductive pattern 17 are formed (the width of which is smaller than the lower portion) The width of the conductive pattern 155 is configured to be the floating gate (four) 18 〇. For example, the upper pattern 130 can be inscribed by using a wet etching process. Alternatively, it can be used. Money is carved into the gas The upper pattern 130 is left to be engraved, and if the wet etching process is used, the etching solution contains NH4〇H. Meanwhile, since the top surface and the sidewall of the upper pattern GO may be etched using an etching solution, It should be considered that the top surface of the upper pattern 13A is etched to determine the thickness of the original floating gate pattern 2 2 。. Meanwhile, although the side surface of the lower conductive pattern ! 55 is the isolation layer pattern 12 0 Covered and protected, so according to the process conditions, the edge of the top surface can be etched to some extent. In addition, according to the process strip 112311.doc -45-1300608, the side surface of the upper conductive pattern 170 can have vertical, tilt a flat or slightly thick green surface. In addition, the joint portion between the upper conductive pattern 17A and the lower conductive pattern 155 may have a smooth curve. An insulating layer for forming the gate interlayer insulating layer is used for After the conductive layer of the interelectrode electrode is controlled, the conductive layer of the control (four) electrode, the closed interlayer insulating layer and the floating gate pattern 182 are patterned, and then 'The control gate electrode 196 is formed, the gate electrode i96 is formed 'to be placed on the dragon 1G2, and the floating interpole electrode 192 is formed on the control gate electrode 196 and the active region Μ] Each of the intersections. According to the method described with reference to Figures 27A to 559, the floating-electrode electrode is self-aligned on the active region. For example, t, the floating open electrode is formed 'to make the floating gate electrode The width of the lower conductive pattern is substantially equal to the width of the active region. In the method described above with reference to FIGS. 27A to 27E, after forming the trench |〇5, before the formation process of the device isolation layer , a thermal oxidation can be carried out to solve the damage caused by the engraving process (4) of forming the trench. In this case, the edge of the active region 1〇2 is subjected to orbital oxidation such that the thickness of the dummy insulating layer formed at the edges of the active region 1〇2 is relatively thicker than the other regions of the region 1〇2. In the method described with reference to Figs. 27A to 27E, the floating gate pattern can prevent the top surface of the upper pattern 130 from being etched. For this purpose, the removal process between the mask pattern UG and the device isolation layer 115 can be imposed: 112311.doc -46- 1300608 The process sequence between the engraving processes. For example, t can be performed in the state in which the mask pattern 11 is not removed from the top surface of the floating gate pattern 210, and the upper pattern 13 of the floating gate pattern 210 is subjected to an etching process. Description will be made with reference to Figs. 28A to 28C. First, the processes of Figs. 27A and 27B are performed to form a floating gate pattern 210, a gate insulating layer 14A, a mask pattern ιι, and a device isolation layer 115. Referring to FIG. 28A, a portion of the device isolation layer 115 in the inverted gate region is etched such that a side surface of the floating gate pattern 210 is exposed, thereby forming a top portion of the device isolation layer pattern 12 The surface is lower than the top surface of the floating gate pattern 210. Herein, the top surface of the floating gate pattern 210 is covered by the mask pattern 11A. Referring to FIG. 28B, the side surface of the exposed floating gate pattern 21 of the upper pattern 130 is etched to reduce its width, thereby forming the upper conductive germanium pattern. In the embodiment of the present invention, the upper portion is not etched. The top surface of the pattern 13 is different from the method described with reference to Figures 27A to 27E. Thereafter, the mask pattern 110 is removed as shown in FIG. 28C. For the embodiment of Figures 27A through, the top surface of the upper pattern can be etched such that the top surface edge of the upper conductive pattern can be formed as a smooth curve/shape, as opposed to the embodiment of Figures 27A through 27E. In the specific embodiment of FIGS. 28-8 to 28C, the top surface of the upper pattern is not engraved due to the mask pattern, so the top surface edge of the upper conductive pattern may be formed into an angular shape. According to the invention, the gate of the selective transistor has a box-shaped cross section and in another region has an inverted τ-shaped cross section. Since &, it is possible to embody H2311.doc -47· 1300608 (4) t μ e with enhanced punch-through characteristics and $(4). According to the present invention, since the memory is electrically inverted, the selection of the electric gate is broken into When the gate portion of the electrified body is controlled to be closed by the pattern, it is possible to prevent the formation of the selection electrode, so that the action area is damaged by the button. 4 Selecting the region of the electrode body According to the invention, the floating closed electrode has a cross-sectional area of the inverted τ ::::::: electrode, making it possible to most: two: =::17 surface area of the idle electrode Process margin, and thus the effect. As a result, the non-volatile: two-motion=pole interference acoustic concealment device of the present invention can overcome the problem of high placement of 5 households, such as electrical interference and coupling ratio degradation. Inverted T-shaped profile, so it can be increased, the distance between the conductive patterns above the floating gate electrode, wherein the floating-electrode electrodes are adjacent to each other in the direction in which the control electrode extends. Controlling interference between floating gate electrodes adjacent to each other in the direction in which the gates extend. y Other characteristics, advantages, or effects are understood from the drawings and related descriptions. It is to be understood by those skilled in the art that the present invention may be Modifications and variations of the present invention within the scope of the appended claims and equivalents thereof are intended to cover various modifications and variations. The present invention is used to explain the principles of the present invention in order to provide the present invention, which is a part of the specification, and is incorporated in and incorporated by reference. : Figure 1 shows according to this 1 is a schematic plan view of a NAND flash memory device of a specific embodiment; FIG. 2 is a partially enlarged view of a region of reference numeral 9 绿 in a green diagram, the region J is in a portion where a memory transistor is formed A boundary region between a region 10 and a second region 20 where a selective transistor is formed; FIGS. 3 to 8 respectively show 1-1, ΙΙ-ΙΓ, πι-in, and IV along FIG. A cross-sectional view of the IV, VV, and VI-VI' lines; FIG. 9A is a schematic cross-sectional view of the floating gate electrode as an example of the direction of extension of the control gate according to the present invention; A perspective view of the arrangement of the floating idle electrode according to the present invention - a typical embodiment of the present invention is shown in FIGS. 11 to 18 of the present invention. FIG. 19 is a cross-sectional view of a 5 memory cell of a flash memory device according to the present invention. FIG. 20 is a schematic view of the memory device of the N flash memory device; A cross-sectional view according to the present invention; a flash memory device 轭21 of the yoke example, a day according to another aspect of the present invention FIG. 22A to 22H illustrate a cross-sectional view of a method for fabricating a straight body according to the present invention—and implementing a NAND flash memory device; 112311.doc •49 - j3〇〇6〇8 FIGS. 23A to 23B illustrate another embodiment of the NAND flash memory device according to the present invention for use in the drawing of FIG. 2 4 to 2 4 B, which is illustrated in accordance with the present invention. FIG. 25A to FIG. 25E are diagrams for illustrating a method for fabricating a NAND flash memory device according to another embodiment of the present invention. FIG. 26A to FIG. 26B show another embodiment of the NAND flash memory device according to the present invention; FIG. 27Α to 27Ε illustrate according to the present invention; Invention#Body Example> m is a cross-sectional view of a floating NAND flash memory device for making a τ gate and a square; FIGS. 28A to 28C illustrate another embodiment according to the present invention. Example > A floating gate of a NAND flash memory device is used to make a sectional view of the main component symbol description z. Figure 1 to Figure 18 Symbol Description 10 = One area (where the memory transistor is formed) 20 Second area (where the selected transistor is formed) 30 Semiconductor substrate 40 Device isolation layer pattern (device isolation layer) 50 Action area 60 inverted τ-shaped gate region 70 butt contact (butt contact area) 80 box-shaped gate region 90 region (between 112311.doc -50- 1300608 forming a memory transistor)

a boundary region between a region 10 and a second region 20 where a selective transistor is formed) 100 selects a transistor 110 a first insulating layer 130 a first gate 131 a horizontal portion 133 of the first portion 135 of the first gate 130 The vertical portion 135 of the first portion 135 of the gate 130 selects the first portion 137 of the first gate 130 of the transistor 100. The second portion of the first gate 13 of the transistor 1 is selected. Gate 191S/D, 193S/D, impurity region 291S/D 200 memory transistor 210 tunneling insulation layer 2305 230? floating gate (floating gate electrode) 231, 231' horizontal portion 233 of floating gate 230, 233* floating gate 2 3 0 vertical portion 250 gate interlayer insulating layer 270 control gate 300 substrate 400 spread isolation layer pattern 112311.doc 51 1300608

410 lower device isolation layer pattern 500 active region 600 first insulating layer 700 first conductive pattern (first conductive layer pattern) 710 narrowed first conductive pattern 730 remaining first conductive pattern 800 mask 900 second insulating layer 1000 Two conductive layers 1100a, 1100b gate mask CSL common source line DC bit line contact (drain contact) GSL ground select line (second select line) SSL string select line (first select line) WLO ~ WLn word line D2 Distance between horizontal parts d3 Distance between vertical parts hi Thickness of horizontal part h2 Thickness of vertical part Si Cross-sectional area of horizontal part S2 Cross-sectional area of vertical part S3 Face area Stotal Total facing area W1? W ]* The width of the horizontal portion 112311.doc -52- 1300608 w2, w2' The width of the vertical portion FIG. 19 to FIG. 28 The symbol description 100 The semiconductor substrate 102 The active region 105 The trench 110 The trench mask pattern (mask pattern) 112 Pad oxide layer pattern

114 Mask nitride layer pattern (mask nitride pattern) 115 Mask pattern (Fig. 25) 115 Device isolation layer (Fig. 27) 119 Device isolation layer (device isolation layer pattern) 120 Device isolation layer pattern 130 Clearance region 130 Upper portion Pattern (Fig. 27) 140 Gate insulating layer 150 Conductive interstitial pattern 155 Lower conductive pattern 160 Mold layer 165 Mode spacer 165r Remaining mold spacer 170 Upper conductive pattern 180 Floating gate pattern 190 Stacked gate structure (word line) 192 floating gate electrode 112311.doc -53 - 1300608 194 gate interlayer insulating layer 196 control gate electrode 200 mask pattern 210 floating gate pattern 220 spacer insulating layer 230 buffer insulating layer pattern 240 buffer spacer W] lower conductive pattern Width W 155 width of upper conductive pattern 170 112311.doc -54-

Claims (1)

1300608 X. Patent Application Range: 1. A semiconductor device comprising: - a first gate formed on an active region of a substrate, wherein the active region is defined by a device isolation layer pattern; - a first insulation a layer formed between the first gate and the active region; and first and second impurity regions formed on the active regions on both sides of the first gate, wherein adjacent to the layer A cross-sectional shape of a first portion of the first gate of the first impurity region is different from a cross-sectional shape of a second portion of the first gate adjacent to the second impurity region. 2. The semiconductor device of claim 1, wherein the first portion of the first gate substantially has an inverted T-shaped profile when crossing the active region and one of the device isolation layer patterns. The second portion of the first gate has a box-shaped cross section. The semiconductor device of claim 2, wherein the concentration of the first impurity region is lower than the concentration of the second impurity region. 4. The semiconductor device of claim 2, wherein a channel doping concentration of the substrate under the first portion of the first gate is higher than a channel doping of the substrate under the second portion of the first gate Miscellaneous concentration. 5. The semiconductor device of claim 2, further comprising: a second insulating layer formed on the first gate; a second gate penetrating the second insulating layer such that it is electrically connected to the a first gate; and 112311.doc 1300608 a brother recall body gate, which is sequentially stacked on the active region, a tunnel insulation layer, a floating gate, a gate interlayer insulation layer and a control gate The pole is configured, wherein the memory gate is separated from the first gate. 6. The semiconductor device of claim 5, wherein the floating gate has an inverted τ-shaped profile when crossing the active region and one of the device isolation layer patterns. 7. The semiconductor device of claim 6, wherein a height of the device isolation layer pattern adjacent to the floating gate of the memory gate is lower than a pattern of the device isolation layer adjacent to the first gate height. 8. The semiconductor device of claim 6, wherein the first gate and the floating gate are formed from the same layer, and the second insulating layer and the gate interlayer insulating layer are formed from the same layer, and the The second gate and the control gate are formed from the same layer. 9. The semiconductor device of claim 6, wherein a height of a top surface of the device isolation layer pattern adjacent to the floating gate is substantially equal to a height of a top surface of the horizontal portion of the floating gate. 10. A NAND flash memory device, comprising: a selective transistor formed on an active region of a substrate, wherein the 5 Hz active region is defined by a device isolation layer pattern; and a plurality of memory transistors Forming on the active region, the plurality of &quot;resonant transistors are connected in series to the selective transistor, wherein the selective transistor and each of the plurality of memory transistors comprise a stacked gate structure, wherein the stacked gate structure is sequentially formed on the active region, a first insulating layer, a first gate, a third layer, a second insulating layer, and a second The gate is configured to excite the cross-sectional shape of the first gate of the group of crystals - the selected transistor of the memory of the memory of the memory is: identical to the cross-sectional shape adjacent to the record, and in the memory The electro-optic - the first gate of the first-part body - the second portion of the selected electro-crystal 1 曰 - '. The face shape is different from the section of the (four)th gate of the selected electric B body. U·If the NAND flash memory version of claim 10 is placed in the direction of the intersection between the active area and the device, the memory of the second body of the memory A closed pole has an inverted τ-shaped cross section, and the second portion of the first gate of the selective transistor has a box-shaped cross section. 12. The cryptic flash memory device of claim U, wherein a height of the device isolation layer (4) adjacent to the first idle electrode of the memory transistor is lower than a height adjacent to the selected transistor The height of the device isolation layer pattern of a gate. For example, a request is made for a blazing flash memory device, wherein a top surface of the device isolation layer pattern adjacent to the first gate of the memory transistor is substantially equal to one of the memory transistors The top surface height of the box-shaped horizontal portion of one of the first gates of the τ shape. The NAND flash memory device of claim 11, wherein a concentration of the impurity region of the first portion of the first gate adjacent to the selection transistor is lower than the first adjacent to the selection transistor The concentration of the impurity region of the second portion of the gate. The NAND flash memory device of claim 11, wherein the channel of the substrate under the first portion of the first gate of the selected transistor is doped with 112311.doc j3〇〇6〇^ A channel doping concentration of the substrate that is higher than the second portion of the first inter-electrode of the selected transistor. 16. A method of fabricating a semiconductor device, the method comprising: forming a first insulating layer and a first conductive layer pattern on an active region of the substrate, wherein the active region is patterned by a device isolation layer Defining; etching a portion of the device isolation layer pattern downward to form a lower device isolation layer pattern, the lower device isolation layer pattern covering a side surface of one of the lower patterns of the first conductive pattern; The side surface of the upper pattern of one of the conductive layer patterns is formed to form a narrowed upper portion, and the width of the upper pattern of the access pattern is smaller than the width of the lower pattern of the first conductive pattern , wherein the first conductive pattern is on. The pattern of 5 is upwardly protruded above the lower device isolation layer pattern, and the first core pattern having the lower pattern and the narrowed upper pattern is formed to form a first portion and a second portion: a pole, wherein the first portion is patterned from the lower pattern and from the upper pattern, and the first conductive pattern is patterned from the adjacent isolation layer of the device And the first and second impurity regions are adjacent to the first portion and the second portion of the gate. 1 7 · If the request item 1 6··, +, before: further includes 'the first conduction 112311.doc in the pattern of the predetermined σ卩 forming the first gate and the narrowed upper pattern! Forming a second insulating layer on the pattern of 3〇〇6°8; and forming a second conductive layer, which penetrates the insulating layer, wherein the mth is electrically connected to the second j-. Up to the first conductive pattern, the conductive pattern of the first conductive pattern includes: by patterning the second; transferring the second insulating layer 'from the first/de-V layer electrically connected to the first-closed pole A second gate. Step 0: According to the method of claim 17, a conductive layer, the second one...: when the wrong pattern is patterned by the second $°°-th conductive layer, forming an electrical connection to the first brother and the gate The second gate is connected to a floating gate which is separated from the first-shaped cross section of the first-level electrode, and a gate electrode formed from the second surface having a vertical edge layer; The insulating layer and the second pass layer from the second pass layer are from the first conduction: 'Λw pole' where it is formed.曰 "The lower pattern and the upper pattern 19 = method of making a AND flash memory device, the method comprising: forming a guiding layer pattern on an active area of the substrate, wherein the active area is - the device isolation layer pattern is defined; the etched one direction of the substrate is etched down to form the substrate - one of the memory transistors is "...the case is formed - the lower device isolation layer is patterned, the lower 4 device isolation layer The pattern covers one of the first-conducting maps:: the case-side surface; the guardian (2) the lower part of the millet «the first-conducting layer pattern is an upper part of the pattern - narrowing the upper part pattern, the narrowing heart, the 阋The width of the lower pattern of the first conductive pattern is smaller than the width of the lower pattern of the first conductive pattern, wherein the upper conductive pattern of the first conductive pattern protrudes upward and is higher than the lower device isolation layer pattern; Forming a second insulating layer and a second conductive layer on the pattern of the lower device isolation layer and the first conductive layer pattern; and &gt; patterning the first conductive layer, the second insulating layer, and the first Conductive 曰 to the side Forming a gate of the memory transistor from the second conductive layer in a region, forming the memory transistor &amp; gate interlayer insulating layer from the second insulating layer, and patterning from the first conductive layer The lower and upper patterns form a floating gate of the memory transistor, wherein the control idle pole of the memory transistor extends in a second direction perpendicular to the first direction and intersects with the ##^m The immersion zone and the lower device isolation layer pattern are 〇Λ20. According to the method of claim 19, the second electrode is formed at the body transistor (4) the substrate is formed by the memory to etch the substrate into a layer 2... Setting the isolation layer pattern includes forming a selective transistor isolation layer pattern downwardly, and the device and the first transmission are: the first conductive layer and the second transistor - the choice of the second direction extension ^ L Η times in the weight of the 筮 - „ 1 in: ! into the selection of the transistor - the first - pole, :: the role of the pole:: the second division of the The lower part of the isolation layer is slaughtered, and the two pole crossing cases and the 垓 effect A. / Shame opposing spacer layer FIG H2311.doc