CN115274832A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN115274832A CN115274832A CN202210725186.1A CN202210725186A CN115274832A CN 115274832 A CN115274832 A CN 115274832A CN 202210725186 A CN202210725186 A CN 202210725186A CN 115274832 A CN115274832 A CN 115274832A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
The application relates to a semiconductor structure and a preparation method thereof. The semiconductor structure includes: the transistor structure comprises a transistor and a first dielectric layer, the transistor is positioned in the first dielectric layer and comprises a semiconductor column and a grid structure at least partially surrounding the semiconductor column, a source region or a drain region is formed at the top of the semiconductor column, a groove is formed in the first dielectric layer, and the groove is exposed out of the top of the semiconductor column; the metal silicide is positioned in the groove; the electrode layer is positioned on the metal silicide and fills the groove; and the storage structure is positioned on the electrode layer. The embodiment of the application can effectively reduce the contact resistance between the transistor and the storage structure, thereby increasing the driving current of the transistor.
Description
Technical Field
The present disclosure relates to integrated circuit technologies, and more particularly, to a semiconductor structure and a method for fabricating the same.
Background
VGAA (Vertical Gate-All-Around) transistors, the entire channel outer profile is completely surrounded by the Gate. Under the same size structure, the gate of the VGAA transistor has stronger channel control capability compared with other transistors. Therefore, the size of the VGAA transistor can be further scaled down. Therefore, the VGAA transistor is more suitable for the development requirement of a high-density memory device.
Meanwhile, as the feature size of semiconductors shrinks, the driving current provided by transistors is affected.
Disclosure of Invention
Based on this, embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, which can effectively reduce contact resistance between a transistor and a memory structure, thereby increasing a transistor driving current.
A semiconductor structure, comprising:
the transistor structure comprises a transistor and a first medium layer, the transistor is positioned in the first medium layer, the transistor comprises a semiconductor column and a grid structure at least partially surrounding the semiconductor column, a source region or a drain region is formed at the top of the semiconductor column, a groove is formed in the first medium layer, and the groove is exposed out of the top of the semiconductor column;
the metal silicide is positioned in the groove;
the electrode layer is positioned on the metal silicide and fills the groove;
and the storage structure is positioned on the electrode layer.
In one embodiment, the semiconductor pillar is formed on a semiconductor substrate, and an orthogonal projection of the semiconductor pillar on the substrate overlaps with an orthogonal projection of the groove on the substrate or is located inside the orthogonal projection of the groove on the substrate.
In one embodiment, the semiconductor pillar is formed on a semiconductor substrate, and an orthogonal projection of the groove on the substrate is located inside an orthogonal projection of the storage structure on the substrate.
In one embodiment, the semiconductor structure further comprises:
and the metal barrier layer is positioned between the electrode layer and the metal silicide.
In one embodiment, the metal barrier layer extends from the groove to the first dielectric layer.
In one embodiment, the metal silicide surface has a concave-convex structure.
In one embodiment, the semiconductor structure further comprises:
the isolation protective layer covers the storage structure and the first dielectric layer;
the second dielectric layer is positioned on the isolation protective layer;
the conductive plug penetrates through the second dielectric layer and the isolation protection layer and is connected with the top of the storage structure;
and the metal layer is positioned on the second dielectric layer and is connected with the conductive plug.
A method of fabricating a semiconductor structure, comprising:
providing a transistor structure, wherein the transistor structure comprises a transistor and a first dielectric layer, the transistor is positioned in the first dielectric layer, the transistor comprises a semiconductor column and a grid electrode structure at least partially surrounding the semiconductor column, and a source region or a drain region is formed at the top of the semiconductor column;
forming a groove in the first dielectric layer, wherein the groove exposes the top of the semiconductor column;
forming metal silicide in the groove;
forming an electrode layer on the metal silicide to fill the groove;
and forming a storage structure on the electrode layer.
In one embodiment, the forming of the metal silicide in the groove includes:
forming a metal material layer on the surface of the first dielectric layer and in the groove;
carrying out heat treatment on the metal material layer to form the metal silicide in the groove;
and removing the unreacted metal material layer.
In one embodiment, the semiconductor pillar is formed on a semiconductor substrate, and an orthogonal projection of the semiconductor pillar on the substrate is overlapped with an orthogonal projection of the groove on the substrate or is positioned inside the orthogonal projection of the groove on the substrate.
In one embodiment, the semiconductor pillar is formed on a semiconductor substrate, and an orthogonal projection of the recess on the substrate is located inside an orthogonal projection of the storage structure on the substrate.
In one embodiment, after the forming the metal silicide in the groove, the method further includes:
and carrying out graphical processing on the metal silicide so as to form a concave-convex structure on the surface of the metal silicide.
In one embodiment, after forming the metal silicide in the groove and before forming the electrode layer on the metal silicide, the method further includes:
and forming a metal barrier layer in the groove.
In one embodiment, the metal barrier layer is formed on the upper surface of the first dielectric layer while the metal barrier layer is formed in the groove.
In one embodiment, the forming a groove in the first dielectric layer further includes:
removing the first dielectric layer above the semiconductor pillar to enable the upper surface of the first dielectric layer to be flush with the top surface of the semiconductor pillar;
and back-etching the top of the semiconductor column to form the groove in the first dielectric layer.
In one embodiment, after the forming the memory structure on the electrode layer, the method further includes:
forming an isolation protection layer covering the storage structure and the first dielectric layer;
forming a second dielectric layer on the isolation protection layer;
forming an interconnection through hole penetrating through the second dielectric layer and the isolation protection layer, and forming a conductive plug in the interconnection through hole;
and forming a metal layer on the second dielectric layer, wherein the metal layer is connected with the conductive plug.
According to the semiconductor structure and the preparation method thereof, the groove exposing the top of the semiconductor column is formed in the first dielectric layer. And forming metal silicide in the groove first, and then forming an electrode layer. At this time, the contact resistance between the drain region (or the source region) and the memory structure can be effectively reduced by the metal silicide and the electrode layer. And the electrode layer and the metal silicide are simultaneously formed in the groove, so that the size of the device can be accurately controlled.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings needed to be used in the description of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without any creative efforts.
FIG. 1 is a flow chart of a method of fabricating a semiconductor structure provided in one embodiment;
FIGS. 2-12 are schematic diagrams of cross-sectional structures during fabrication of a semiconductor structure provided in an embodiment;
FIGS. 13-16 are cross-sectional structural diagrams of semiconductor structures fabricated in various embodiments;
FIG. 17 is a schematic cross-sectional structure diagram of a semiconductor structure provided in another embodiment during fabrication thereof;
fig. 18 is a schematic cross-sectional view of a semiconductor structure provided in yet another embodiment during fabrication thereof.
Description of reference numerals:
100-transistor structure, 110-transistor, 111-semiconductor column, 112-gate structure, 120-first dielectric layer, 200-metal silicide, 300-electrode layer, 400-memory structure, 401-isolation layer, 402-phase change memory cell bottom electrode, 403-phase change layer, 404-phase change memory cell top electrode, 405-ferroelectric memory cell bottom electrode ferroelectric layer, 406-ferroelectric layer, 407-ferroelectric memory cell top electrode, 41-resistance change memory cell bottom electrode layer, 42-insulation layer, 43-resistance change memory cell top electrode layer, 410-pinning layer, 420-tunnel junction, 430-free layer, 500-metal material layer, 600-metal barrier layer, 700-isolation protection layer, 800-second dielectric layer, 900-conductive plug, 1000-metal layer, 10-mask material, 20-patterned photoresist.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to, or coupled to the other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
Spatial relational terms, such as "under," "below," "under," "above," "over," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the terms "spatial relationship" and "spatial relationship" encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
Therefore, the structure of the embodiments of the present application should not be limited to the specific shapes shown in the drawings of the specification, but include deviations in shapes resulting from, for example, manufacturing techniques.
As background art appears, the drive current provided by VGAA transistors is affected as the semiconductor feature size shrinks.
Specifically, for example, a Magnetic Random Access Memory (MRAM) is one of new nonvolatile Random Access memories based on the principle of modulating the magnitude of Magnetic resistance. MRAM, as a nonvolatile memory, has a read/write speed comparable to that of a volatile memory DRAM. And the standby power consumption of the MRAM is far less than that of the DRAM, and the MRAM has the potential of replacing the DRAM in the future.
A memory cell of an MRAM generally includes one transistor and one Magnetic Tunnel Junction (MTJ). To implement DRAM-like applications, transistors are required to be small in size and to have high drive currents to drive the magnetic tunnel junction switching.
For another example, a plurality of novel technologies represented by Phase Change Random Access Memory (PCRAM) have attracted attention due to their characteristics of high integration level, low power consumption, and the like. In particular, PCRAMs have the potential to serve as both main and external memory due to their non-volatile, byte-addressable, and like characteristics. Under its influence, the boundary between main memory and external memory is also becoming increasingly blurred, and even there are changes that may bring about a significant revolution in future storage architectures. Thus, PCRAM is considered one of the new technologies that have a great development prospect, most likely to completely replace DRAM.
A PCRAM data storage operation requires a certain drive current. However, as semiconductor devices are scaled down, the transistor driving current decreases, which results in the inability to maintain the original driving capability.
For another example, for Ferroelectric Random Access Memory (FeRAM) and Resistive Random Access Memory (RRAM), the feature size of semiconductor process is continuously reduced to meet the requirement of high-density architecture. At this time, the sizes of the gate, source and drain active regions of the transistors in the memory cells are also reduced correspondingly, so that the drive current of the transistors is restrained from increasing, and the memory can not be driven to work.
Based on the above, the present application provides a semiconductor structure and a method for manufacturing the same, so as to improve the current driving capability of a transistor gate. The semiconductor structure may include, but is not limited to, a magnetic memory, a phase change memory, a ferroelectric memory, a resistive random access memory, or the like. The transistor may include but is not limited to a VGAA transistor.
In one embodiment, referring to fig. 1, a method for fabricating a semiconductor structure is provided, which includes the steps of:
step S100, providing a transistor structure 100, where the transistor structure 100 includes a transistor 110 and a first dielectric layer 120, the transistor 110 is located inside the first dielectric layer 120, the transistor 110 includes a semiconductor pillar 111 and a gate structure 112 at least partially surrounding the semiconductor pillar 111, and a source region or a drain region is formed at the top of the semiconductor pillar 111, please refer to fig. 2;
step S300, forming a groove 120a in the first dielectric layer 120, wherein the groove 120a exposes the top of the semiconductor pillar 111, please refer to fig. 3;
step S500, forming a metal silicide 200 in the recess 120a, please refer to fig. 5;
step S700, forming an electrode layer 300 on the metal silicide 200 to fill the recess 120a, please refer to fig. 8;
in step S900, a memory structure 400 is formed on the electrode layer 300, please refer to fig. 11.
In step S100, referring to fig. 2, in the formation process of the transistor structure 100, a semiconductor substrate 10 may be provided first. The substrate 10 may include, but is not limited to, a silicon (Si) substrate 10, a silicon germanium (GeSi) substrate 10, or a Silicon On Insulator (SOI), etc. Meanwhile, the substrate 10 may be a P-type substrate 10, or may be an N-type substrate 10.
Then, the substrate 10 may be etched, thereby forming vertical semiconductor pillars 111 on the substrate 10. Thereafter, a gate structure 112 is formed to fully surround or partially surround the semiconductor pillar 111. At this time, the gate structure 112 entirely surrounds the semiconductor pillar 111, or the gate structure 112 partially surrounds the semiconductor pillar 111. That is, the gate structure 112 at least partially surrounds the semiconductor pillar 111.
The top and bottom of the semiconductor pillar 111 are heavily doped to form a source region and a drain region, respectively. Specifically, the top of the semiconductor pillar 111 may form a source region, and may also form a drain region.
It is understood herein that the gate structure 112 may include a gate dielectric layer as well as a gate conductive layer. The gate dielectric layer can be formed by using a material with a low k dielectric constant, and can also be formed by using a material with a high k dielectric constant.
During the formation of the transistor structure 100, a first dielectric layer 120 may also be formed. Referring to fig. 2, a first dielectric layer 120 may be filled between the semiconductor pillars 111 and completely cover the transistor 110.
Specifically, first dielectric layer 120 may include, but is not limited to, silicon oxide (SiO)2) Layer, silicon nitride (Si)3N4) Layer, alumina (Al)2O3) A layer or a silicon oxynitride (SiON) layer.
By way of example, first dielectric layer 120 may include multiple film layers of the same or different materials. Multiple film layers may be formed in different process steps.
In step S300, please refer to fig. 3, which may include, as an example:
step S310, removing the first dielectric layer 120 above the semiconductor pillar 111 to make the upper surface of the first dielectric layer 120 flush with the top surface of the semiconductor pillar 111;
in step S320, the top of the semiconductor pillar 111 is etched back to form a recess 120a in the first dielectric layer 120.
Specifically, the first dielectric layer 120 above the semiconductor pillar 111 may be removed by performing chemical mechanical polishing and/or etching on the first dielectric layer 120, so that the upper surface of the first dielectric layer 120 is flush with the top surface of the semiconductor pillar 111.
Then, the top (drain region or source region) of the semiconductor pillar 111 may be etched back, thereby forming the recess 120a. The recess 120a exposes the top (drain or source) of the semiconductor pillar 111 after the etch back. At this time, the recess 120a may be precisely aligned with the top (drain or source) of the semiconductor pillar 111.
Of course, the groove 120a may be formed in other manners. For example, first dielectric layer 120 may be etched to form recess 120a in first dielectric layer 120.
Specifically, a photoresist may be first coated on the first dielectric layer 120, and then a patterned photoresist may be formed on the first dielectric layer 120 through processes of exposure, development, and the like. The patterned photoresist has openings opposite the semiconductor pillars 111. Then, the patterned photoresist is used as a mask to etch the first dielectric layer 120 until the top of the semiconductor pillar 111 is exposed, thereby forming a recess 120a in the first dielectric layer 120.
By etching the first dielectric layer 120, the first dielectric layer 120 may be thinned before the groove 120a is formed in the first dielectric layer 120, so as to control the depth of the subsequently formed groove 120a.
In step S500, referring to fig. 5, the material of the metal silicide 200 may be TiSi, coSi, or NiPtSi. After the metal silicide 200 is formed in the recess 120a, the recess 120a is not filled with the metal silicide 200, i.e., there is still room in the recess 120a.
In step S700, referring to fig. 8, an electrode layer 300 is formed on the metal silicide 300 in the recess 120a, thereby filling the recess 120a.
The material of the electrode layer 300 may include, but is not limited to, metal materials having good conductivity such as Co, ni, ti, W, cu, al, and the like.
In step S900, the memory structure 400 may include, but is not limited to, any one or more of a magnetic random access memory structure (see fig. 13), a phase-change random access memory structure (see fig. 14), a ferroelectric random access memory structure (see fig. 15), and a resistive random access memory structure (see fig. 16).
Referring to FIG. 13, when the memory structure 400 includes a magnetic random access memory structure, it may include a free layer 430, a tunnel junction 420, and a pinned layer 410.
Referring to fig. 14, when the memory structure 400 includes a phase change random access memory structure, it may include a 401 isolation layer, a 402 phase change memory cell bottom electrode, a 403 phase change layer, and a 404 phase change memory cell top electrode.
Referring to fig. 15, when memory structure 400 includes a ferroelectric random access memory structure, it may include 405 a ferroelectric memory cell bottom electrode, 406 a ferroelectric layer, and 407 a ferroelectric memory cell top electrode.
Referring to fig. 16, when the memory structure 400 includes a resistive random access memory structure, it may include a resistive memory cell bottom electrode layer 41, an insulating layer 42, and a resistive memory cell top electrode layer 43. In the formation of the memory structure 400, the materials of the film layers of the memory structure 400 may be first formed on the upper surface of the electrode layer 300 and the upper surface of the first dielectric layer 120. Then, the material of each layer is patterned, so as to form the memory structure 400 on the electrode layer 300.
For example, when the memory structure 400 comprises a magnetic random access memory structure, it comprises a Magnetic Tunnel Junction (MTJ). At this time, referring to fig. 9, a pinned layer material 411 may be first formed on the upper surface of the electrode layer 300 and the upper surface of the first dielectric layer 120. Tunnel junction (tunnel barrier) material 421 is then formed over the pinned layer material. Then a Free layer material 431 is formed over the tunnel junction material.
Thereafter, referring to fig. 10, a masking material 20 may be formed on the free layer material, and a patterned photoresist 30 may be formed on the masking material 20. Then, the mask material 20 is patterned by photolithography, etching, or the like to form a mask layer. Then, the patterned photoresist 30 is removed, and the free layer material, the tunnel junction material, and the pinned layer material are sequentially etched based on the mask layer, thereby forming a free layer 430, a tunnel junction 420, and a pinned layer 410, as shown in fig. 11. The free layer 430, the tunnel junction 420, and the pinned layer 410 constitute a magnetic tunnel junction.
In the present embodiment, a recess 120a exposing the top of the semiconductor pillar 111 is formed in the first dielectric layer 120. And a metal silicide 200 is formed in the recess 120a, and then an electrode layer 300 is formed. At this time, the contact resistance between the drain region (or the source region) and the memory structure 400 may be effectively reduced by the metal silicide 200 and the electrode layer 300. Also, the electrode layer 300 is formed in the groove 120a simultaneously with the metal silicide 200, so that precise control of the device size is possible.
In one embodiment, step S500 includes:
step S510, referring to fig. 4, forming a metal material layer 500 on the surface of the first dielectric layer 120 and in the groove 120 a;
step S520, please refer to fig. 5, in which the metal material layer 500 is heat-treated to form a metal silicide 200 in the recess 120 a;
in step S530, please refer to fig. 5, the unreacted metal material layer 500 is removed.
In step S510, specifically, a metal material layer 500 may be formed on the upper surface of the first dielectric layer 120 and in the groove 120a by magnetron sputtering or electroplating. The material of the metallic material layer 500 may include Ti, co, or NiPt, etc.
In step S520, the metallic material layer 500 may be heat-treated by annealing. During the heat treatment, the metal material layer 500 reacts with the interdiffusion of atoms (silicon is the main diffusion) in the tops of the semiconductor pillars 111, thereby forming the metal silicide 200.
Thereafter, in step S530, the unreacted metal material layer 500 may be removed by etching.
As an example, an orthogonal projection of the semiconductor pillar 111 on the substrate 10 may be provided to overlap an orthogonal projection of the groove 120a on the substrate 10. Alternatively, the orthogonal projection of the semiconductor pillar 111 on the substrate 10 is located inside the orthogonal projection of the recess 120a on the substrate 10.
At this time, the top surface of the semiconductor pillar 111 is covered by the metal material layer 500, so that the metal material layer 500 reacts with the top surface of the semiconductor pillar 111 to form the metal silicide 200, and the contact resistance between the formed metal silicide 200 and the semiconductor pillar 111 can be effectively reduced.
In one embodiment, the orthographic projection of the recess 120a on the substrate 10 is located inside the orthographic projection of the storage structure 400 on the substrate 10.
The larger the contact area of the memory structure 400 with the electrode layer 300, the smaller the resistance. Therefore, the resistance can be further reduced at this time.
In one embodiment, after step S500, the method further includes:
in step S610, a patterning process is performed on the metal silicide 200 to form a concave-convex structure on the surface of the metal silicide 200.
Specifically, a photoresist layer may be coated on the upper surface of the first dielectric layer 120 and the top surface of the metal silicide 200, and through a series of steps such as exposure and development, a patterned photoresist layer is formed. Then, the top (drain region or source region) of the metal silicide 200 is etched based on the patterned photoresist layer to form a concave-convex structure. Then, the photoresist layer is removed.
The shape and size of the concave-convex structure can be set according to requirements.
As an example, referring to fig. 17, the concave-convex structure may be formed by removing two opposite side edges (e.g., front and rear edges or left and right edges) of the top of the metal silicide 200, or by removing all the peripheral edges of the top of the semiconductor pillar 111, so that the central portion protrudes upward.
Alternatively, referring to fig. 18, the concave-convex structure may be formed by removing a central portion of the metal silicide 200, so that the metal silicide 200 is recessed.
Of course, the form of the concave-convex structure is not limited thereto, and it may also be, for example, a saw-tooth shape, a wave shape, or the like.
In this embodiment, the concave-convex structure can effectively increase the contact area between the metal silicide 200 and the structures on both sides thereof, thereby further reducing the contact resistance.
In one embodiment, after step S500 and before step S700, the method further includes:
in step S620, referring to fig. 6, a metal barrier layer 600 is formed in the recess 120a.
At this time, the metal barrier layer 600 may be formed on the sidewalls of the recess 120a and the surface of the metal silicide 200.
The metal barrier layer 600 may include, but is not limited to, at least one of a titanium nitride layer, a cobalt layer, a platinum layer, and a titanium tungsten layer.
The metal barrier layer 600 is formed before the electrode layer 300, so that the problem of metal diffusion in the electrode layer 300 can be effectively prevented.
For example, referring to fig. 6, while forming the metal barrier layer 600 in the recess 120a, the metal barrier layer 600 is also formed on the upper surface of the first dielectric layer 120.
Specifically, the metal barrier layer 600 may be formed on the upper surface of the first dielectric layer 120 and the recess 120a by chemical vapor deposition.
The chemical Vapor Deposition method may specifically include an Atomic Layer Deposition (ALD) method, a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, and the like.
At this time, the metal barrier layer 600 can better prevent the metal in the electrode layer 300 from diffusing into the first dielectric layer 120, so as to effectively prevent the adjacent transistors 110 from interfering with each other.
Meanwhile, after the metal barrier layer 600 is formed, referring to fig. 7, in step S700, an electrode material layer 301 may be formed on the surface of the metal barrier layer 600 by Physical Vapor Deposition (PVD) or the like. The electrode material layer 301 may fill up and extend beyond the recess 120a. Then, the electrode material layer 301 may be subjected to a Chemical Mechanical Polishing (CMP) process. During the chemical mechanical polishing, the metal barrier layer 600 may be used as a polishing stop layer, thereby preventing damage caused by polishing the first dielectric layer 120.
Referring to fig. 8, after the cmp process, the upper surface of the electrode layer 300 may be flush with the upper surface of the metal barrier layer 600. Thereafter, when the memory structure 400 is formed on the electrode layer 300, the relevant film layer of the memory structure 400 may be formed on a flat surface to have a uniform thickness.
Of course, in other examples, the metal barrier layer 600 may also be formed in the recess 120a, but not on the upper surface of the first dielectric layer 120. This is not a limitation here.
In one embodiment, after step S900, the method further includes:
step S11, please refer to fig. 11, forming an isolation protection layer 700 covering the memory structure 400 and the first dielectric layer 120;
step S12, referring to fig. 12, forming a second dielectric layer 800 on the isolation protection layer 700;
step S13, referring to fig. 12 and 13, forming an interconnection via penetrating through the second dielectric layer 800 and the isolation protection layer 700, and forming a conductive plug 900 in the interconnection via;
in step S14, referring to fig. 13, a metal layer 1000 is formed on the second dielectric layer 800, and the metal layer 1000 is connected to the conductive plug 900.
In step S11, referring to fig. 11, since the surface of the previously formed memory structure 400 is higher than the surface of the first dielectric layer 120, the isolation protection layer 700 may specifically cover the upper surface of the first dielectric layer 120, the upper surface of the memory structure 400, and the sidewall surface of the memory structure 400.
The isolation protection layer 700 may include, but is not limited to, a silicon oxide layer (SiO)2) Silicon nitride layer (Si)3N4) Alumina (Al)2O3) Or a silicon oxynitride layer (SiON), etc. The isolation protection layer 700 may be formed by chemical vapor deposition. The chemical Vapor Deposition method may specifically include an Atomic Layer Deposition (ALD) method, a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, and the like.
In step S12, a second dielectric material may be deposited on the isolation protection layer 700. Meanwhile, the surface of the second dielectric material formed by deposition may be uneven because the surface of the previously formed memory structure 400 is higher than the surface of the first dielectric layer 120. Accordingly, after the second dielectric material is formed, a planarization process may be performed on the second dielectric material, thereby forming the second dielectric layer 800. At this time, the second dielectric layer 800 has a flat surface, as shown in fig. 12.
In step S13, an interconnection via may be formed in the second dielectric layer 800 by photolithography, etching, or the like. Specifically, a patterned photoresist layer may be first formed on the surface of the second dielectric layer 800 by a photolithography process. The second dielectric layer 800 is then dry etched based on the patterned photoresist layer to form the interconnect via. The dry etching includes at least any one of Reactive Ion Etching (RIE), inductively coupled plasma etching (ICP), or high density plasma etching (HDP).
Then, a conductive material is deposited within the interconnect via. The conductive material may be higher than the interconnect vias. The conductive material is then planarized to form conductive plugs 900 in the interconnect vias, as shown in fig. 13.
Specifically, the material of the conductive plug 900 may include metal materials such as cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), titanium tantalum (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al).
In step S14, referring to fig. 13, a metal layer material may be formed on the surface of the flat second dielectric layer 800 by sputtering or the like. Then, patterning is performed on the metal layer material, thereby forming a metal layer 1000.
The metal layer 1000 is connected to the conductive plug 900 so that a signal can be applied to the conductive plug 900 through the metal layer 1000. Multiple conductive plugs 900 may be connected to the same metal layer 1000, simplifying the circuit.
The material of the metal layer 1000 may include metal materials such as cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al). The material of the metal layer 1000 may be the same as or different from the conductive plug 900.
It should be understood that, although the steps in the flowchart of fig. 1 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in a strict order unless explicitly stated herein, and may be performed in other orders. Moreover, at least a portion of the steps in fig. 1 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily sequential, but may be performed alternately or in alternation with other steps or at least a portion of the steps or stages in other steps.
In one embodiment, a semiconductor structure is also provided. Referring to fig. 13, 14, 15, and 16, the semiconductor structure includes: a transistor structure 100, a metal silicide 200, an electrode layer 300, and a memory structure 400.
In one embodiment, the semiconductor pillars 111 are formed on a semiconductor substrate 10. An orthogonal projection of the semiconductor pillar 111 on the substrate 10 overlaps an orthogonal projection of the recess 120a on the substrate 10. Or the orthographic projection of the semiconductor pillar 111 on the substrate 10 is located inside the orthographic projection of the recess 120a on the substrate 10.
In one embodiment, the semiconductor pillar 111 is formed on a semiconductor substrate 10, and an orthogonal projection of the recess 120a on the substrate 10 is located inside an orthogonal projection of the memory structure 400 on the substrate 10.
In one embodiment, the semiconductor structure further comprises a metal barrier layer 600. The metal barrier layer 600 is located between the electrode layer 300 and the metal silicide 200.
In one embodiment, metal barrier layer 600 extends from within recess 120a to over first dielectric layer 120.
In one embodiment, the surface of the metal silicide 200 has a concave-convex structure.
In one embodiment, the semiconductor structure further includes an isolation protection layer 700, a second dielectric layer 800, a conductive plug 900, and a metal layer 1000.
All possible combinations of the technical features of the embodiments described above are not described for brevity, but should be considered as within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several implementation modes of the present application, and the description thereof is specific and detailed, but not construed as limiting the scope of the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent application shall be subject to the appended claims.
Claims (16)
1. A semiconductor structure, comprising:
the transistor structure comprises a transistor and a first dielectric layer, wherein the transistor is positioned in the first dielectric layer and comprises a semiconductor column and a grid structure at least partially surrounding the semiconductor column, a source region or a drain region is formed at the top of the semiconductor column, a groove is formed in the first dielectric layer, and the groove is exposed out of the top of the semiconductor column;
the metal silicide is positioned in the groove;
the electrode layer is positioned on the metal silicide and fills the groove;
and the storage structure is positioned on the electrode layer.
2. The semiconductor structure of claim 1, wherein the semiconductor pillar is formed on a substrate of a semiconductor, and an orthogonal projection of the semiconductor pillar on the substrate overlaps with an orthogonal projection of the recess on the substrate or is located inside the orthogonal projection of the recess on the substrate.
3. The semiconductor structure of claim 1, wherein the semiconductor pillar is formed on a semiconductor substrate, and an orthogonal projection of the recess on the substrate is located inside an orthogonal projection of the memory structure on the substrate.
4. The semiconductor structure of claim 1, further comprising:
and the metal barrier layer is positioned between the electrode layer and the metal silicide.
5. The semiconductor structure of claim 4, wherein the metal barrier layer extends from within the recess to over the first dielectric layer.
6. The semiconductor structure of claim 1, wherein the metal silicide surface has a relief structure.
7. The semiconductor structure of any of claims 1-6, further comprising:
the isolation protective layer covers the storage structure and the first dielectric layer;
the second dielectric layer is positioned on the isolation protective layer;
the conductive plug penetrates through the second dielectric layer and the isolation protection layer and is connected with the top of the storage structure;
and the metal layer is positioned on the second dielectric layer and is connected with the conductive plug.
8. A method of fabricating a semiconductor structure, comprising:
providing a transistor structure, wherein the transistor structure comprises a transistor and a first dielectric layer, the transistor is positioned in the first dielectric layer, the transistor comprises a semiconductor column and a gate structure at least partially surrounding the semiconductor column, and a source region or a drain region is formed at the top of the semiconductor column;
forming a groove in the first dielectric layer, wherein the groove exposes the top of the semiconductor column;
forming metal silicide in the groove;
forming an electrode layer on the metal silicide to fill the groove;
and forming a storage structure on the electrode layer.
9. The method of claim 8, wherein forming a metal silicide in the recess comprises:
forming a metal material layer on the surface of the first dielectric layer and in the groove;
carrying out heat treatment on the metal material layer to form the metal silicide in the groove;
and removing the unreacted metal material layer.
10. The method of claim 9, wherein the semiconductor pillar is formed on a semiconductor substrate, and an orthogonal projection of the semiconductor pillar on the substrate overlaps with an orthogonal projection of the recess on the substrate, or is located inside the orthogonal projection of the recess on the substrate.
11. The method of claim 8, wherein the semiconductor pillar is formed on a semiconductor substrate, and an orthogonal projection of the recess on the substrate is located inside an orthogonal projection of the storage structure on the substrate.
12. The method of claim 8, further comprising, after forming the metal silicide in the recess:
and carrying out graphical processing on the metal silicide so as to form a concave-convex structure on the surface of the metal silicide.
13. The method of claim 8, wherein after forming the metal silicide in the recess and before forming the electrode layer on the metal silicide, the method further comprises:
and forming a metal barrier layer in the groove.
14. The method of claim 13, wherein the metal barrier layer is formed on the upper surface of the first dielectric layer while the metal barrier layer is formed in the recess.
15. The method of claim 8, wherein forming a recess in the first dielectric layer further comprises:
removing the first dielectric layer above the semiconductor pillar to enable the upper surface of the first dielectric layer to be flush with the top surface of the semiconductor pillar;
and back-etching the top of the semiconductor column to form the groove in the first dielectric layer.
16. The method for fabricating a semiconductor structure according to any one of claims 8 to 15, further comprising, after forming a memory structure on the electrode layer:
forming an isolation protection layer covering the storage structure and the first dielectric layer;
forming a second dielectric layer on the isolation protection layer;
forming an interconnection through hole penetrating through the second dielectric layer and the isolation protection layer, and forming a conductive plug in the interconnection through hole;
and forming a metal layer on the second dielectric layer, wherein the metal layer is connected with the conductive plug.
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