CN115274415A - Semiconductor structure and preparation method thereof - Google Patents

Semiconductor structure and preparation method thereof Download PDF

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Publication number
CN115274415A
CN115274415A CN202210725163.0A CN202210725163A CN115274415A CN 115274415 A CN115274415 A CN 115274415A CN 202210725163 A CN202210725163 A CN 202210725163A CN 115274415 A CN115274415 A CN 115274415A
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semiconductor
dielectric layer
layer
transistor
forming
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王晓光
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

Abstract

The application relates to a semiconductor structure and a preparation method thereof, wherein the preparation method of the semiconductor structure comprises the following steps: forming a transistor structure, wherein the transistor structure comprises a transistor and a first dielectric layer, the transistor comprises a semiconductor column and a grid structure at least partially surrounding the semiconductor column, a source region or a drain region is formed at the top of the semiconductor column, the first dielectric layer surrounds the transistor, and the upper surface of the first dielectric layer is flush with the top surface of the semiconductor column; forming a metal material layer on the upper surface of the first dielectric layer and the top surface of the semiconductor column; carrying out heat treatment on the metal material layer to enable the metal material layer to react with the top of the semiconductor column to form metal silicide; removing the unreacted metal material layer; and forming a storage structure on the metal silicide. The embodiment of the application can effectively improve the current driving capability of the grid electrode of the transistor.

Description

Semiconductor structure and preparation method thereof
Technical Field
The present disclosure relates to the field of memory technologies, and in particular, to a semiconductor structure and a method for fabricating the same.
Background
Vertical fully-wrapped-around-gate (VGAA) transistors are an emerging technology that continues the path of existing semiconductor technology, further enhancing gate control capability, overcoming the physical scaling and performance limitations of current technologies. However, the enhancement of the current driving capability of the transistor gate is still a concern.
Disclosure of Invention
Accordingly, embodiments of the present application provide a semiconductor structure and a method for fabricating the same to improve the current driving capability of a gate of a transistor.
A method of fabricating a semiconductor structure, comprising:
forming a transistor structure, wherein the transistor structure comprises a transistor and a first dielectric layer, the transistor comprises a semiconductor column and a grid structure at least partially surrounding the semiconductor column, a source region or a drain region is formed at the top of the semiconductor column, the first dielectric layer surrounds the transistor, and the upper surface of the first dielectric layer is flush with the top surface of the semiconductor column;
forming a metal material layer on the upper surface of the first dielectric layer and the top surface of the semiconductor column;
carrying out heat treatment on the metal material layer to enable the metal material layer to react with the top of the semiconductor column to form metal silicide;
removing the unreacted metal material layer;
and forming a storage structure on the metal silicide.
In one embodiment, before forming the memory structure on the metal silicide, the method further includes:
and carrying out planarization treatment on the upper surface of the first dielectric layer and the upper surface of the metal silicide.
In one embodiment, before forming the metal material layer on the upper surface of the first dielectric layer and the top surface of the semiconductor pillar, the method includes:
and carrying out patterning treatment on the top of the semiconductor column to form an upward convex structure.
In one embodiment, before forming the metal material layer on the upper surface of the first dielectric layer and the top surface of the semiconductor pillar, the method includes:
and carrying out graphical processing on the top of the semiconductor column to form a concave structure.
In one embodiment, the area of the orthographic projection of the storage structure on the projection plane parallel to the top surface of the half guide pillar accounts for more than 75% of the area of the orthographic projection of the semiconductor pillar.
In one embodiment, the orthographic projection area of the storage structure is greater than or equal to the orthographic projection area of the semiconductor pillar.
In one embodiment, after the forming the memory structure on the metal silicide, the method further includes:
forming an isolation protection layer covering the storage structure and the first dielectric layer;
forming a second dielectric layer on the isolation protection layer;
forming an interconnection through hole penetrating through the second dielectric layer and the isolation protection layer, and forming a conductive plug in the interconnection through hole;
and forming a metal layer on the second dielectric layer, wherein the metal layer is connected with the conductive plug.
A semiconductor structure, comprising:
the transistor structure comprises a transistor and a first dielectric layer, the transistor comprises a semiconductor column and a grid structure at least partially surrounding the semiconductor column, a source region or a drain region is formed at the top of the semiconductor column, and the first dielectric layer surrounds the transistor;
the metal silicide is positioned on the top of the semiconductor column and is connected with the first dielectric layer;
and the storage structure is positioned on the metal silicide.
In one embodiment, the upper surface of the first dielectric layer is flush with the upper surface of the metal silicide.
In one embodiment, the semiconductor pillar is formed with a raised top structure on top.
In one embodiment, a recessed structure is formed on the top of the semiconductor pillar.
In one embodiment, the area of the orthographic projection of the storage structure on the projection plane parallel to the top surface of the half guide pillar accounts for more than 75% of the area of the orthographic projection of the semiconductor pillar.
In one embodiment, the orthographic projection area of the storage structure is greater than or equal to the orthographic projection area of the semiconductor pillar.
In one embodiment, the semiconductor structure further comprises:
the isolation protective layer covers the storage structure and the first dielectric layer;
the second dielectric layer is positioned on the isolation protective layer;
the conductive plug penetrates through the second dielectric layer and the isolation protective layer and is connected with the top of the storage structure;
and the metal layer is positioned on the second dielectric layer and is connected with the conductive plug.
In one embodiment, the memory structure includes any one or more of a magnetic random access memory structure, a phase change random access memory structure, a ferroelectric random access memory structure, and a resistance change random access memory structure.
According to the semiconductor structure and the preparation method thereof, the metal silicide is formed on the drain region (or the source region) of the transistor, so that the contact resistance between the drain region (or the source region) of the transistor and the storage structure is effectively reduced, and the grid current driving capability of the transistor is improved.
In addition, according to the embodiment of the application, the upper surface of the first dielectric layer is flush with the top surface of the semiconductor column, and then the metal material layer is formed. The top surface of the semiconductor column and the upper surface of the first dielectric layer are fully paved by the formed metal material layer, so that each position of the top surface of the semiconductor column reacts with the metal material layer. At this time, the semiconductor pillar and the metal silicide can be well contacted, and the contact resistance between the semiconductor pillar and the metal silicide can be effectively reduced. Therefore, the total resistance value of the contact resistor between the drain region (or the source region) of the transistor and the storage structure can be effectively reduced, so that the current driving capability of the gate electrode of the transistor can be effectively improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the description of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the description below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a flow chart of a method of fabricating a semiconductor structure provided in one embodiment;
FIGS. 2-9 are schematic cross-sectional views of a semiconductor structure provided in one embodiment during fabrication thereof;
FIGS. 10-13 are schematic views of semiconductor structures fabricated in various embodiments;
FIG. 14 is a schematic cross-sectional view of a semiconductor structure during fabrication thereof in accordance with another embodiment;
fig. 15 is a schematic cross-sectional view of a semiconductor structure during fabrication in yet another embodiment.
Description of the reference numerals:
100-transistor structure, 110-transistor, 111-semiconductor column, 112-gate structure, 120-first dielectric layer, 200-metal material layer, 300-metal silicide, 400-memory structure, 500-isolation protection layer, 600-second dielectric layer, 700-conductive plug, and 800-metal layer.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
Spatial relational terms, such as "under," "below," "under," "over," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may comprise additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the present application should not be limited to the particular shapes of regions illustrated in the drawings of the specification but are to include deviations in shapes that result, for example, from manufacturing techniques.
As mentioned in the background, the gate current driving capability of the VGAA transistor still needs to be enhanced.
Specifically, for example, a Magnetic Random Access Memory (MRAM) is one of new nonvolatile Random Access memories based on the principle of modulating the magnitude of Magnetic resistance. MRAM, as a nonvolatile memory, has a read/write speed comparable to that of a volatile memory DRAM. And the standby power consumption of the MRAM is far smaller than that of the DRAM, and the MRAM has the potential of replacing the DRAM in the future.
A memory cell of an MRAM generally includes one transistor and one Magnetic Tunnel Junction (MTJ). To implement DRAM-like applications, smaller transistor sizes and higher drive currents are required to drive the magnetic tunnel junction switching.
For another example, a plurality of novel technologies represented by Phase Change Random Access Memory (PCRAM) have attracted attention due to their characteristics of high integration level, low power consumption, and the like. In particular, PCRAMs have the potential to serve as both main and external memory due to their non-volatile, byte-addressable, and like characteristics. Under its influence, the boundary between main memory and external memory is also becoming increasingly blurred, possibly even bringing about significant changes to future memory architectures. Thus, PCRAM is considered to be one of the new technologies with great development prospects, most likely to replace DRAM completely.
A PCRAM data storage operation requires a certain drive current. However, as semiconductor devices are scaled down, the transistor driving current decreases, which results in the inability to maintain the original driving capability.
For example, for Ferroelectric Random Access Memory (FeRAM) and Resistive Random Access Memory (RRAM), a high-density architecture requirement is required to be achieved, and the feature size of a semiconductor process is continuously reduced. At this time, the sizes of the gate, source and drain active regions of the transistor in the memory cell are also reduced correspondingly, so that the driving current of the transistor is restrained from increasing, and the memory cannot be driven to work.
Based on the above, the present application provides a semiconductor structure and a method for manufacturing the same, so as to improve the current driving capability of a transistor gate. The semiconductor structure may include, but is not limited to, a magnetic memory, a phase change memory, a ferroelectric memory, a resistive random access memory, or the like. The transistor may include, but is not limited to, a VGAA transistor.
In one embodiment, referring to fig. 1, a method for fabricating a semiconductor structure is provided, which includes the steps of:
step S100, please refer to fig. 3, forming a transistor structure 100, wherein the transistor structure 100 includes a transistor 110 and a first dielectric layer 120, the transistor includes a semiconductor pillar 111 and a gate structure 112 at least partially surrounding the semiconductor pillar 111, a source region or a drain region is formed at the top of the semiconductor pillar 111, the first dielectric layer surrounds the transistor, and the upper surface of the first dielectric layer 120 is flush with the top surface of the semiconductor pillar 111;
step S300, referring to fig. 3, forming a metal material layer 200 on the upper surface of the first dielectric layer 120 and the top surface of the semiconductor pillar 111;
step S500, referring to fig. 4, performing a heat treatment on the metal material layer 200 to react with the top of the semiconductor pillar 111 to form a metal silicide 300;
step S700, please refer to fig. 4, removing the unreacted metal material layer 200;
in step S900, referring to fig. 7, a memory structure 400 is formed on the metal silicide 300.
In step S100, referring to fig. 2, in the formation process of the transistor structure 100, a semiconductor substrate may be provided first. The substrate may include, but is not limited to, a silicon (Si) substrate, a germanium (Ge) substrate, or a silicon-on-insulator (SOI) substrate, etc. Meanwhile, the substrate can be a P-type substrate or an N-type substrate. Then, vertical semiconductor pillars 111 are formed on the substrate. Then, the gate structure 112 is formed to fully surround or partially surround the semiconductor pillar 111. At this time, the gate structure 112 entirely surrounds the semiconductor pillar 111, or the gate structure 112 partially surrounds the semiconductor pillar 111. That is, the gate structure 112 at least partially surrounds the semiconductor pillar 111. The top and bottom of the semiconductor pillar 111 are heavily doped to form a source region and a drain region, respectively. Specifically, the top of the semiconductor pillar 111 may form a source region, and may also form a drain region.
It is understood herein that the gate structure 112 may include a gate dielectric layer as well as a gate conductive layer. The gate dielectric layer can be formed by a common dielectric layer or a material with a high k dielectric constant. High-k dielectric constant materials may include, for example: aluminum oxide (Al)2O3) Hafnium oxide (HfO)2) Hafnium oxynitride (HfON), zirconium oxide (ZrO)2) Tantalum oxide (Ta 2O)5) Titanium oxide (TiO)2) Or strontium titanium oxide (SrTiO)3)。
The gate conductive layer may include, but is not limited to, any one or more of titanium nitride (TiN), titanium (Ti), tungsten silicide (Si 2W), tungsten (W), and the like.
Meanwhile, during the formation of the transistor structure 100, the first dielectric layer 120 may also be formed. Referring to fig. 2, a first dielectric layer 120 may be initially formed to fill between the semiconductor pillars 111 and completely cover the transistor 110. Then, referring to fig. 3, the first dielectric layer 120 above the semiconductor pillar 111 may be removed by performing chemical mechanical polishing and/or etching on the first dielectric layer 120, so that the upper surface of the first dielectric layer 120 is flush with the top surface of the semiconductor pillar 111.
Specifically, first dielectric layer 120 may include, but is not limited to, silicon oxide (SiO)2) Layer, silicon nitride (Si)3N4) Layer, alumina (Al)2O3) A layer or a silicon oxynitride (SiON) layer.
By way of example, first dielectric layer 120 may include multiple film layers of the same or different materials. Multiple film layers may be formed in different process steps.
In step S300, referring to fig. 3, a metal material layer 200 may be formed on the planarized upper surface of the first dielectric layer 120 and the top surface of the semiconductor pillar 111 by magnetron sputtering or electroplating.
The metal material layer 200 may include, but is not limited to, ti, co, or NiPt, etc.
In step S500, the metallic material layer 200 may be heat-treated by annealing. During the heat treatment, the metal material layer 200 and atoms in the top of the semiconductor pillars 111 are diffused into each other to react, thereby forming the metal silicide 300. At this time, the formed metal silicide 300 extends from the interface between the metal material layer 200 and the semiconductor pillar 111 before annealing to the metal material layer 200 and the semiconductor pillar 111 on both sides. Meanwhile, the metal material layer 200 is formed at each position of the top of the semiconductor pillar 111, so that each position of the top of the semiconductor pillar 111 reacts with the metal material layer to form the metal silicide 300. At this time, the finally formed metal silicide 300 is connected to the first dielectric layer 120, the semiconductor pillar 111 and the metal silicide 300 can be well contacted, and the contact resistance between the two can be effectively reduced.
In step S700, referring to fig. 4, as an example, the unreacted metal material layer 200 may be removed by Chemical Mechanical Polishing (CMP). Specifically, CMP may stop on first dielectric layer 120 so that unreacted metallic material layer 200 may be completely removed.
At this time, after the CMP process, the upper surface of the metal silicide 300 may be flush with the upper surface of the first dielectric layer 120.
Of course, this is not a limitation here. The unreacted metal material layer 200 may also be removed by other means, such as wet etching. After removing the unreacted metal material layer 200, the upper surface of the metal silicide 300 may also be higher than the upper surface of the first dielectric layer 120.
In step S900, the memory structure 400 may include, but is not limited to, any one or more of a magnetic random access memory structure (see fig. 10), a phase-change random access memory structure (see fig. 11), a ferroelectric random access memory structure (see fig. 12), and a resistive random access memory structure (see fig. 13).
During the formation of the memory structure 400, the materials of the layers of the memory structure 400 may be first formed on the upper surface of the metal silicide 300 and the upper surface of the first dielectric layer 120. The material of each layer is then patterned to form a memory structure 400 over the metal silicide 300.
For example, when memory structure 400 comprises a magnetic random access memory structure, it comprises a magnetic tunnel junction. At this time, referring to fig. 5, a pinned layer 411 may be formed on the upper surface of the metal silicide 300 and the upper surface of the first dielectric layer 120. Then, a tunnel barrier (tunnel barrier) material 421 is formed on the surface of the plug layer material. A Free layer material 431 is then formed over the tunnel junction material.
Next, referring to fig. 6, a masking material 10 may be formed on the free layer material, and a patterned photoresist 20 may be formed on the masking material 10. Then, the mask material 10 is patterned by photolithography, etching, or the like to form a mask layer. Then, the patterned photoresist 20 is removed, and the free layer material, the tunnel junction material, and the plug layer material are sequentially etched based on the mask layer, so as to form a free layer 430, a tunnel junction 420, and a plug layer 410, as shown in fig. 7. The free layer 430, the tunnel junction 420, and the pinned layer 410 constitute a magnetic tunnel junction.
In the present embodiment, the metal silicide 300 is formed on the drain region (or the source region) of the transistor 110, so that the contact resistance between the drain region (or the source region) of the transistor 110 and the memory structure 400 is effectively reduced, thereby improving the gate current driving capability of the transistor.
In addition, in the present embodiment, the upper surface of the first dielectric layer 120 is flush with the top surface of the semiconductor pillar 111, and then the metal material layer 200 is formed. The metal material layer 200 is formed to fill the top surface of the semiconductor pillar 111 and the upper surface of the first dielectric layer 120, so that the top surface of the semiconductor pillar 111 reacts with the metal material layer at each position. At this time, the semiconductor pillar may be in good contact with the metal silicide 300, and the contact resistance therebetween may be effectively reduced. Therefore, the total resistance of the contact resistors between the drain region (or source region) and the memory structure 400 of the transistor 110 can be effectively reduced, so that the gate current driving capability of the transistor can be effectively improved.
In one embodiment, before step S900, the method further includes:
step S800, a planarization process is performed on the upper surface of the first dielectric layer 120 and the upper surface of the metal silicide 300.
Specifically, after step S700, if the upper surface of the metal silicide 300 is higher than the upper surface of the first dielectric layer 120, the upper surface of the first dielectric layer 120 and the upper surface of the metal silicide 300 may be planarized so that the upper surfaces thereof are flush.
At this time, in the process of forming the memory structure 400 subsequently, materials of the layers can be formed on the flat surface, so that the thickness of the relevant layers of the finally formed memory structure 400 is more uniform.
Of course, in other embodiments, as before, the unreacted metal material layer 200 may also be removed directly by CMP in step S700, so that the upper surface of the metal silicide 300 may be flush with the upper surface of the first dielectric layer 120.
Alternatively, in other embodiments, the deposition of the film materials of the memory structure 400 may also be performed in a case that the upper surface of the metal silicide 300 is higher than the upper surface of the first dielectric layer 120, which is not limited herein.
In one embodiment, before step S300, the method further includes:
in step S210, a top portion of the semiconductor pillar 111 is patterned to form a raised structure, as shown in fig. 14.
Specifically, a photoresist layer may be coated on the upper surface of the first dielectric layer 120 and the top surface of the semiconductor pillar 111, and through a series of steps such as exposure and development, a patterned photoresist layer is formed. Then, the top (drain region or source region) of the semiconductor pillar 111 is etched based on the patterned photoresist layer, thereby forming an upper convex structure. Then, the photoresist layer is removed.
The shape and size of the convex structure can be set according to requirements. For example, the cross-sectional shape of the upwardly convex structure may be rectangular. At this time, as an example, both opposite side edges (e.g., front and rear edges or left and right edges) of the top of the semiconductor pillar 111 may be removed, or all the peripheral edges of the top of the semiconductor pillar 111 may be removed. As another example, the cross-sectional shape of the raised boss can be circular. At this time, the edge portion other than the circular shape may be removed.
At this time, the exposed surface area of the semiconductor pillar 111 can be effectively increased, so that the metal material layer 200 formed in step S300 has a larger contact area with the semiconductor pillar 111, and the metal silicide 300 formed subsequently has a larger contact surface. At this time, the contact resistance can be further reduced.
In one embodiment, before step S300, the method further includes:
in step S220, a top portion of the semiconductor pillar 111 is patterned to form a recessed structure, please refer to fig. 15.
Specifically, a photoresist layer may be coated on the upper surface of the first dielectric layer 120 and the top surface of the semiconductor pillar 111, and through a series of steps such as exposure and development, a patterned photoresist layer is formed. Then, the top (drain region or source region) of the semiconductor pillar 111 is etched based on the patterned photoresist layer, thereby forming a recess structure. Then, the photoresist layer is removed.
The shape and size of the recessed structure can be set as required. For example, the cross-sectional shape of the recessed structure may be rectangular, circular, or the like. At this time, as an example, a center portion of the semiconductor pillar 111 may be removed such that the center of the semiconductor pillar 111 is recessed to form a recessed structure.
At this time, the exposed surface area of the semiconductor pillar 111 can be effectively increased, so that the metal material layer 200 formed in step S300 and the semiconductor pillar 111 have a larger contact area, and the metal silicide 300 formed subsequently has a larger contact surface, so that the contact resistance can be further reduced.
In one embodiment, the orthographic projection area of the memory structure 400 occupies more than 75% of the orthographic projection area of the semiconductor pillar 111 on a projection plane parallel to the top surface of the semiconductor pillar 111.
At this time, the memory structure 400 has a sufficiently large contact area with the metal silicide 300 that may be formed on the semiconductor pillar 111, so that contact resistance therebetween may be effectively reduced.
As an example, the storage structure 400 may be set to have an orthographic projection area equal to or greater than that of the semiconductor pillars 111.
At this time, the entire upper surface of the metal silicide 300 may be brought into contact with the memory structure 400, thereby further reducing the contact resistance therebetween.
In one embodiment, after step S900, the method further includes:
step S11, please refer to fig. 8, forming an isolation protection layer 500 covering the memory structure 400 and the first dielectric layer 120;
step S12, referring to fig. 9, forming a second dielectric layer 600 on the isolation protection layer 500;
step S13, please refer to fig. 9, in which an interconnection via penetrating through the second dielectric layer 600 and the isolation protection layer 500 is formed, and a conductive plug 700 is formed in the interconnection via;
in step S14, referring to fig. 10, a metal layer 800 is formed on the second dielectric layer 600, and the metal layer 800 is connected to the conductive plug 700.
In step S11, since the surface of the previously formed storage structure 400 is higher than the surface of the first dielectric layer 120, the isolation protection layer 500 may specifically cover the upper surface of the first dielectric layer 120, the upper surface of the storage structure 400, and the sidewall surface of the storage structure 400.
The isolation protection layer 500 may include, but is not limited to, a silicon oxide layer (SiO)2) Silicon nitride layer (Si)3N4) Alumina (Al)2O3) Or a silicon oxynitride layer (SiON), etc. The isolation protection layer 500 may be formed by chemical vapor deposition. The chemical Vapor Deposition method may specifically include an Atomic Layer Deposition (ALD) method, a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, and the like.
In step S12, a second dielectric material may be deposited on the isolation protection layer 500. Meanwhile, the surface of the second dielectric material formed by deposition may be uneven because the surface of the previously formed memory structure 400 is higher than the surface of the first dielectric layer 120. Accordingly, after forming the second dielectric material, the second dielectric material may be planarized to form the second dielectric layer 600. At this time, the second dielectric layer 600 has a flat surface.
In step S13, an interconnection via may be formed in the second dielectric layer 600 by photolithography, etching, or the like. Specifically, a patterned photoresist layer may be first formed on the surface of the second dielectric layer 600 through a photolithography process. The second dielectric layer 600 is then dry etched based on the patterned photoresist layer to form the interconnect via. The dry etching includes at least any one of Reactive Ion Etching (RIE), inductively coupled plasma etching (ICP), or high density plasma etching (HDP).
Then, a conductive material is deposited within the interconnect via. The conductive material may be higher than the interconnect vias. The conductive material is then planarized to form conductive plugs 700 within the interconnect vias.
Specifically, the material of the conductive plug 700 may include cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), titanium tantalum (TaTi), tungsten nitride (WN), copper (Cu), aluminum (Al), and other metal materials.
In step S14, a metal layer material may be formed on the surface of the flat second dielectric layer 600 by sputtering or the like. Then, patterning is performed on the metal layer material, thereby forming the metal layer 800.
Metal layer 800 connects conductive plug 700 so that a signal can be applied to conductive plug 700 through metal layer 800. Multiple conductive plugs 700 may be connected to the same metal layer 800, simplifying the circuit.
The material of the metal layer 800 may include metal materials such as cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), titanium tantalum (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al). The material of metal layer 800 may be the same as or different from conductive plug 700.
It should be understood that, although the steps in the flowchart of fig. 1 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not limited to being performed in the exact order illustrated and, unless explicitly stated herein, may be performed in other orders. Moreover, at least a part of the steps in fig. 1 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least a part of the steps or stages in other steps.
In one embodiment, a semiconductor structure is also provided. Referring to any of fig. 10-13, the semiconductor structure includes a transistor structure 100, a metal silicide 300, and a memory structure 400.
Transistor structure 100 includes a transistor 110 and a first dielectric layer 120. The transistor 110 includes a semiconductor pillar 111 and a gate structure 112. A gate structure 112 at least partially surrounds the semiconductor pillar 111. Meanwhile, a source region or a drain region is formed on top of the semiconductor pillar 111. First dielectric layer 120 surrounds transistor 110. The metal silicide 300 is located on top of the semiconductor pillar 111 and connected to the first dielectric layer 120. The memory structure 400 is located on the metal silicide 300.
In the present embodiment, the metal silicide 300 is formed on the drain region (or the source region) of the transistor 110, so that the contact resistance between the drain region (or the source region) of the transistor 110 and the memory structure 400 is effectively reduced, thereby improving the gate current driving capability of the transistor.
Meanwhile, the metal silicide 300 is connected to the first dielectric layer 120. At this time, the semiconductor pillar 111 and the metal silicide 300 may be in good contact, and the contact resistance therebetween may be effectively reduced. Therefore, the total resistance of the contact resistor between the drain region (or source region) of the transistor 110 and the memory structure 400 can be effectively reduced, so that the gate current driving capability of the transistor can be effectively improved.
In one embodiment, the upper surface of the first dielectric layer 120 is flush with the upper surface of the metal silicide 300.
In one embodiment, the semiconductor pillars 111 are formed with a raised top structure on top.
At this time, the metal silicide 300 has a larger contact surface, so that the contact resistance can be further reduced.
In one embodiment, the semiconductor pillars 111 are formed with a recessed structure on top.
At this time, the metal silicide 300 also has a larger contact surface, so that the contact resistance can be further reduced.
In one embodiment, the area of the orthographic projection of the storage structure 400 on a projection plane parallel to the top surface of the half pillars is more than 75% of the area of the orthographic projection of the semiconductor pillars 111.
At this time, the memory structure 400 has a sufficiently large contact area with the metal silicide 300 that may be formed on the semiconductor pillar 111, so that contact resistance therebetween may be effectively reduced.
In one embodiment, the orthographic area of the memory structure 400 is equal to or greater than the orthographic area of the semiconductor pillars 111.
At this time, the entire upper surface of the metal silicide 300 may be brought into contact with the memory structure 400, thereby further reducing the contact resistance therebetween.
In one embodiment, the semiconductor structure further includes an isolation protection layer 500, a second dielectric layer 600, a conductive plug 700, and a metal layer 800.
The isolation protection layer 500 covers the memory structure 400 and the first dielectric layer 120. The second dielectric layer 600 is located on the isolation protection layer 500. The conductive plug 700 penetrates through the second dielectric layer 600 and the isolation protection layer 500 to connect to the top of the memory structure 400. The metal layer 800 is located on the second dielectric layer 120 and connected to the conductive plug 700.
In one embodiment, the memory structure comprises any one or more of a magnetic random access memory structure, a phase change random access memory structure, a ferroelectric random access memory structure, and a resistive random access memory structure.
For the specific definition of the semiconductor structure, reference may be made to the above definition of the preparation method of the semiconductor structure, and redundant description is not repeated here.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features of the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent application shall be subject to the appended claims.

Claims (15)

1. A method for fabricating a semiconductor structure, comprising:
forming a transistor structure, wherein the transistor structure comprises a transistor and a first dielectric layer, the transistor comprises a semiconductor column and a grid structure at least partially surrounding the semiconductor column, a source region or a drain region is formed at the top of the semiconductor column, the first dielectric layer surrounds the transistor, and the upper surface of the first dielectric layer is flush with the top surface of the semiconductor column;
forming a metal material layer on the upper surface of the first dielectric layer and the top surface of the semiconductor column;
carrying out heat treatment on the metal material layer to enable the metal material layer to react with the top of the semiconductor column to form metal silicide;
removing the unreacted metal material layer;
and forming a storage structure on the metal silicide.
2. The method of claim 1, further comprising, prior to forming a memory structure over the metal silicide:
and carrying out planarization treatment on the upper surface of the first dielectric layer and the upper surface of the metal silicide.
3. The method of claim 1, wherein before forming the metal material layer on the upper surface of the first dielectric layer and the top surface of the semiconductor pillar, the method comprises:
and carrying out patterning treatment on the top of the semiconductor column to form an upward convex structure.
4. The method of claim 1, wherein before forming the metal material layer on the upper surface of the first dielectric layer and the top surface of the semiconductor pillar, the method comprises:
and carrying out patterning treatment on the top of the semiconductor column to form a concave structure.
5. The method of claim 1, wherein an orthographic area of the storage structure on a projection plane parallel to the top surface of the half pillars is more than 75% of the orthographic area of the semiconductor pillars.
6. The method of claim 5, wherein an orthographic area of the storage structure is equal to or larger than an orthographic area of the semiconductor pillar.
7. The method as claimed in any of claims 1-6, further comprising, after forming a memory structure over the metal silicide:
forming an isolation protection layer covering the storage structure and the first dielectric layer;
forming a second dielectric layer on the isolation protection layer;
forming an interconnection through hole penetrating through the second dielectric layer and the isolation protection layer, and forming a conductive plug in the interconnection through hole;
and forming a metal layer on the second dielectric layer, wherein the metal layer is connected with the conductive plug.
8. A semiconductor structure, comprising:
the transistor structure comprises a transistor and a first dielectric layer, the transistor comprises a semiconductor column and a grid structure at least partially surrounding the semiconductor column, a source region or a drain region is formed at the top of the semiconductor column, and the first dielectric layer surrounds the transistor;
the metal silicide is positioned on the top of the semiconductor column and is connected with the first dielectric layer;
and the storage structure is positioned on the metal silicide.
9. The semiconductor structure of claim 8, wherein an upper surface of the first dielectric layer is flush with an upper surface of the metal silicide.
10. The semiconductor structure of claim 8, wherein the top of the semiconductor pillar is formed with an upwardly raised structure.
11. The semiconductor structure of claim 8, wherein the top of the semiconductor pillar is formed with a recessed structure.
12. The semiconductor structure of claim 8, wherein an orthographic area of the storage structure on a projection plane parallel to the top surface of the half pillar is over 75% of the orthographic area of the semiconductor pillar.
13. The semiconductor structure of claim 12, wherein an orthographic area of the memory structure is equal to or greater than an orthographic area of the semiconductor pillar.
14. The semiconductor structure of any of claims 8-13, further comprising:
the isolation protective layer covers the storage structure and the first dielectric layer;
the second dielectric layer is positioned on the isolation protective layer;
the conductive plug penetrates through the second dielectric layer and the isolation protective layer and is connected with the top of the storage structure;
and the metal layer is positioned on the second medium layer and is connected with the conductive plug.
15. The semiconductor structure of any of claims 8-13, wherein the memory structure comprises any one or more of a magnetic random access memory structure, a phase change random access memory structure, a ferroelectric random access memory structure, and a resistive random access memory structure.
CN202210725163.0A 2022-06-24 2022-06-24 Semiconductor structure and preparation method thereof Pending CN115274415A (en)

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