CN115020473A - Semiconductor structure and preparation method thereof - Google Patents

Semiconductor structure and preparation method thereof Download PDF

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Publication number
CN115020473A
CN115020473A CN202210601541.4A CN202210601541A CN115020473A CN 115020473 A CN115020473 A CN 115020473A CN 202210601541 A CN202210601541 A CN 202210601541A CN 115020473 A CN115020473 A CN 115020473A
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layer
semiconductor
channel region
gate dielectric
forming
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刘佑铭
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

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Abstract

The embodiment of the disclosure provides a semiconductor structure and a preparation method thereof, wherein the semiconductor structure comprises: the semiconductor device comprises a substrate, a first channel region, a second channel region and a second source drain region, wherein the substrate is provided with a plurality of semiconductor columns which are arranged at intervals, and the semiconductor columns comprise the first source drain region, the first channel region, the second channel region and the second source drain region which are sequentially distributed along the direction far away from the surface of the substrate; the gate dielectric layer surrounds the side face of the semiconductor column in the first channel region; the word lines extend along a first direction, each word line surrounds a plurality of semiconductor columns distributed along the first direction, the word lines surround a first channel region and a second channel region in the semiconductor columns, a gate dielectric layer is arranged between the word lines and the semiconductor columns in the first channel region, and an air gap is arranged between the word lines and the semiconductor columns in the second channel region. Embodiments of the present disclosure are at least beneficial for reducing gate induced drain leakage current of a semiconductor structure.

Description

Semiconductor structure and preparation method thereof
Technical Field
The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.
Background
As the integration density of dynamic memories is moving toward higher density, higher requirements are placed on the layout of transistors and the size of transistors in the dynamic memory array structure. When the full-surrounding gate transistor structure is used as a transistor in a dynamic memory, a smaller pattern size can be obtained under a given process condition, and the integration density of the dynamic memory is favorably increased.
While the layout of the dynamic memory structure and how to reduce the size of the dynamic memory structure are studied, it is also necessary to improve the electrical performance of the small-sized dynamic memory. Specifically, as the size of the dynamic memory structure is reduced, in the dynamic memory structure, the influence of GIDL (gate-induced drain leakage current) on the electrical performance of the semiconductor structure is increased due to the reduction of the separation distance between the gate electrode layer and the semiconductor channel.
Disclosure of Invention
Embodiments of the present disclosure provide a semiconductor structure and a method for fabricating the same, which at least facilitate reducing gate-induced drain leakage current of the semiconductor structure.
An aspect of an embodiment of the present disclosure provides a semiconductor structure, including: the semiconductor device comprises a substrate, a first channel region, a second channel region and a second source drain region, wherein the substrate is provided with a plurality of semiconductor columns which are arranged at intervals, and the semiconductor columns comprise the first source drain region, the first channel region, the second channel region and the second source drain region which are sequentially distributed along the direction far away from the surface of the substrate; the gate dielectric layer surrounds the side face of the semiconductor column in the first channel region; the word lines extend along a first direction, each word line surrounds a plurality of semiconductor columns distributed along the first direction, the word lines surround a first channel region and a second channel region in the semiconductor columns, a gate dielectric layer is arranged between the word lines and the semiconductor columns in the first channel region, and an air gap is arranged between the word lines and the semiconductor columns in the second channel region.
In some embodiments, a ratio of a length of the gate dielectric layer to a length of the air gap in a direction away from the substrate surface is greater than 1: 3.
in some embodiments, the thickness of the gate dielectric layer is greater than or equal to the width of the air gap in the first direction.
In some embodiments, the width of the air gap along the first direction is in the range of 1-5 nm.
In some embodiments, the word line comprises: a first conductive layer surrounding the semiconductor pillar of the first channel region; and the second conductive layer is positioned on the surface of the first conductive layer and surrounds the semiconductor column of the second channel region, and the material of the second conductive layer is different from that of the first conductive layer.
In some embodiments, the work function value of the material of the first conductive layer is different from the work function value of the material of the second conductive layer.
In some embodiments, the bottom surface of the first conductive layer is flush with the bottom surface of the gate dielectric layer, and the first conductive layer is exposed out of the side surface of the gate dielectric layer with partial height; the second conductive layer is also positioned on the side surface of the gate dielectric layer with the exposed part of the height of the first conductive layer.
In some embodiments, further comprising: and the word line covering layer covers the top surface of the word line and the top opening of the air gap.
In some embodiments, further comprising: a plurality of bit lines extending along the second direction, wherein each bit line is positioned between the plurality of semiconductor columns arranged along the second direction and the substrate, and the bit lines are electrically connected with the first source drain regions; and the isolation layers are positioned between the bit lines and the word lines, and also positioned between the adjacent word lines and between the adjacent bit lines.
In some embodiments, the isolation layer comprises: the first isolation layers are positioned between adjacent semiconductor columns and between adjacent bit lines, and the top surfaces of the first isolation layers are contacted with the bottom surfaces of the word lines and the bottom surfaces of the gate dielectric layers; and the second isolation layer extends along the first direction and penetrates through the first isolation layer between the adjacent semiconductor columns distributed along the second direction, the second isolation layer is positioned between the adjacent word lines, and the top surface of the second isolation layer is higher than that of the word lines.
In another aspect, a method for manufacturing a semiconductor structure is provided, including: providing a substrate, wherein the substrate is provided with a plurality of semiconductor columns which are arranged at intervals, and the semiconductor columns comprise a first source drain region, a first channel region, a second channel region and a second source drain region which are sequentially distributed along the direction far away from the surface of the substrate; forming a gate dielectric layer, wherein the gate dielectric layer surrounds the side face of the semiconductor column in the first channel region; and forming a plurality of word lines extending along the first direction, wherein each word line surrounds a plurality of semiconductor columns distributed along the first direction, the word lines surround a first channel region and a second channel region in the semiconductor columns, a gate dielectric layer is arranged between the word lines and the semiconductor columns in the first channel region, and an air gap is arranged between the word lines and the semiconductor columns in the second channel region.
In some embodiments, the process step of forming the gate dielectric layer comprises: forming a sacrificial layer on the side face of the semiconductor pillar of the second channel region; oxidizing the side face of the semiconductor column in the first channel region to form a gate dielectric layer; and removing the sacrificial layer.
In some embodiments, before forming the gate dielectric layer, the method further comprises: forming a first isolation layer and a second isolation layer on the substrate, wherein the first isolation layer is positioned between adjacent semiconductor columns, the top surface of the first isolation layer is lower than the top surfaces of the semiconductor columns, the second isolation layer penetrates through the first isolation layer between the adjacent semiconductor columns along the first direction, and the top surface of the second isolation layer is higher than the top surfaces of the semiconductor columns in the second channel region; in the step of forming the sacrificial layer, the sacrificial layer is further formed on the side face of the second isolation layer, and the etching rate of the sacrificial layer and the etching rate of the second isolation layer in the same etching process are different.
In some embodiments, the process step of forming the sacrificial layer comprises: forming a protective layer which is positioned on the top surface of the first isolation layer and covers the side surface of the semiconductor column of the first channel region; forming a sacrificial film, wherein the sacrificial film is positioned on the top surface of the protective layer, the side surface of the semiconductor column of the second channel region and the side surface of the second isolation layer; and removing the sacrificial film on the top surface of the protective layer, wherein the residual sacrificial film is used as a sacrificial layer.
In some embodiments, the sacrificial film is made of silicon nitride, and the second isolation layer is made of silicon nitride; after removing the sacrificial film on the top surface of the protective layer, the method further comprises: and carrying out plasma treatment on the residual sacrificial film so that the etching rate of the same etching process to the sacrificial layer is different from the etching rate to the second isolation layer.
In some embodiments, before forming the word line, further comprising: forming an epitaxial layer on the side face of the semiconductor column in the second channel region by adopting an epitaxial process; in the process step of forming the word line, the word line covers the side surface of the epitaxial layer; after the word lines are formed, the epitaxial layer is removed to form air gaps.
In some embodiments, the process steps of forming the word lines include: forming a first conductive layer, wherein the first conductive layer covers the side surface of the gate dielectric layer and surrounds the semiconductor column of the first channel region; and forming a second conductive layer on the top surface of the first conductive layer, wherein the second conductive layer covers the side surface of the epitaxial layer and surrounds the semiconductor pillar of the second channel region.
In some embodiments, the process step of forming the first conductive layer comprises: forming a first conductive film surrounding the semiconductor pillars of the first channel region and the second channel region; and etching back to remove the first conductive film with partial thickness until the top surface of the remaining first conductive film is lower than that of the gate dielectric layer, and taking the remaining first conductive film as the first conductive layer.
The technical scheme provided by the embodiment of the disclosure has at least the following advantages:
in the technical scheme, the semiconductor column is used for forming a semiconductor channel of a transistor, the semiconductor column comprises a first source-drain region, a first channel region, a second channel region and a second source-drain region which are sequentially distributed along the direction far away from the surface of a substrate, wherein the semiconductor column of the first source-drain region is used for forming a source electrode of the transistor, the semiconductor column of the second source-drain region is used for forming a drain electrode of the transistor, the semiconductor column of the first channel region and the semiconductor column of the second channel region are used for forming a semiconductor column of a channel region in the semiconductor channel of the transistor, a word line surrounds the semiconductor column of the channel region, a gate dielectric layer is arranged in the space between the word line and the semiconductor column, the gate dielectric layer only covers the surface of the semiconductor column of the first channel region adjacent to the first source-drain region, so that the space between the semiconductor column of the second channel region and the word line is an air gap, and electrons, namely thermionic electrons which absorb energy to jump exist in the word line and the semiconductor column, the air gap enables the hot electrons in the word line adjacent to the second source drain region semiconductor column to be captured by the word line, so that the hot electrons are prevented from being captured by the gate dielectric layer, the reduction of leakage current generated between the word line and the second source drain region semiconductor column is facilitated, namely the reduction of GIDL of a transistor is facilitated, and the improvement of the electrical performance of the semiconductor structure is facilitated.
Drawings
One or more embodiments are illustrated by corresponding figures in the drawings, which are not to be construed as limiting the embodiments, unless expressly stated otherwise, and which are not to scale; in order to more clearly illustrate the embodiments of the present disclosure or technical solutions in the conventional technologies, the drawings required to be used in the embodiments will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;
fig. 2 to 19 are schematic diagrams illustrating steps of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure.
Detailed Description
As can be seen from the background, as the separation distance between the word line and the semiconductor channel decreases, GIDL (gate-induced drain leakage current) has an increasing effect on the electrical performance of the semiconductor structure. Specifically, for example, a semiconductor structure is taken as a fully-surrounding gate transistor, in order to improve the conductivity of a source, a drain and a channel region of the transistor, a semiconductor column including the source, the drain and the channel region is doped, and the concentrations of doped ions in the source, the drain and the channel region are higher, so that a lateral electric field at a position where a word line corresponds to the semiconductor column is increased, GIDL is generated, the GIDL reduces the proportion of on or off carriers in the channel region, and the word line is difficult to control the closing of the channel region, thereby reducing the electrical performance of the semiconductor structure. Analysis shows that increasing the length of the drain electrode is beneficial to reducing GIDL, but the longer drain electrode is not only not beneficial to small-volume integration, but also can increase the resistance of a semiconductor channel of a transistor, and influences the electrical performance of a semiconductor structure.
The embodiment of the disclosure provides a semiconductor structure and a preparation method thereof, wherein a semiconductor column in the semiconductor structure comprises a first source drain region, a first channel region, a second channel region and a second source drain region which are sequentially distributed along a direction far away from the surface of a substrate, the semiconductor column is used for forming a semiconductor channel of a transistor, the semiconductor column of the first source drain region is used for forming a source electrode of the transistor, the semiconductor column of the second source drain region is used for forming a drain electrode of the transistor, the semiconductor column of the first channel region and the semiconductor column of the second channel region are channel region semiconductor columns used for forming a channel region of the transistor, a word line surrounds the semiconductor column of the channel region, a gate dielectric layer is only positioned in a region between the semiconductor column of the first channel region and the word line, a region between the semiconductor column of the second channel region and the word line is an air gap, and under the condition that the length of the drain electrode is not increased, the air gap is arranged to enable hot electrons in the word line adjacent to be captured by the semiconductor column of the second source drain region, thereby avoiding the hot electrons from being captured by the gate dielectric layer, being beneficial to reducing GIDL, further being beneficial to improving the electrical property of the semiconductor structure and being beneficial to reducing the size of the semiconductor structure.
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the embodiments of the disclosure, numerous technical details are set forth in order to provide a better understanding of the embodiments of the disclosure. However, the claimed embodiments of the present disclosure may be practiced without these specific details or with various changes and modifications based on the following embodiments.
Fig. 1 is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure.
Referring to fig. 1, an aspect of the embodiments of the present disclosure provides a semiconductor structure, including: the semiconductor device comprises a substrate 100, wherein a plurality of semiconductor columns 104 arranged at intervals are arranged on the substrate 100, and the semiconductor columns 104 comprise a first source drain region I, a first channel region II, a second channel region III and a second source drain region IV which are sequentially distributed along the direction far away from the surface of the substrate 100; the gate dielectric layer 120, the gate dielectric layer 120 surrounds the semiconductor pillar 104 side of the first channel region II; the semiconductor device comprises a plurality of word lines 130 extending along a first direction X, wherein each word line 130 surrounds a plurality of semiconductor pillars 104 arranged along the first direction X, the word lines 130 surround a first channel region II and a second channel region III in the semiconductor pillars 104, a gate dielectric layer 120 is arranged between the word lines 130 and the semiconductor pillars 104 of the first channel region II, and an air gap 121 is arranged between the word lines 130 and the semiconductor pillars 104 of the second channel region III.
The material of the substrate 100 is a semiconductor material, and in some embodiments, the material of the substrate 100 is silicon. In other embodiments, the substrate 100 may be a germanium substrate, a silicon carbide substrate, or a silicon-on-insulator substrate.
The semiconductor pillar 104 is a semiconductor channel of a transistor, which in some embodiments may be a full-wrap gate transistor that can achieve a minimum pattern size under given process conditions, which is advantageous for increasing the integration density of the semiconductor structure. In addition, the material of the semiconductor pillars 104 may be the same as that of the substrate 100. In some embodiments, the material of the semiconductor pillars 104 may be silicon.
The direction far away from the surface of the substrate 100 is the extending direction of the semiconductor pillar 104, i.e., the third direction Z, the semiconductor pillar 104 is in the first source-drain region I, the first channel region II, the second channel region III, and the second source-drain region IV which are sequentially distributed along the third direction Z, the first source-drain region I and the second source-drain region IV are the source and the drain of the subsequent transistor, and the first channel region II and the second channel region III are the channel regions of the semiconductor pillar 104 for forming the channel regions of the transistor. The first source drain region I and the second source drain region IV are doped regions, and in some embodiments, the type of the doped ions in the doped regions may be different from the type of the doped ions in the channel region. Specifically, in one example, the dopant ions in the doped region may be N-type ions, the dopant ions in the channel region may be P-type ions, the P-type ions may be at least one of boron ions, indium ions, or gallium ions, and the N-type ions may be at least one of arsenic ions, phosphorus ions, or antimony ions. In another example, the dopant ions in the doped region may be P-type ions and the dopant ions in the channel region may be N-type ions. In other embodiments, the type of dopant ions in the doped region may also be the same as the type of dopant ions in the channel region, i.e., the semiconductor pillar 104 may be used to form a junction-free field effect transistor.
In addition, the semiconductor pillars 104 may be arranged in an array, the arrangement direction of the rows in the semiconductor pillars 104 is a first direction X, the arrangement direction of the columns is a second direction Y, and the first direction X is different from the second direction Y. It should be noted that the definitions of "row" and "column" are opposite, that is, the arrangement direction of the columns may be defined as the first direction X, and the arrangement direction of the rows may be defined as the second direction Y.
The word lines 130 extend along the first direction X and surround the semiconductor pillars 104 in the channel region, and specifically, each word line 130 may surround a row of the semiconductor pillars 104 arranged along the first direction X. The word line 130 serves as a gate of the transistor, and turns on a channel region based on a control signal, thereby realizing the transfer of carriers between the source and the drain. The material of the word line 130 is a conductive material, and in some examples, the material of the word line 130 includes at least one of polysilicon, tungsten, molybdenum, titanium, cobalt, or ruthenium.
The gate dielectric layer 120 is located between the word line 130 and the semiconductor pillar 104 of the first channel region II, and is disposed around the semiconductor pillar 104 of the first channel region II, and the gate dielectric layer 120 is used for enabling the source of the transistor driven by the word line 130 to be conducted with the drain of the transistor. An air gap 121 is formed between the word line 130 and the semiconductor pillar 104 of the second channel region III, the semiconductor pillar 104 of the second channel region III is adjacent to the semiconductor pillar 104 of the second source-drain region IV, the semiconductor pillar 104 of the second source-drain region IV is a drain of a transistor, that is, an air gap 121 is formed between a part of the word line 130 adjacent to the drain and the opposite semiconductor pillar 104, and the air gap 121 is beneficial to enabling hot electrons in the word line 130 adjacent to the drain to be captured by the word line 130, avoiding the hot electrons from being captured by the gate dielectric layer 120, further being beneficial to reducing GIDL and being beneficial to improving the electrical performance of the semiconductor structure.
In some embodiments, the gate dielectric layer 120 may be made of silicon oxide, and a thermal oxidation process is adopted to form silicon oxide on the semiconductor pillar 104 made of silicon, which is beneficial to reducing the difficulty in preparing the gate dielectric layer 120. In other embodiments, the material of the gate dielectric layer 120 may also be silicon nitride or silicon oxynitride.
In some embodiments, the ratio of the length of the gate dielectric layer 120 to the length of the air gap 121 in a direction away from the surface of the substrate 100 is greater than 1: 3. the gate dielectric layer 120 is used to enable the word line 130 to drive the source of the transistor to be conducted with the drain of the transistor, and if the length of the gate dielectric layer 120 along the third direction Z is too small, the ability of the word line 130 to drive current may be reduced, which affects the electrical performance of the semiconductor structure, and even the source of the transistor and the drain of the transistor cannot be conducted, thereby reducing the yield of the semiconductor structure. Setting the ratio of the length of the gate dielectric layer 120 to the length of the air gap 121 to be greater than 1: 3, on one hand, an air gap 121 is ensured between the word line 130 and the semiconductor pillar 104 of the second channel region III, which is beneficial to reducing GIDL; on the other hand, gate dielectric layer 120 is ensured to have a sufficient length so that word line 130 has a better ability to drive the source and drain to be conducted.
In some embodiments, the thickness of the gate dielectric layer 120 is greater than or equal to the width of the air gap 121 along the first direction X. The wider air gap 121 reduces the ability of the word line 130 to drive the source and drain to be conductive, so that the thickness of the gate dielectric layer 120 is greater than the width of the air gap 121, which is beneficial to ensuring the ability of the word line 130 to drive current, and is further beneficial to improving the electrical performance of the semiconductor structure.
In some embodiments, the width of the air gap 121 along the first direction X is in the range of 1-5 nm. The conducting capacity of the word line 130 for driving the source and the drain is reduced when the width of the air gap 121 is too large, and the conducting capacity of the word line 130 for driving the source and the drain cannot be effectively reduced when the width of the air gap 121 is too small, so that the width of the air gap 121 is set to be 1-5 nm, which is beneficial to ensuring the conducting capacity of the word line 130 for driving the source and the drain; on the other hand, the method is beneficial to effectively reducing GIDL and improving the electrical property of the semiconductor structure.
In some embodiments, the word line 130 includes: a first conductive layer 131, the first conductive layer 131 surrounding the semiconductor pillar 104 of the first channel region II; a second conductive layer 132, wherein the second conductive layer 132 is disposed on the surface of the first conductive layer 131 and surrounds the semiconductor pillars 104 in the second channel region III, and the material of the second conductive layer 132 is different from that of the first conductive layer 131. Since the word line 130 and the semiconductor pillar 104 of the second channel region III have the air gap 121 therebetween, in order to ensure that the word line 130 has a better capability of driving the source and the drain to be conducted, the word line 130 may be configured as the first conductive layer 131 and the second conductive layer 132 stacked along the third direction Z and having different materials, and the first conductive layer 131 and the second conductive layer 132 having different materials may be configured to adjust the capability of the word line 130 of driving the source and the drain to be conducted by adjusting the materials of the first conductive layer 131 and the second conductive layer 132. In addition, if the material with better conductivity and higher material preparation cost is the first conductive layer 131, and the material with poorer conductivity and lower material preparation cost is the second conductive layer 132, compared with the word line 130 composed of only the first conductive layer 131 or the word line 130 composed of only the second conductive layer 132, the word line 130 is configured to be the first conductive layer 131 and the second conductive layer 132 with different materials, which is beneficial to reducing the preparation cost. The word line 130 is configured with the first conductive layer 131 and the second conductive layer 132 which are made of different materials, which is not only beneficial to ensuring that the word line 130 has a better capability of driving the conduction of the source and the drain, but also beneficial to reducing the manufacturing cost of the word line 130.
In some embodiments, the work function value of the material of the first conductive layer 131 is different from the work function value of the material of the second conductive layer 132. The smaller the difference between the work function value of the word line 130 and the work function value of the semiconductor pillar 104, the lower the threshold voltage of the transistor, which is beneficial to improve the sensitivity of the channel region to turn on or off. Since the work function values of the semiconductor pillars 104 of different types of transistors (e.g., PMOS or NMOS) are different, different materials of the word lines 130 need to be configured for different transistors to adjust the threshold voltages of the different types of transistors, and configuring different materials of the word lines 130 for different transistors increases the difficulty in manufacturing the semiconductor structure. The word line 130 is configured as the first conductive layer 131 and the second conductive layer 132 having different work function values, so that it is beneficial to adjust the work function value of the word line 130 by adjusting the relevant parameters, such as the material and the thickness of the first conductive layer 131 and the second conductive layer 132, so as to reduce the difference between the work function value of the word line 130 and the work function value of the semiconductor pillar 104. The word line 130 arranged in this way is beneficial to reducing the transverse electric field at the position where the word line 130 corresponds to the semiconductor column 104, further reducing GIDL and improving the sensitivity of controlling the on or off of the channel region; on the other hand, it is beneficial to make the word line 130 suitable for different types of transistors by adjusting and controlling the relevant parameters of the first conductive layer 131 and the second conductive layer 132, thereby being beneficial to reducing the difficulty of manufacturing the semiconductor structure.
In some embodiments, the bottom surface of the first conductive layer 131 is flush with the bottom surface of the gate dielectric layer 120, and the first conductive layer 131 exposes a part of the height of the side surface of the gate dielectric layer 120; the second conductive layer 132 is also located on the side of the gate dielectric layer 120 at the exposed partial height of the first conductive layer 131. Specifically, along the third direction Z, the top surface of the first conductive layer 131 is lower than the top surface of the gate dielectric layer 120, the lower portion of the second conductive layer 132 is attached to the side surface of the portion of the gate dielectric layer 120 exposed by the first conductive layer 131, and the second conductive layer 132 is in contact with the gate dielectric layer 120, so that the influence of the work function change of the second conductive layer 132 on the lateral electric field at the position where the word line 130 corresponds to the semiconductor pillar 104 is more obvious, and the GIDL can be effectively adjusted by adjusting the work function of the second conductive layer 132.
In some embodiments, further comprising: a word line capping layer 105, the word line capping layer 105 covering the top surface of the word line 130 and covering the top opening of the air gap 121. Thus, the bottom surface of the word line capping layer 105, the side surface of the word line 130 opposite to the second channel region III semiconductor pillar 104, the side surface of the second channel region III semiconductor pillar 104 and the top surface of the gate dielectric layer 120 enclose an air gap 121, and the word line capping layer 105 is favorable for preventing subsequent impurities from entering the air gap 121 to affect the performance of the semiconductor structure; on the other hand, the word line capping layer 105 is beneficial to providing support for the structure on top of the air gap 121, and improving the structural stability of the air gap 121 in the semiconductor structure.
In some embodiments, further comprising: a plurality of bit lines 102 extending along the second direction Y, wherein each bit line 102 is located between the plurality of semiconductor pillars 104 arranged along the second direction Y and the substrate 100, and the bit line 102 is electrically connected to the first source/drain region I; and isolation layers positioned between the bit lines 102 and the word lines 130, and also positioned between adjacent word lines 130 and between adjacent bit lines 102. The bit lines 102 are beneficial to leading out the source electrodes of the transistors, and further beneficial to providing electric signals for the source electrodes of the transistors, and the isolation layers are beneficial to realizing isolation between adjacent word lines 130, isolation between adjacent bit lines 102 and isolation between the bit lines 102 and the word lines 130, providing support for subsequent structures and providing support inside a semiconductor structure, and improving stability of the semiconductor structure.
Specifically, the bit line 102 may be in contact with the bottom of a row of semiconductor pillars 104 arranged along the second direction Y, the material of the bit line 102 may be a conductive material, and in some embodiments, the material of the bit line 102 includes a metal silicide, and the metal silicide is a buried bit line 102 formed by using a silicon metallization process. In other embodiments, the material of the bit line 102 may also include metal silicide and metal. The isolation layer is an insulating material, and in some examples, the material of the isolation layer may be at least one of silicon oxide or silicon nitride.
In some embodiments, the isolation layer comprises: a first isolation layer 101, wherein the first isolation layer 101 is positioned between the adjacent semiconductor pillars 104 and between the adjacent bit lines 102, and the top surface of the first isolation layer 101 contacts with the bottom surface of the word line 130 and the bottom surface of the gate dielectric layer 120; and a second isolation layer 103, wherein the second isolation layer 103 extends along the first direction X and penetrates through the first isolation layer 101 between adjacent semiconductor pillars 104 arranged along the second direction Y, the second isolation layer 103 is located between adjacent word lines 130, and the top surface of the second isolation layer 103 is higher than the top surfaces of the word lines 130. The first isolation layer 101 is advantageous for isolation of adjacent bit lines 102 and for providing support for the gate dielectric layer 120 and the word lines 130, and the second isolation layer 103 is advantageous for isolation of adjacent word lines 130.
In some embodiments, the material of the first isolation layer 101 is different from the material of the second isolation layer 103, and the material of the first isolation layer 101 and the material of the second isolation layer 103 which are different from each other are beneficial to selectively remove a part of the material of the first isolation layer 101 or the material of the second isolation layer 103 through different etching processes, so as to form the first isolation layer 101 and the second isolation layer 103 which are different in shape, which is beneficial to reducing the difficulty in preparing the first isolation layer 101 and the second isolation layer 103.
In the semiconductor structure provided by the above embodiment, the semiconductor pillar 104 is used to form a semiconductor channel of a transistor, the semiconductor pillar 104 of the first source-drain region I is used to form a source of the transistor, the semiconductor pillar 104 of the second source-drain region IV is used to form a drain of the transistor, the semiconductor pillar 104 of the first channel region II and the semiconductor pillar 104 of the second channel region III are used to form a channel region semiconductor pillar 104 of a channel of the transistor, the word line 130 surrounds the semiconductor pillar 104 of the channel region, the gate dielectric layer 120 is only located in a region between the semiconductor pillar 104 of the first channel region II and the word line 130, and a region between the semiconductor pillar 104 of the second channel region III and the word line 130 is an air gap 121, where the air gap 121 facilitates that hot electrons in the word line 130 adjacent to the second source-drain region IV semiconductor pillar 104 are captured by the word line 130 without increasing the length of the drain, which is beneficial to reducing GIDL, and facilitates scaling down of semiconductor structures. In addition, the word line 130 may be configured to include the first conductive layer 131 and the second conductive layer 132 with different work function values, so that the difference between the work function value of the word line 130 and the work function value of the semiconductor pillar 104 is reduced by adjusting the relevant parameters of the first conductive layer 131 and the second conductive layer 132, and further the lateral electric field at the position where the word line 130 corresponds to the semiconductor pillar 104 is reduced, thereby further reducing GIDL and improving the electrical performance of the semiconductor structure.
In another aspect, a method for manufacturing a semiconductor structure is provided for manufacturing the semiconductor structure according to the above embodiments, and the method for manufacturing a semiconductor structure according to the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, for the same or corresponding parts as those in the foregoing embodiments, reference may be made to the detailed description of the foregoing embodiments, and details will not be described below.
Fig. 2 to 19 are schematic diagrams illustrating steps of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. In fig. 2 to 19, fig. 6 is a cross-sectional view of the semiconductor structure shown in fig. 5 along a direction perpendicular to the third direction Z and including a semiconductor pillar, fig. 7 and 9 to 19 are cross-sectional views at a-a1 shown in fig. 6, and fig. 8 is a cross-sectional view at C-C1 shown in fig. 6.
Referring to fig. 2 to 5, a substrate 100 is provided, the substrate 100 has a plurality of semiconductor pillars 104 arranged at intervals, the semiconductor pillars 104 include a first source/drain region I, a first channel region II, a second channel region III, and a second source/drain region IV sequentially distributed along a direction away from a surface of the substrate 100, and specifically, an initial substrate is provided, the initial substrate is patterned, a plurality of grooves extending along a first direction X are formed, an isolation material 106 is filled in the grooves, the initial substrate with the isolation material 106 is patterned, a plurality of grooves extending along a second direction Y are formed, and a plurality of semiconductor pillars 104 arranged at intervals are formed. The method for forming the semiconductor pillars 104 by patterning the initial substrate is advantageous for simplifying the process flow and for saving the manufacturing cost. The isolation material 106 may be a more common silicon oxide.
In some embodiments, the initial substrate may be patterned by using a Self-aligned Double Patterning (SADP) process or a Self-aligned Quadruple Patterning (SAQP) process, where the SADP process or the SAQP process may form a pattern with a smaller size, which is beneficial to improving the fineness of the Patterning process of the initial substrate and forming the pillars 104 with a smaller size, thereby being beneficial to reducing the size of the semiconductor structure.
In some embodiments, after the semiconductor pillar 104 is formed, a doping process may be further performed on the semiconductor pillar 104 to form a channel region and doped regions located at two sides of the channel region, that is, a first channel region II, a second channel region III, a first source drain region I, and a second source drain region IV are formed. The doped regions on both sides of the channel region constitute a source and a drain of the semiconductor structure. Specifically, in some embodiments, the semiconductor pillars 104 may be doped using any one of ion implantation or thermal diffusion. In other embodiments, the initial substrate may be doped before the semiconductor pillars 104 are formed, and after the mutually independent semiconductor pillars 104 are formed, the semiconductor pillars 104 may have a channel region and doped regions at both sides of the channel region.
In some embodiments, forming a plurality of bit lines extending along the second direction Y, where the formed bit lines are located between the plurality of semiconductor pillars 104 arranged along the second direction Y and the substrate 100, and the bit lines are electrically connected to the first source/drain regions I. Specifically, referring to fig. 4, a metal silicide process may be used to form a buried bit line at the bottom of the semiconductor pillar 104, and the bit line 102 may be electrically connected to a column of the semiconductor pillars 104 arranged along the second direction Y.
In some embodiments, the method for manufacturing a semiconductor structure further includes, before forming the gate dielectric layer 120: forming a first isolation layer 101 and a second isolation layer 103 on the substrate 100, the first isolation layer 101 being located between adjacent semiconductor pillars 104, a top surface of the first isolation layer 101 being lower than top surfaces of the semiconductor pillars 104, the second isolation layer 103 penetrating the first isolation layer 101 between the adjacent semiconductor pillars 104 along the first direction X, and a top surface of the second isolation layer 103 being higher than the top surfaces of the semiconductor pillars 104 of the second channel region III; the first isolation layer 101 is used to isolate adjacent bit lines, and the second isolation layer 103 is used to isolate adjacent word lines formed later, so as to prevent electrical interference between adjacent conductive structures. In addition, the first isolation layer 101 and the second isolation layer 103 are also used for assisting in forming a subsequent gate dielectric layer and a word line.
Specifically, the steps of forming the first isolation layer 101 and the second isolation layer 103 may be as follows: referring to fig. 4 to 8, a second isolation layer 103 extending along the first direction X is formed in a portion of the groove shown in fig. 4, and a groove outside the second isolation layer 103 is filled with an isolation material 106 to form the structure shown in fig. 5, wherein the manner of forming the isolation material 106 and forming the second isolation layer 103 may be a deposition process. Referring to fig. 7 and 8, a portion of the thickness of isolation material 106 is removed, forming first isolation layer 101.
Referring to fig. 9 to 14, a gate dielectric layer 120 is formed, the gate dielectric layer 120 surrounding the side of the semiconductor pillar 104 of the first channel region II, and referring to fig. 11, in some embodiments, the process step of forming the gate dielectric layer 120 may include: the sacrificial layer 112 is formed on the side surface of the semiconductor pillar 104 in the second channel region III, and the sacrificial layer 112 is favorable for preventing the semiconductor pillar 104 in the second channel region III and the second source/drain region IV from being contaminated when the gate dielectric layer 120 is formed.
Specifically, in some embodiments, the process steps for forming the sacrificial layer 112 include: referring to fig. 9, forming the protection layer 110, wherein the protection layer 110 is located on the top surface of the first isolation layer 101 and covers the side surfaces of the semiconductor pillars 104 of the first channel region II, which is beneficial to prevent the semiconductor pillars 104 of the first channel region II from being contaminated during the process of forming the sacrificial layer 112, and to provide support for the sacrificial layer 112 formed subsequently, which assists in forming the sacrificial layer 112. The material of the protective layer 110 may be silicon oxide. In other embodiments, when the first isolation layer 101 is formed by removing the isolation material 106 with a partial thickness, the height of the top surface of the first isolation layer 101 may be aligned with the height of the top surface of the first channel II semiconductor pillar 104, that is, the first isolation layer 101 with a partial thickness is directly used as the protection layer 110, which is beneficial to reducing the difficulty in preparing the protection layer 110.
Referring to fig. 10, a sacrificial film 111 is formed, the sacrificial film 111 being located on the top surface of the protective layer 110, the side surface of the semiconductor pillar 104 of the second channel region III, and the side surface of the second isolation layer 103; referring to fig. 11, the sacrificial film 111 on the top surface of the protective layer 110 is removed, and the sacrificial film 111 remains as a sacrificial layer 112. Specifically, the sacrificial film 111 may be formed by a deposition process, a back etching process is used to remove a portion of the sacrificial film 111 on the top surface of the protection layer 110, and the sacrificial film 111 on the sidewall of the semiconductor pillar 104 is remained to form the sacrificial layer 112.
In the step of forming the sacrificial layer 112, the sacrificial layer 112 is also formed on the side surface of the second isolation layer 103, and the etching rate of the same etching process to the sacrificial layer 112 is different from the etching rate to the second isolation layer 103. The sacrificial layer 112 and the second isolation layer 103 are made of different materials, the sacrificial layer 112 can be selectively removed by using an etching process with a higher etching selection ratio for the sacrificial layer 112, and the second isolation layer 103 is reserved for assisting in forming the word line 130, which is beneficial to reducing the difficulty in manufacturing the word line 130.
In some embodiments, the sacrificial film 111 is made of the same material as the second isolation layer 103, such as silicon nitride; after removing the sacrificial film 111 on the top surface of the protection layer 110, the method further includes: the remaining sacrificial film 111 is plasma-treated so that the same etching process has a different etching rate for the sacrificial layer 112 than for the second isolation layer 103. The preparation process of the silicon nitride is mature, the selection of the silicon nitride as the sacrificial layer 112 is favorable for reducing the preparation difficulty of the sacrificial layer 112, and if the material of the second isolation layer 103 is the same as that of the sacrificial layer 112, the sacrificial layer 112 needs to be subjected to plasma processing, specifically, the sacrificial layer 112 needs to be subjected to plasma doping processing, so that the sacrificial layer 112 and the second isolation layer 103 have different etching selection ratios, which is further favorable for removing the sacrificial layer 112 by adopting an etching process with a higher etching selection ratio for the sacrificial layer 112, and the second isolation layer 103 for assisting in forming the word line 130 is reserved.
Referring to fig. 12, after the sacrificial layer 112 is formed, a wet etching process with a higher etching selectivity to the protection layer 110 than to the sacrificial layer 112, the second isolation layer 103, the first isolation layer 101 and the semiconductor silicon pillar 104 may be used to remove the protection layer 110, exposing the side surface of the semiconductor pillar 104 of the first channel region II. The semiconductor pillar 104 of the second channel region III and the semiconductor pillar 104 of the second source drain region IV are covered by the sacrificial layer 112, and therefore, referring to fig. 13, the gate dielectric layer 120 may be formed on the side surface of the semiconductor pillar 104 of the first channel region II by performing oxidation treatment on the semiconductor pillar 104 through a thermal oxidation process, which is beneficial to reducing the difficulty in preparing the gate dielectric layer 120. Referring to fig. 14, after forming gate dielectric layer 120, sacrificial layer 112 is removed using an etch process that has a relatively high etch selectivity for sacrificial layer 112 relative to other materials.
Referring to fig. 15 to 18, after removing the sacrificial layer 112, a plurality of word lines 130 extending along the first direction X are formed, each word line 130 surrounds a plurality of semiconductor pillars 104 arranged along the first direction X, the word lines 130 surround a first channel region II and a second channel region III in the semiconductor pillars 104, a gate dielectric layer 120 is disposed between the word lines 130 and the semiconductor pillars 104 of the first channel region II, and an air gap 121 is disposed between the word lines 130 and the semiconductor pillars 104 of the second channel region III. The gap is beneficial to enabling hot electrons in the word line 130 adjacent to the second source drain region IV semiconductor column 104 to be captured by the word line 130 under the condition that the length of the drain electrode is not increased, so that GIDL is reduced, and the electrical performance of the semiconductor structure is improved.
Specifically, referring to fig. 15, in some embodiments, the process steps for forming the word line 130 include: before the word line 130 is formed, an epitaxial process is adopted, an epitaxial layer 113 is formed on the side surface of the semiconductor column 104 of the second channel region III, and the epitaxial layer 113 is favorable for avoiding the subsequently formed word line 130 from contacting the semiconductor column 104 of the second channel region III, so as to assist in forming an air gap and reduce the preparation difficulty of the air gap. Moreover, the epitaxial layer 113 formed by the selective epitaxial process and the gate dielectric layer 120 have different etching selection ratios, which is beneficial to reducing the preparation difficulty of the epitaxial layer 113 and avoiding damage to the gate dielectric layer 120 in the subsequent process of removing the epitaxial layer 113. It should be noted that an epitaxial layer 113 is also formed on the side surface of the second source/drain region IV semiconductor pillar 104, and the material of the epitaxial layer 113 may be silicon germanium.
In some embodiments, referring to fig. 16 and 17, the process steps for forming the word line 130 include: a conductive material is formed on the top surface of the first isolation layer 101, and a portion of the thickness of the conductive material is removed to form a word line 130 surrounding the channel region semiconductor pillar 104.
Referring to fig. 17, the word line 130 covers the side surface of the epitaxial layer 113 in contact with the semiconductor pillar 104 of the second channel region III, and after the word line 130 is formed, referring to fig. 18, the epitaxial layer 113 is removed by using an etching process with a relatively high etching selectivity for the epitaxial layer 113, so that the air gap 121 can be formed. It should be noted that, compared with the method of removing the gate dielectric layer material with a part of the height to form the air gap 121, the method of forming the air gap 121 according to the embodiment of the present disclosure can form the air gap 121 with a controllable shape and can avoid damage to the gate dielectric layer 120, so that the method is beneficial to accurately controlling the shape of the gate dielectric layer 120 and improving the electrical performance of the semiconductor structure.
Referring to fig. 16-17, in some embodiments, the process steps of forming the word line 130 further include: forming a first conductive layer 131, wherein the first conductive layer 131 covers the side surface of the gate dielectric layer 120 and surrounds the semiconductor pillar 104 of the first channel region II; a second conductive layer 132 is formed on the top surface of the first conductive layer 131, and the second conductive layer 132 covers the side surface of the epitaxial layer 113 and surrounds the semiconductor pillars 104 of the second channel region III. That is, the first conductive layer 131 and the second conductive layer 132 with different work function values are formed, so that the lateral electric field at the corresponding position of the word line 130 and the semiconductor pillar 104 can be adjusted by adjusting the relevant parameters of the first conductive layer 131 and the second conductive layer 132, thereby reducing GIDL and further improving the electrical performance of the semiconductor structure.
Specifically, in some embodiments, the process step of forming the first conductive layer 131 may include: forming a first conductive film surrounding the semiconductor pillars 104 of the first channel region II and the second channel region III; and etching back to remove part of the thickness of the first conductive film until the top surface of the remaining first conductive film is lower than the top surface of the gate dielectric layer 120, and using the remaining first conductive film as the first conductive layer 131. The top surface of the first conductive layer 131 is lower than the top surface of the gate dielectric layer 120, so that the second conductive layer 132 is in contact with the gate dielectric layer 120, which is beneficial to making the influence of the work function change of the second conductive layer 132 on the lateral electric field at the position where the word line 130 corresponds to the semiconductor pillar 104 more obvious, and is beneficial to effectively adjusting GIDL by adjusting the work function of the second conductive layer 132.
Referring to fig. 19, in some embodiments, after forming the word line 130, a chemical vapor deposition process with a weak hole filling capability is further performed to form a word line capping layer 105 on the top surface of the word line 130 and at the top opening of the air gap 121. Thus, it is beneficial to prevent impurities from entering the air gap 121, which affects the performance of the semiconductor structure.
The method for forming the semiconductor structure provided by the above embodiment is beneficial to forming the air gap 121 between the word line 130 and the semiconductor pillar 104 of the second channel region III without increasing the length of the drain, so that hot electrons in the word line 130 adjacent to the second source drain region IV semiconductor pillar 104 are captured by the word line 130, thereby being beneficial to reducing GIDL and reducing the size of the semiconductor structure. In addition, compared with the method of forming the air gap 121 and the gate dielectric layer by removing the gate dielectric layer material with a part of height after forming the gate dielectric layer material on the semiconductor pillar 104 in the channel region, the method of forming the air gap 121 by removing the epitaxial layer 113 according to the embodiment of the present disclosure can avoid damage to the gate dielectric layer 120, is beneficial to precise control of the morphology of the gate dielectric layer 120, and is beneficial to improving the electrical performance of the semiconductor structure.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the present disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure in practice. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the disclosure, and it is intended that the scope of the disclosure be limited only by the claims appended hereto.

Claims (18)

1. A semiconductor structure, comprising:
the semiconductor device comprises a substrate, wherein a plurality of semiconductor columns are arranged on the substrate at intervals, and each semiconductor column comprises a first source drain region, a first channel region, a second channel region and a second source drain region which are sequentially distributed along the direction far away from the surface of the substrate;
the gate dielectric layer surrounds the side face of the semiconductor column of the first channel region;
the semiconductor device comprises a plurality of semiconductor columns arranged along a first direction, a plurality of word lines extending along the first direction, a plurality of word lines arranged along the first direction, a plurality of semiconductor columns arranged along the first direction, a plurality of gate dielectric layers arranged between the word lines and the semiconductor columns in the first channel region, and a plurality of semiconductor columns arranged along the first direction.
2. The semiconductor structure of claim 1, wherein a ratio of a length of the gate dielectric layer to a length of the air gap in a direction away from the substrate surface is greater than 1: 3.
3. the semiconductor structure of claim 1, wherein a thickness of the gate dielectric layer along the first direction is greater than or equal to a width of the air gap.
4. The semiconductor structure of claim 3, wherein a width of the air gap along the first direction is in a range of 1-5 nm.
5. The semiconductor structure of claim 1, wherein the word line comprises: a first conductive layer surrounding the semiconductor pillar of the first channel region; the second conducting layer is positioned on the surface of the first conducting layer and surrounds the semiconductor pillar of the second channel region, and the material of the second conducting layer is different from that of the first conducting layer.
6. The semiconductor structure of claim 5, wherein a work function value of a material of the first conductive layer is different from a work function value of a material of the second conductive layer.
7. The semiconductor structure of claim 5, wherein a bottom surface of the first conductive layer is flush with a bottom surface of the gate dielectric layer, and the first conductive layer is exposed at a portion of the height of the side surface of the gate dielectric layer; the second conducting layer is also positioned on the side surface of the gate dielectric layer with the exposed part of the height of the first conducting layer.
8. The semiconductor structure of claim 1, further comprising: a word line capping layer covering the word line top surface and covering the top opening of the air gap.
9. The semiconductor structure of claim 1, further comprising:
a plurality of bit lines extending along a second direction, each of the bit lines being located between the plurality of semiconductor pillars arranged along the second direction and the substrate, and the bit lines being electrically connected to the first source drain regions;
an isolation layer between the bit lines and the word lines, and also between adjacent word lines and between adjacent bit lines.
10. The semiconductor structure of claim 9, wherein the isolation layer comprises:
the first isolation layers are positioned between the adjacent semiconductor pillars and between the adjacent bit lines, and the top surfaces of the first isolation layers are contacted with the bottom surfaces of the word lines and the bottom surfaces of the gate dielectric layers;
the second isolation layer extends along the first direction and penetrates through the first isolation layer between the adjacent semiconductor columns distributed along the second direction, the second isolation layer is located between the adjacent word lines, and the top surface of the second isolation layer is higher than the top surfaces of the word lines.
11. A method of fabricating a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a plurality of semiconductor columns which are arranged at intervals, and the semiconductor columns comprise a first source drain region, a first channel region, a second channel region and a second source drain region which are sequentially distributed along the direction far away from the surface of the substrate;
forming a gate dielectric layer, wherein the gate dielectric layer surrounds the side face of the semiconductor column of the first channel region;
forming a plurality of word lines extending along a first direction, wherein each word line surrounds a plurality of semiconductor columns arranged along the first direction, the word lines surround the first channel regions and the second channel regions in the semiconductor columns, the gate dielectric layer is arranged between the word lines and the semiconductor columns in the first channel regions, and an air gap is arranged between the word lines and the semiconductor columns in the second channel regions.
12. The method of fabricating a semiconductor structure of claim 11, wherein the step of forming the gate dielectric layer comprises:
forming a sacrificial layer on the side face of the semiconductor pillar of the second channel region;
carrying out oxidation treatment on the side face of the semiconductor column in the first channel region to form the gate dielectric layer;
and removing the sacrificial layer.
13. The method of fabricating a semiconductor structure of claim 12, further comprising, prior to forming the gate dielectric layer: forming a first isolation layer and a second isolation layer on the substrate, wherein the first isolation layer is positioned between the adjacent semiconductor columns, the top surface of the first isolation layer is lower than the top surfaces of the semiconductor columns, the second isolation layer penetrates through the first isolation layer between the adjacent semiconductor columns along the first direction, and the top surface of the second isolation layer is higher than the top surfaces of the semiconductor columns of the second channel region;
in the step of forming the sacrificial layer, the sacrificial layer is further formed on the side face of the second isolation layer, and the etching rate of the same etching process to the sacrificial layer is different from the etching rate to the second isolation layer.
14. The method of fabricating a semiconductor structure of claim 13, wherein the process step of forming the sacrificial layer comprises:
forming a protective layer which is positioned on the top surface of the first isolation layer and covers the side surface of the semiconductor pillar of the first channel region;
forming a sacrificial film on the top surface of the protection layer, the side surface of the semiconductor pillar of the second channel region and the side surface of the second isolation layer;
and removing the sacrificial film on the top surface of the protective layer, and taking the remaining sacrificial film as the sacrificial layer.
15. The method of fabricating a semiconductor structure according to claim 14, wherein the sacrificial film is made of silicon nitride, and the second spacer is made of silicon nitride; after removing the sacrificial film on the top surface of the protection layer, the method further comprises: and carrying out plasma treatment on the rest sacrificial film so as to enable the etching rate of the same etching process to the sacrificial layer to be different from the etching rate of the same etching process to the second isolation layer.
16. The method of fabricating a semiconductor structure according to claim 11, further comprising, prior to forming the word line:
forming an epitaxial layer on the side face of the semiconductor column of the second channel region by adopting an epitaxial process;
in the process step of forming the word line, the word line covers the side face of the epitaxial layer;
after the word line is formed, the epitaxial layer is removed to form the air gap.
17. The method of fabricating a semiconductor structure of claim 16, wherein the process step of forming the word line comprises: forming a first conductive layer, wherein the first conductive layer covers the side face of the gate dielectric layer and surrounds the semiconductor pillar of the first channel region;
and forming a second conductive layer on the top surface of the first conductive layer, wherein the second conductive layer covers the side surface of the epitaxial layer and surrounds the semiconductor pillar of the second channel region.
18. The method of fabricating a semiconductor structure of claim 17, wherein the process step of forming the first conductive layer comprises:
forming a first conductive film surrounding the semiconductor pillars of the first and second channel regions;
and etching back to remove part of the thickness of the first conductive film until the top surface of the remained first conductive film is lower than the top surface of the gate dielectric layer, and the remained first conductive film is used as the first conductive layer.
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CN116390485A (en) * 2023-06-06 2023-07-04 长鑫存储技术有限公司 Semiconductor structure and preparation method thereof

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CN116390485A (en) * 2023-06-06 2023-07-04 长鑫存储技术有限公司 Semiconductor structure and preparation method thereof
CN116390485B (en) * 2023-06-06 2023-10-24 长鑫存储技术有限公司 Semiconductor structure and preparation method thereof

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