TW201909340A - Dynamic random access memory and method of manufacturing the same - Google Patents

Dynamic random access memory and method of manufacturing the same Download PDF

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TW201909340A
TW201909340A TW106123317A TW106123317A TW201909340A TW 201909340 A TW201909340 A TW 201909340A TW 106123317 A TW106123317 A TW 106123317A TW 106123317 A TW106123317 A TW 106123317A TW 201909340 A TW201909340 A TW 201909340A
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random access
access memory
dynamic random
substrate
conductor
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TW106123317A
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TWI640064B (en
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竹迫壽晃
陳皇男
張維哲
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華邦電子股份有限公司
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Abstract

A dynamic random access memory (DRAM) includes a substrate, isolation structures, word line sets, bit-line structures, spacers, capacitors, and capacitor contacts. The isolation structures are located in the substrate to divided the substrate into active regions. The active areas are configured in the shape of band and arranged as an array. The word line sets are disposed in the substrate in parallel in a Y direction. The bit-line structures are disposed on the substrate in parallel in a X direction and across the word line sets. The spacers are disposed on sidewalls of the substrate in parallel in the X direction, wherein the spacers include silicon oxide. The capacitors are respectively disposed at two terminal of the long side of each of the active areas. The capacitor contacts are respectively located between the capacitors and the active regions.

Description

動態隨機存取記憶體及其製造方法Dynamic random access memory and manufacturing method thereof

本發明是有關於一種記憶元件及其製造方法,且特別是有關於一種動態隨機存取記憶體及其製造方法。The present invention relates to a memory element and a method of fabricating the same, and more particularly to a dynamic random access memory and a method of fabricating the same.

動態隨機存取記憶體屬於一種揮發性記憶體,其是由多個記憶胞所構成。詳細地說,每一個記憶胞主要是由一個電晶體與一個由電晶體所操控的電容器所構成,且每一個記憶胞藉由字元線與位元線彼此電性連接。為提升動態隨機存取記憶體的積集度以加快元件的操作速度,並符合消費者對於小型化電子裝置的需求,近年來發展出埋入式字元線動態隨機存取記憶體(buried word line DRAM),以滿足上述種種需求。The DRAM is a kind of volatile memory, which is composed of a plurality of memory cells. In detail, each memory cell is mainly composed of a transistor and a capacitor controlled by a transistor, and each of the memory cells is electrically connected to each other by a word line and a bit line. In order to improve the accumulative degree of dynamic random access memory to speed up the operation speed of components and meet the consumer demand for miniaturized electronic devices, buried word line dynamic random access memory (buried word) has been developed in recent years. Line DRAM) to meet the above needs.

在先前技術中,常使用較厚的位元線間隙壁來減少相鄰位元線之間的寄生電容。然而,在記憶體的積集度提高與元件尺寸縮小的情況下,較厚的位元線間隙壁會壓縮電容器接觸窗(Capacitor Contact)的線寬,使得電容器接觸窗與主動區之間的接觸面積縮小。由於電容器接觸窗與主動區之間的接觸面積變小,將使得電容器接觸窗與主動區之間的阻值增加,進而降低產品可靠度。因此,如何發展一種動態隨機存取記憶體及其製造方法,其可降低相鄰位元線之間的寄生電容並維持電容器接觸窗與主動區之間的接觸面積將成為重要的一門課題。In the prior art, thicker bit line spacers are often used to reduce parasitic capacitance between adjacent bit lines. However, in the case where the memory is increased and the component size is reduced, the thicker bit line spacer compresses the line width of the capacitor contact window, so that the contact between the capacitor contact window and the active region is made. The area is reduced. As the contact area between the capacitor contact window and the active region becomes smaller, the resistance between the capacitor contact window and the active region is increased, thereby reducing product reliability. Therefore, how to develop a dynamic random access memory and a manufacturing method thereof, which can reduce the parasitic capacitance between adjacent bit lines and maintain the contact area between the capacitor contact window and the active area will become an important subject.

本發明提供一種動態隨機存取記憶體及其製造方法,其可降低相鄰位元線之間的寄生電容並維持電容器接觸窗與主動區之間的接觸面積。The present invention provides a dynamic random access memory and a method of fabricating the same that can reduce parasitic capacitance between adjacent bit lines and maintain a contact area between a capacitor contact window and an active area.

本發明提供一種動態隨機存取記憶體,包括:基底、多個隔離結構、多個字元線組、多個位元線結構、多個間隙壁、多個電容器以及多個電容器接觸窗。所述隔離結構位於所述基底中,以將所述基底分隔成多個主動區。所述主動區被配置成帶狀且排列成一陣列。所述字元線組沿著Y方向平行配置於所述基底中。所述位元線結構沿著X方向平行配置於所述基底上,且橫越所述字元線組。所述間隙壁沿著X方向平行配置於所述位元線結構的側壁上,其中所述間隙壁包括氧化矽。所述電容器分別配置於所述主動區的長邊的兩端點上。所述電容器接觸窗分別位於所述電容器與所述主動區之間。The present invention provides a dynamic random access memory comprising: a substrate, a plurality of isolation structures, a plurality of word line groups, a plurality of bit line structures, a plurality of spacers, a plurality of capacitors, and a plurality of capacitor contact windows. The isolation structure is located in the substrate to divide the substrate into a plurality of active regions. The active regions are arranged in a strip shape and arranged in an array. The word line groups are arranged in parallel in the substrate along the Y direction. The bit line structures are disposed in parallel along the X direction on the substrate and traverse the word line set. The spacers are disposed in parallel along the X direction on sidewalls of the bit line structure, wherein the spacers comprise ruthenium oxide. The capacitors are respectively disposed at two ends of the long sides of the active region. The capacitor contact windows are respectively located between the capacitor and the active region.

本發明提供一種動態隨機存取記憶體的製造方法,其步驟如下。於基底中形成多個隔離結構,以將所述基底分隔成多個主動區。所述主動區被配置成帶狀且排列成一陣列。於所述基底中形成多個字元線組。所述字元線組沿著Y方向延伸並穿過所述隔離結構與所述主動區,以將所述基底分成多個第一區與多個第二區。所述第一區與所述第二區沿著X方向交替排列且所述字元線組位於所述第一區中。於所述基底上形成多個位元線結構。所述位元線結構沿著所述X方向延伸並橫跨所述字元線組。於所述位元線結構的側壁上分別形成多個間隙壁。於所述第二區的所述基底上形成多個導體層。於所述第一區的所述基底上形成多個第一介電層。所述導體層的頂面低於所述第一介電層的頂面。於所述導體層中分別形成多個第二介電層。各所述第二介電層將所對應的導體層分隔成兩個導體柱。所述第一介電層的材料與所述第二介電層的材料相同。於所述導體柱上分別形成多個電容器。The present invention provides a method of fabricating a dynamic random access memory, the steps of which are as follows. A plurality of isolation structures are formed in the substrate to divide the substrate into a plurality of active regions. The active regions are arranged in a strip shape and arranged in an array. A plurality of word line groups are formed in the substrate. The set of word lines extends along the Y direction and passes through the isolation structure and the active area to divide the substrate into a plurality of first regions and a plurality of second regions. The first zone and the second zone are alternately arranged along the X direction and the word line group is located in the first zone. A plurality of bit line structures are formed on the substrate. The bit line structure extends along the X direction and spans the word line set. A plurality of spacers are respectively formed on sidewalls of the bit line structure. A plurality of conductor layers are formed on the substrate of the second region. A plurality of first dielectric layers are formed on the substrate of the first region. The top surface of the conductor layer is lower than the top surface of the first dielectric layer. A plurality of second dielectric layers are respectively formed in the conductor layer. Each of the second dielectric layers divides the corresponding conductor layer into two conductor posts. The material of the first dielectric layer is the same as the material of the second dielectric layer. A plurality of capacitors are respectively formed on the conductor post.

基於上述,本發明藉由先形成導體層,再於導體層中形成第一介電層與第二介電層,以將導體層分隔成多個導體柱(或電容器接觸窗)。因此,本發明可簡化電容器接觸窗的製造方法並使得電容器接觸窗維持為柱狀結構。而且所形成的電容器接觸窗的底部寬度可大於或等於電容器接觸窗的頂部寬度,其可降低電容器接觸窗與主動區之間的阻值,藉此增加動態隨機存取記憶體的讀取速度,進而提升產品效率與可靠度。另外,本發明將配置於位元線結構的側壁上的間隙壁的材料置換為氧化矽,以降低相鄰位元線結構之間的寄生電容,進而提升記憶體的效能。此外,本發明將電容器接觸窗旁的介電層的材料皆置換為氮化矽,其可避免過度蝕刻而導致相鄰兩個電容器接觸窗短路的問題。Based on the above, the present invention divides the conductor layer into a plurality of conductor pillars (or capacitor contact windows) by first forming a conductor layer and then forming a first dielectric layer and a second dielectric layer in the conductor layer. Therefore, the present invention can simplify the manufacturing method of the capacitor contact window and maintain the capacitor contact window as a columnar structure. Moreover, the bottom width of the formed capacitor contact window may be greater than or equal to the top width of the capacitor contact window, which may reduce the resistance between the capacitor contact window and the active region, thereby increasing the read speed of the dynamic random access memory. In turn, improve product efficiency and reliability. In addition, the present invention replaces the material of the spacers disposed on the sidewalls of the bit line structure with yttrium oxide to reduce the parasitic capacitance between adjacent bit line structures, thereby improving the performance of the memory. In addition, the present invention replaces the material of the dielectric layer next to the capacitor contact window with tantalum nitride, which avoids the problem of over-etching causing short-circuiting of adjacent two capacitor contact windows.

為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.

參照本實施例之圖式以更全面地闡述本發明。然而,本發明亦可以各種不同的形式體現,而不應限於本文中所述之實施例。圖式中的層與區域的厚度會為了清楚起見而放大。相同或相似之標號表示相同或相似之元件,以下段落將不再一一贅述。The invention will be more fully described with reference to the drawings of the embodiments. However, the invention may be embodied in a variety of different forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings will be exaggerated for clarity. The same or similar reference numerals indicate the same or similar elements, and the following paragraphs will not be repeated.

圖1是本發明之一實施例的動態隨機存取記憶體的上視示意圖。請參照圖1,本實施例提供一種動態隨機存取記憶體包括:基底100、多個隔離結構101、多個主動區AA、多個位元線結構102、多個字元線組202以及多個電容器接觸窗CC1、CC2。為圖面清楚起見,圖1僅顯示上述構件,其他結構可見於後續圖2A至圖7的剖面圖。1 is a top plan view of a dynamic random access memory according to an embodiment of the present invention. Referring to FIG. 1, the embodiment provides a dynamic random access memory including: a substrate 100, a plurality of isolation structures 101, a plurality of active areas AA, a plurality of bit line structures 102, a plurality of word line groups 202, and a plurality of Capacitors contact windows CC1, CC2. For the sake of clarity of the drawing, FIG. 1 only shows the above-mentioned members, and other structures can be seen in the subsequent cross-sectional views of FIGS. 2A to 7.

如圖1所示,基底100包括多個第一區R1與多個第二區R2。第一區R1與第二區R2沿著X方向相互排列。隔離結構101配置於基底100中,以將基底100定義出多個主動區(active areas)AA。換言之,相鄰兩個主動區AA之間具有隔離結構101。在一實施例中,一個主動區AA上只形成有一個記憶單元,且各記憶單元之間由隔離結構101分隔,以有效減少記憶單元之間的干擾問題。詳細地說,主動區AA被配置為帶狀且排列成一陣列。在本實施例中,主動區AA排列成3個主動區行(active area columns)AC1~AC3,且相鄰兩個主動區行呈鏡像配置。舉例來說,主動區行AC3的長邊方向與X方向呈現非正交而具有夾角θ,主動區行AC2的長邊方向與X方向呈現非正交而具有夾角(180º-θ)。在一實施例中,夾角θ可介於15度至75度之間。但本發明不以此為限,在其他實施例中,相鄰兩個主動區行亦可以是相同配置。As shown in FIG. 1, the substrate 100 includes a plurality of first regions R1 and a plurality of second regions R2. The first region R1 and the second region R2 are arranged to each other along the X direction. The isolation structure 101 is disposed in the substrate 100 to define the substrate 100 with a plurality of active areas AA. In other words, there is an isolation structure 101 between two adjacent active areas AA. In an embodiment, only one memory unit is formed on one active area AA, and each memory unit is separated by an isolation structure 101 to effectively reduce the interference problem between the memory units. In detail, the active areas AA are configured in a strip shape and arranged in an array. In this embodiment, the active area AA is arranged in three active area columns AC1~AC3, and the adjacent two active area lines are mirrored. For example, the long side direction of the active area row AC3 and the X direction are non-orthogonal and have an included angle θ, and the long side direction of the active area line AC2 and the X direction are non-orthogonal and have an included angle (180o-θ). In an embodiment, the included angle θ may be between 15 degrees and 75 degrees. However, the present invention is not limited thereto. In other embodiments, the adjacent two active area lines may also be the same configuration.

位元線結構102位於基底100上,且橫越第一區R1與第二區R2。位元線結構102沿著X方向延伸,且沿著Y方向相互排列。字元線組202位於第一區R1的基底100中。字元線組202沿著Y方向D2,且沿著X方向相互排列。每一字元線組202具有兩個埋入式字元線202a、202b。在一實施例中,X方向與Y方向實質上互相垂直。The bit line structure 102 is located on the substrate 100 and traverses the first region R1 and the second region R2. The bit line structures 102 extend in the X direction and are arranged in the Y direction. The word line group 202 is located in the substrate 100 of the first region R1. The word line group 202 is arranged along the Y direction D2 and along the X direction. Each word line set 202 has two buried word lines 202a, 202b. In an embodiment, the X direction and the Y direction are substantially perpendicular to each other.

在本實施例中,每一主動區AA具有長邊L1與短邊L2,且長邊L1橫越所對應的字元線組202(即兩個埋入式字元線202a、202b),且每一主動區AA與所對應的位元線結構102的重疊處具有位元線接觸窗BC。因此,每一位元線結構102在橫越所對應的字元線組202時,可利用位元線接觸窗BC來電性連接所對應的摻雜區(未繪示),其中所述摻雜區位於兩個埋入式字元線202a、202b之間。In this embodiment, each active area AA has a long side L1 and a short side L2, and the long side L1 traverses the corresponding word line group 202 (ie, two buried word lines 202a, 202b), and Each of the active areas AA has a bit line contact window BC at an overlap with the corresponding bit line structure 102. Therefore, each bit line structure 102 can be electrically connected to a corresponding doped region (not shown) by using a bit line contact window BC when traversing the corresponding word line group 202, wherein the doping is performed. The zone is located between the two buried word lines 202a, 202b.

電容器接觸窗CC1、CC2位於位元線結構102之間的基底100上。詳細地說,電容器接觸窗CC1、CC2分別配置在主動區AA的長邊L1的兩端點上,其可電性連接主動區AA與後續形成的電容器(未繪示)。另外,雖然電容器接觸窗CC1、CC2在圖1中顯示為矩形,但實際上形成的接觸窗會略呈圓形,且其大小可依製程需求來設計。Capacitor contact windows CC1, CC2 are located on substrate 100 between bit line structures 102. In detail, the capacitor contact windows CC1 and CC2 are respectively disposed at the two end points of the long side L1 of the active area AA, and are electrically connected to the active area AA and a subsequently formed capacitor (not shown). In addition, although the capacitor contact windows CC1, CC2 are shown as rectangular in FIG. 1, the contact window actually formed is slightly rounded, and its size can be designed according to process requirements.

圖2A至圖2C是沿著圖1之A-A’線段的動態隨機存取記憶體之製造流程的剖面示意圖。圖3A至圖3E、圖4、圖5A至圖5C以及圖6-7是沿著圖1之B-B’線段的動態隨機存取記憶體之製造流程的剖面示意圖。2A to 2C are schematic cross-sectional views showing a manufacturing flow of a dynamic random access memory along the line A-A' of Fig. 1. 3A to 3E, 4, 5A to 5C, and 6-7 are schematic cross-sectional views showing a manufacturing flow of the dynamic random access memory along the line B-B' of Fig. 1.

請同時參照圖1與圖2A,本實施例提供一種動態隨機存取記憶體的製造方法,其步驟如下。首先,提供一初始結構,其包括基底100、多個隔離結構101以及多個字元線組202。隔離結構101以及字元線組202皆位於基底100中。由於圖2A至圖2C的剖面中並未繪示出字元線組202,因此,關於字元線組202的詳細說明請參照後續圖3A。在本實施例中,基底100可例如為半導體基底、半導體化合物基底或是絕緣層上有半導體基底(Semiconductor Over Insulator,SOI)。Referring to FIG. 1 and FIG. 2A simultaneously, the embodiment provides a method for manufacturing a dynamic random access memory, and the steps are as follows. First, an initial structure is provided that includes a substrate 100, a plurality of isolation structures 101, and a plurality of word line groups 202. The isolation structure 101 and the word line set 202 are all located in the substrate 100. Since the word line group 202 is not shown in the cross section of FIGS. 2A to 2C, a detailed description of the word line group 202 will be described later with reference to FIG. 3A. In this embodiment, the substrate 100 can be, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor substrate (Semiconductor Over Insulator (SOI)).

如圖1與圖2A所示,隔離結構101配置於基底100,以將基底100分隔出多個主動區AA。在一實施例中,隔離結構101包括介電材料,所述介電材料可以是氧化矽。在一實施例中,隔離結構101可例如是淺溝渠隔離結構(STI)。As shown in FIG. 1 and FIG. 2A, the isolation structure 101 is disposed on the substrate 100 to separate the substrate 100 from the plurality of active regions AA. In an embodiment, the isolation structure 101 comprises a dielectric material, which may be tantalum oxide. In an embodiment, the isolation structure 101 can be, for example, a shallow trench isolation structure (STI).

如圖1與圖3A所示,多個字元線組202配置於第一區R1的基底100中。詳細地說,每一字元線組202包括兩個埋入式字元線202a、202b。每一埋入式字元線202a包括閘極204a以及閘介電層206a。閘介電層206a圍繞閘極204a,以電性隔離閘極204a與基底100。在一實施例中,閘極204a的材料包括導體材料,所述導體材料可例如是金屬材料、阻障金屬材料或其組合,其形成方法可以是化學氣相沈積法或物理氣相沈積法。閘介電層206a的材料可例如是氧化矽,其形成方法可以是化學氣相沉積法、熱氧化法或臨場蒸氣產生法(in situ steam generation,ISSG)等。相似地,另一埋入式字元線202b 包括閘極204b以及閘介電層206b。閘介電層206b圍繞閘極204b,以電性隔離閘極204b與基底100。另外,所述初始結構更包括氮化矽層208。詳細地說,氮化矽層208配置於埋入式字元線202a、202b上。在一實施例中,氮化矽層208的形成方法可以是化學氣相沈積法。As shown in FIGS. 1 and 3A, a plurality of word line groups 202 are disposed in the substrate 100 of the first region R1. In detail, each word line group 202 includes two buried word lines 202a, 202b. Each buried word line 202a includes a gate 204a and a gate dielectric layer 206a. The gate dielectric layer 206a surrounds the gate 204a to electrically isolate the gate 204a from the substrate 100. In one embodiment, the material of the gate 204a includes a conductive material, which may be, for example, a metal material, a barrier metal material, or a combination thereof, which may be formed by chemical vapor deposition or physical vapor deposition. The material of the gate dielectric layer 206a may be, for example, hafnium oxide, which may be formed by a chemical vapor deposition method, a thermal oxidation method, or an in situ steam generation (ISSG). Similarly, another buried word line 202b also includes a gate 204b and a gate dielectric layer 206b. The gate dielectric layer 206b surrounds the gate 204b to electrically isolate the gate 204b from the substrate 100. Additionally, the initial structure further includes a tantalum nitride layer 208. In detail, the tantalum nitride layer 208 is disposed on the buried word lines 202a and 202b. In an embodiment, the method of forming the tantalum nitride layer 208 may be a chemical vapor deposition method.

請回頭參照圖1與圖2A,在初始結構(或基底100)上形成多個位元線結構102。在圖2A的剖面上,位元線結構102由下而上包括氧化矽層104、氮化矽層106、阻障層108、位元線110以及頂蓋層112。第一間隙壁114覆蓋氮化矽層106的側壁、阻障層108的側壁、位元線110的側壁以及頂蓋層112的側壁。第二間隙壁116覆蓋第一間隙壁114的側壁與氧化矽層104的側壁。另一方面,在沿著主動區AA的剖面上,位元線結構102由下而上包括位元線接觸窗(未繪示)、阻障層108、位元線110以及頂蓋層112。位元線結構102可藉由位元線接觸窗(未繪示)來電性連接主動區AA(即源極/汲極摻雜區)。Referring back to Figures 1 and 2A, a plurality of bit line structures 102 are formed on the initial structure (or substrate 100). In the cross-section of FIG. 2A, the bit line structure 102 includes a hafnium oxide layer 104, a tantalum nitride layer 106, a barrier layer 108, a bit line 110, and a cap layer 112 from bottom to top. The first spacers 114 cover sidewalls of the tantalum nitride layer 106, sidewalls of the barrier layer 108, sidewalls of the bit lines 110, and sidewalls of the cap layer 112. The second spacer 116 covers the sidewall of the first spacer 114 and the sidewall of the ruthenium oxide layer 104. On the other hand, on the cross section along the active area AA, the bit line structure 102 includes a bit line contact window (not shown), a barrier layer 108, a bit line 110, and a cap layer 112 from bottom to top. The bit line structure 102 can be electrically connected to the active area AA (ie, the source/drain doped area) by a bit line contact window (not shown).

在一實施例中,位元線接觸窗(未繪示)的材料可以是多晶矽或矽鍺。阻障層108的材料包括阻障金屬材料,其可例如是TiN。位元線110的材料可以是金屬材料,其可例如是W。頂蓋層112的材料可以是氮化矽。另外,在位元線接觸窗(未繪示)與位元線110之間亦可包括矽化金屬層(未繪示),其可例如是TiSi、CoSi、NiSi或其組合。In an embodiment, the material of the bit line contact window (not shown) may be polysilicon or germanium. The material of the barrier layer 108 includes a barrier metal material, which may be, for example, TiN. The material of the bit line 110 may be a metal material, which may be, for example, W. The material of the cap layer 112 may be tantalum nitride. In addition, a deuterated metal layer (not shown) may be included between the bit line contact window (not shown) and the bit line 110, which may be, for example, TiSi, CoSi, NiSi, or a combination thereof.

需注意的是,第一間隙壁114與第二間隙壁116可以是沿著X方向延伸的條狀形式,其可保護位元線結構102的側壁,以電性隔離位元線結構102與後續形成的導體材料118(如圖2B所示)。另外,第一間隙壁114的材料可以是氮化矽,而第二間隙壁116的材料可以是氧化矽。第一間隙壁114與第二間隙壁116形成方法類似習知間隙壁的形成方法,於此便不再詳述。在一實施例中,由於第二間隙壁116為氧化矽,因此,相較於習知的氮化矽,本實施例之第二間隙壁116可有效地降低相鄰位元線結構102之間的寄生電容,進而提升記憶體的效能。但本發明不以此為限,第二間隙壁116的材料可以是其他低介電常數材料(亦即介電常數低於4的介電材料)。另外,在形成第一間隙壁114的第二間隙壁116之後,位元線結構102之間具有多個開口10。開口10至少暴露出基底100(或主動區AA)的頂面。在替代實施例中,如圖2A所示,亦可移除部分矽基底100,使得開口10的底面低於基底100的頂面。It should be noted that the first spacers 114 and the second spacers 116 may be in the form of strips extending along the X direction, which may protect sidewalls of the bit line structures 102 to electrically isolate the bit line structures 102 and subsequent A conductor material 118 is formed (as shown in Figure 2B). In addition, the material of the first spacers 114 may be tantalum nitride, and the material of the second spacers 116 may be tantalum oxide. The method of forming the first spacers 114 and the second spacers 116 is similar to the conventional method of forming the spacers, and will not be described in detail herein. In one embodiment, since the second spacers 116 are yttria, the second spacers 116 of the present embodiment can effectively reduce the spacing between adjacent bit line structures 102 compared to conventional tantalum nitrides. The parasitic capacitance increases the performance of the memory. However, the present invention is not limited thereto, and the material of the second spacer 116 may be other low dielectric constant materials (that is, dielectric materials having a dielectric constant lower than 4). Additionally, after forming the second spacers 116 of the first spacers 114, there are a plurality of openings 10 between the bit line structures 102. The opening 10 exposes at least the top surface of the substrate 100 (or active area AA). In an alternate embodiment, as shown in FIG. 2A, a portion of the crucible substrate 100 may also be removed such that the bottom surface of the opening 10 is lower than the top surface of the substrate 100.

請同時參照圖2A與圖2B,在初始結構(或基底100)上形成導體材料118。導體材料118填入位元線結構102之間的開口10中,並延伸覆蓋位元線結構102的頂面。導體材料118可以是多晶矽,其形成方法可以是化學氣相沈積法。Referring to Figures 2A and 2B at the same time, conductor material 118 is formed on the initial structure (or substrate 100). Conductor material 118 fills into opening 10 between bit line structures 102 and extends over the top surface of bit line structure 102. The conductor material 118 may be polycrystalline germanium, which may be formed by chemical vapor deposition.

請同時參照圖2B與圖2C,在導體材料118上依序形成氧化矽層120、碳層122以及氮氧化矽層124。在一實施例中,氧化矽層120、碳層122以及氮氧化矽層124的複合層可視為硬罩幕層HM。在一實施例中,氧化矽層120可例如是四乙氧基矽烷。Referring to FIG. 2B and FIG. 2C simultaneously, a ruthenium oxide layer 120, a carbon layer 122, and a ruthenium oxynitride layer 124 are sequentially formed on the conductor material 118. In one embodiment, the composite layer of yttrium oxide layer 120, carbon layer 122, and yttrium oxynitride layer 124 can be considered a hard mask layer HM. In an embodiment, the ruthenium oxide layer 120 can be, for example, tetraethoxy decane.

請同時參照圖2C與圖3A,在氮氧化矽層124(或硬罩幕層HM)上形成光阻圖案126。光阻圖案126具有多個開口12。開口12可以是條狀開口,其沿著Y方向延伸,並暴露出氮氧化矽層124的部分表面。另一方面來看,開口12僅位於第一區R1的基底100上,其對應第一區R1的基底100中的字元線組202。另外,由於開口12僅繪示於圖1之B-B’線段的剖面(亦即圖3A)上,因此,後續製程皆沿著圖1之B-B’線段的剖面來詳細說明。Referring to FIG. 2C and FIG. 3A simultaneously, a photoresist pattern 126 is formed on the yttrium oxynitride layer 124 (or the hard mask layer HM). The photoresist pattern 126 has a plurality of openings 12. The opening 12 may be a strip-shaped opening that extends in the Y direction and exposes a portion of the surface of the yttria layer 124. On the other hand, the opening 12 is located only on the substrate 100 of the first region R1, which corresponds to the word line group 202 in the substrate 100 of the first region R1. In addition, since the opening 12 is only shown in the section of the line B-B' of Fig. 1 (i.e., Fig. 3A), the subsequent processes are described in detail along the section of the line B-B' of Fig. 1.

請同時參照圖3A與圖3B,以光阻圖案126為罩幕,移除部分硬罩幕層HM與部分導體材料118,以在剩餘的氧化矽層120a與導體層118a中形成多個開口14。開口14可以是條狀開口,其沿著Y方向延伸,並暴露出第一區R1的基底100的頂面。也就是說,開口14分隔相鄰兩個導體層118a,使得導體層118a位於第二區R2的基底100上。如圖3B所示,導體層118a可具有底部寬度W1與頂部寬度W2。在一實施例中,底部寬度W1可大於或等於頂部寬度W2。導體層118a至少覆蓋第二區R1的基底100(或主動區AA)的頂面。Referring to FIG. 3A and FIG. 3B simultaneously, a portion of the hard mask layer HM and a portion of the conductor material 118 are removed by using the photoresist pattern 126 as a mask to form a plurality of openings 14 in the remaining yttrium oxide layer 120a and the conductor layer 118a. . The opening 14 may be a strip-shaped opening that extends in the Y direction and exposes the top surface of the substrate 100 of the first region R1. That is, the opening 14 separates the adjacent two conductor layers 118a such that the conductor layer 118a is located on the substrate 100 of the second region R2. As shown in FIG. 3B, the conductor layer 118a may have a bottom width W1 and a top width W2. In an embodiment, the bottom width W1 may be greater than or equal to the top width W2. The conductor layer 118a covers at least the top surface of the substrate 100 (or active region AA) of the second region R1.

請同時參照圖3B與圖3C,在基底100上形成第一介電材料128。第一介電材料128填入開口14中並覆蓋剩餘的氧化矽層120a的頂面120T。在一實施例中,第一介電材料128可以是氮化矽。Referring to FIG. 3B and FIG. 3C simultaneously, a first dielectric material 128 is formed on the substrate 100. The first dielectric material 128 fills the opening 14 and covers the top surface 120T of the remaining ruthenium oxide layer 120a. In an embodiment, the first dielectric material 128 can be tantalum nitride.

請同時參照圖3C與圖3D,進行平坦化製程,移除部分第一介電材料128,以於第一區R1的基底上形成第一介電層128a。如圖3D所示,第一介電層128a的頂面128T與氧化矽層120a的頂面120T實質上共平面。在一實施例中,所述平坦化製程可以是化學機械研磨(CMP)製程或是回蝕刻(Etching back)製程。Referring to FIG. 3C and FIG. 3D simultaneously, a planarization process is performed to remove a portion of the first dielectric material 128 to form a first dielectric layer 128a on the substrate of the first region R1. As shown in FIG. 3D, the top surface 128T of the first dielectric layer 128a is substantially coplanar with the top surface 120T of the yttrium oxide layer 120a. In an embodiment, the planarization process may be a chemical mechanical polishing (CMP) process or an Etching back process.

請同時參照圖3D與圖3E,移除氧化矽層120a。如圖3E所示,導體層118a的頂面118T低於第一介電層128a的頂面128T。在一實施例中,導體層118a的頂面118T與第一介電層128a的頂面128T之間具有高度差H,所述高度差H可介於20 nm至150 nm之間。Referring to FIG. 3D and FIG. 3E simultaneously, the ruthenium oxide layer 120a is removed. As shown in FIG. 3E, the top surface 118T of the conductor layer 118a is lower than the top surface 128T of the first dielectric layer 128a. In an embodiment, there is a height difference H between the top surface 118T of the conductor layer 118a and the top surface 128T of the first dielectric layer 128a, and the height difference H may be between 20 nm and 150 nm.

請同時參照圖3E與圖4,於基底100上形成介電層130。介電層130共形地形成在導體層118a與第一介電層128a上。由於導體層118a的頂面118T與第一介電層128a的頂面128T之間具有高度差H,因此,介電層130的頂面可例如是一連續凹凸結構。位於第一介電層128a上的介電層130為凸部;而位於導體層118a上的介電層130為凹部。如圖4所示,第二區R2的基底100上的介電層130上具有凹部開口16,凹部開口16對應基底100中的絕緣結構101。在一實施例中,介電層130的材料可以是氮化矽。Referring to FIG. 3E and FIG. 4 simultaneously, a dielectric layer 130 is formed on the substrate 100. The dielectric layer 130 is conformally formed on the conductor layer 118a and the first dielectric layer 128a. Since the top surface 118T of the conductor layer 118a and the top surface 128T of the first dielectric layer 128a have a height difference H, the top surface of the dielectric layer 130 can be, for example, a continuous relief structure. The dielectric layer 130 on the first dielectric layer 128a is a convex portion; and the dielectric layer 130 on the conductive layer 118a is a concave portion. As shown in FIG. 4, the dielectric layer 130 on the substrate 100 of the second region R2 has a recess opening 16 corresponding to the insulating structure 101 in the substrate 100. In an embodiment, the material of the dielectric layer 130 may be tantalum nitride.

請同時參照圖4與圖5A,進行蝕刻製程,移除部分介電層130與部分導體層118a,以於第二區R2的導體柱118b與介電層130a中形成開口18。開口18暴露第二區R2的絕緣結構101的表面。另外,在進行上述蝕刻製程時,亦包括移除第一區R1的介電層130,以暴露第一介電層128a的頂面。另一方面來看,開口18將一個導體層118a分隔成兩個導體柱118b。在一實施例中,由於開口18不需要利用微影製程便可對準第二區R2的絕緣結構101,因此,此開口18可視為自對準開口。Referring to FIG. 4 and FIG. 5A simultaneously, an etching process is performed to remove a portion of the dielectric layer 130 and a portion of the conductor layer 118a to form an opening 18 in the conductor post 118b of the second region R2 and the dielectric layer 130a. The opening 18 exposes the surface of the insulating structure 101 of the second region R2. In addition, when performing the above etching process, the dielectric layer 130 of the first region R1 is also removed to expose the top surface of the first dielectric layer 128a. On the other hand, the opening 18 divides one conductor layer 118a into two conductor posts 118b. In one embodiment, the opening 18 can be considered a self-aligned opening because the opening 18 does not require alignment with the insulating structure 101 of the second region R2 using a lithography process.

請同時參照圖5A與圖5B,在基底100上形成第二介電材料132。第二介電材料132填入開口18中並覆蓋剩餘的介電層130a的頂面。在一實施例中,第二介電材料132可以是氮化矽。換言之,第一介電材料128與第二介電材料132相同。Referring to FIG. 5A and FIG. 5B simultaneously, a second dielectric material 132 is formed on the substrate 100. A second dielectric material 132 fills the opening 18 and covers the top surface of the remaining dielectric layer 130a. In an embodiment, the second dielectric material 132 can be tantalum nitride. In other words, the first dielectric material 128 is the same as the second dielectric material 132.

請同時參照圖5B與圖5C,進行平坦化製程,移除部分第二介電材料132與剩餘的介電層130a,以暴露出導體柱118b的頂面。在一實施例中,所述平坦化製程可以是CMP製程或是回蝕刻製程。之後,進行蝕刻製程,移除部分導體柱118b,以形成開口20於導體柱118c1上並形成開口22於導體柱118c2上。在一實施例中,所述蝕刻製程可以是濕式蝕刻或乾式蝕刻製程。在一實施例中,如圖5C所示,開口20的底面與開口22的底面為共平面。Referring to FIG. 5B and FIG. 5C simultaneously, a planarization process is performed to remove a portion of the second dielectric material 132 and the remaining dielectric layer 130a to expose the top surface of the conductor post 118b. In an embodiment, the planarization process may be a CMP process or an etch back process. Thereafter, an etching process is performed to remove a portion of the conductor post 118b to form an opening 20 on the conductor post 118c1 and form an opening 22 on the conductor post 118c2. In an embodiment, the etching process may be a wet etching or a dry etching process. In one embodiment, as shown in FIG. 5C, the bottom surface of the opening 20 is coplanar with the bottom surface of the opening 22.

請同時參照圖5C與圖6,於導體柱118c1、導體柱118c2上分別形成矽化金屬層134與金屬層136。在一實施例中,矽化金屬層134可例如是TiSi、CoSi、NiSi或其組合。在一實施例中,金屬層136可例如是W。如圖6所示,導體柱118c1、矽化金屬層134以及金屬層136的複合結構可視為電容器接觸窗CC1;而導體柱118c2、矽化金屬層134以及金屬層136的複合結構可視為電容器接觸窗CC2。電容器接觸窗CC1配置在主動區AA的一端,以電性連接主動區AA與後續形成的電容器142(如圖7所示)。電容器接觸窗CC2配置在主動區AA的另一端,以電性連接主動區AA與後續形成的電容器142(如圖7所示)。Referring to FIG. 5C and FIG. 6 simultaneously, a deuterated metal layer 134 and a metal layer 136 are formed on the conductor post 118c1 and the conductor post 118c2, respectively. In an embodiment, the deuterated metal layer 134 can be, for example, TiSi, CoSi, NiSi, or a combination thereof. In an embodiment, the metal layer 136 can be, for example, W. As shown in FIG. 6, the composite structure of the conductor post 118c1, the deuterated metal layer 134, and the metal layer 136 can be regarded as the capacitor contact window CC1; and the composite structure of the conductor post 118c2, the deuterated metal layer 134, and the metal layer 136 can be regarded as the capacitor contact window CC2. . The capacitor contact window CC1 is disposed at one end of the active area AA to electrically connect the active area AA with the subsequently formed capacitor 142 (shown in FIG. 7). The capacitor contact window CC2 is disposed at the other end of the active area AA to electrically connect the active area AA with the subsequently formed capacitor 142 (shown in FIG. 7).

在一實施例中,如圖6所示,電容器接觸窗CC1不僅覆蓋主動區AA的表面,還覆蓋部分埋入式字元線202a的頂面。具體來說,電容器接觸窗CC1具有底部寬度W3與頂部寬度W4,其中底部寬度W3大於或等於頂部寬度W4。也就是說,電容器接觸窗CC1可以是梯形結構或矩形結構。在一實施例中,電容器接觸窗CC1的底部寬度W3介於10 nm至80 nm之間。換言之,本實施例可最大化電容器接觸窗CC1與主動區AA之間的接觸面積,使得電容器接觸窗CC1與主動區AA之間的阻值降低,藉此增加動態隨機存取記憶體的讀取速度,進而提升產品效率與可靠度。同樣地,電容器接觸窗CC2也具有相同功效,於此便不再贅述。In one embodiment, as shown in FIG. 6, the capacitor contact window CC1 covers not only the surface of the active area AA but also the top surface of the partially buried word line 202a. Specifically, the capacitor contact window CC1 has a bottom width W3 and a top width W4, wherein the bottom width W3 is greater than or equal to the top width W4. That is, the capacitor contact window CC1 may be a trapezoidal structure or a rectangular structure. In an embodiment, the bottom width W3 of the capacitor contact window CC1 is between 10 nm and 80 nm. In other words, the present embodiment can maximize the contact area between the capacitor contact window CC1 and the active area AA, so that the resistance between the capacitor contact window CC1 and the active area AA is lowered, thereby increasing the reading of the dynamic random access memory. Speed, which in turn increases product efficiency and reliability. Similarly, the capacitor contact window CC2 also has the same effect, and will not be described again here.

另外,在此情況下,第二介電層132a分別對應第二區R2的基底100中的隔離結構101,以電性隔絕相鄰兩個導體柱118c1、118c2(或電容器接觸窗CC1、CC2)。In addition, in this case, the second dielectric layer 132a corresponds to the isolation structure 101 in the substrate 100 of the second region R2, respectively, to electrically isolate the adjacent two conductor posts 118c1, 118c2 (or capacitor contact windows CC1, CC2). .

請同時參照圖6與圖7,先在基底100上形成介電層140。之後,在介電層140中形成多個電容器開口24,並將多個電容器142分別形成在電容器開口24中。電容器142藉由電容器接觸窗CC1、CC2分別與主動區AA電性連接。具體來說,各電容器142包括下電極142a、上電極142c及介電層142b。介電層142b位於下電極142a與上電極142c之間。下電極142a分別與電容器接觸窗CC1、CC2電性連接。在一實施例中,介電層140的材料可例如是氧化矽。下電極142a與上電極142c的材料例如是氮化鈦、氮化鉭、鎢、鈦鎢、鋁、銅或金屬矽化物。介電層142b可包括高介電常數材料層(即介電常數高於4的介電材料),其材料例如是下述元素的氧化物,如:鉿、鋯、鋁、鈦、鑭、釔、釓或鉭,又或是氮化鋁,或是上述任意組合。Referring to FIG. 6 and FIG. 7 simultaneously, a dielectric layer 140 is first formed on the substrate 100. Thereafter, a plurality of capacitor openings 24 are formed in the dielectric layer 140, and a plurality of capacitors 142 are respectively formed in the capacitor openings 24. The capacitor 142 is electrically connected to the active area AA via the capacitor contact windows CC1 and CC2, respectively. Specifically, each capacitor 142 includes a lower electrode 142a, an upper electrode 142c, and a dielectric layer 142b. The dielectric layer 142b is located between the lower electrode 142a and the upper electrode 142c. The lower electrodes 142a are electrically connected to the capacitor contact windows CC1 and CC2, respectively. In an embodiment, the material of the dielectric layer 140 may be, for example, hafnium oxide. The material of the lower electrode 142a and the upper electrode 142c is, for example, titanium nitride, tantalum nitride, tungsten, titanium tungsten, aluminum, copper or metal telluride. The dielectric layer 142b may include a high dielectric constant material layer (ie, a dielectric material having a dielectric constant higher than 4), and the material thereof is, for example, an oxide of the following elements, such as germanium, zirconium, aluminum, titanium, germanium, germanium. , 釓 or 钽, or aluminum nitride, or any combination of the above.

值得注意的是,由於第一介電層128a與第二介電層132a的材料皆為氮化矽,因此,在介電層140中形成電容器開口24時,第一介電層128a與第二介電層132a可用以當作蝕刻停止層。所述蝕刻停止層可避免在形成電容器開口24時的過度蝕刻,而導致相鄰兩個電容器接觸窗CC1、CC2電性連接所造成的短路問題。另一方面,即使電容器開口24的形成過程中有重疊偏移(overlay shift)或是對準失誤(misalignment),由氮化矽所構成的第一介電層128a與第二介電層132a亦可防止電容器開口24形成的過度蝕刻,以防止相鄰兩個電容器接觸窗CC1、CC2短路問題。因此,本實施例之電容器接觸窗CC1、CC2可保持柱狀結構,而不會在電容器接觸窗CC1、CC2的底部產生尖角。It should be noted that, since the materials of the first dielectric layer 128a and the second dielectric layer 132a are both tantalum nitride, when the capacitor opening 24 is formed in the dielectric layer 140, the first dielectric layer 128a and the second layer Dielectric layer 132a can be used as an etch stop layer. The etch stop layer can avoid over-etching when forming the capacitor opening 24, resulting in a short circuit problem caused by the electrical connection of the adjacent two capacitor contact windows CC1, CC2. On the other hand, even if there is overlap shift or misalignment during the formation of the capacitor opening 24, the first dielectric layer 128a and the second dielectric layer 132a composed of tantalum nitride are also Over-etching of the capacitor opening 24 can be prevented to prevent short-circuit problems between adjacent two capacitor contact windows CC1, CC2. Therefore, the capacitor contact windows CC1, CC2 of the present embodiment can maintain the columnar structure without generating sharp corners at the bottom of the capacitor contact windows CC1, CC2.

綜上所述,本發明藉由先形成導體層,再於導體層中形成第一介電層與第二介電層,以將導體層分隔成多個導體柱(或電容器接觸窗)。因此,本發明可簡化電容器接觸窗的製造方法並使得電容器接觸窗維持為柱狀結構。而且所形成的電容器接觸窗的底部寬度可大於或等於電容器接觸窗的頂部寬度,其可降低電容器接觸窗與主動區之間的阻值,藉此增加動態隨機存取記憶體的讀取速度,進而提升產品效率與可靠度。另外,本發明將配置於位元線結構的側壁上的間隙壁的材料置換為氧化矽,以降低相鄰位元線結構之間的寄生電容,進而提升記憶體的效能。此外,本發明將電容器接觸窗旁的介電層的材料皆置換為氮化矽,其可避免過度蝕刻而導致相鄰兩個電容器接觸窗短路的問題。In summary, the present invention divides the conductor layer into a plurality of conductor posts (or capacitor contact windows) by first forming a conductor layer and then forming a first dielectric layer and a second dielectric layer in the conductor layer. Therefore, the present invention can simplify the manufacturing method of the capacitor contact window and maintain the capacitor contact window as a columnar structure. Moreover, the bottom width of the formed capacitor contact window may be greater than or equal to the top width of the capacitor contact window, which may reduce the resistance between the capacitor contact window and the active region, thereby increasing the read speed of the dynamic random access memory. In turn, improve product efficiency and reliability. In addition, the present invention replaces the material of the spacers disposed on the sidewalls of the bit line structure with yttrium oxide to reduce the parasitic capacitance between adjacent bit line structures, thereby improving the performance of the memory. In addition, the present invention replaces the material of the dielectric layer next to the capacitor contact window with tantalum nitride, which avoids the problem of over-etching causing short-circuiting of adjacent two capacitor contact windows.

雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10、12、14、16、18、20、22、24‧‧‧開口10,12,14,16,18,20,22,24‧‧

100‧‧‧基底100‧‧‧Base

101‧‧‧隔離結構101‧‧‧Isolation structure

102‧‧‧位元線結構102‧‧‧ bit line structure

104‧‧‧氧化矽層104‧‧‧Oxide layer

106‧‧‧氮化矽層106‧‧‧layer of tantalum nitride

108‧‧‧阻障層108‧‧‧Barrier layer

110‧‧‧位元線110‧‧‧ bit line

112‧‧‧頂蓋層112‧‧‧Top cover

114‧‧‧第一間隙壁114‧‧‧First gap

116‧‧‧第二間隙壁116‧‧‧Second gap

118‧‧‧導體材料118‧‧‧Conductor materials

118a‧‧‧導體層118a‧‧‧ conductor layer

118b、118c1、118c2‧‧‧導體柱118b, 118c1, 118c2‧‧‧ conductor column

118T‧‧‧頂面118T‧‧‧ top surface

120、120a‧‧‧氧化矽層120, 120a‧‧‧ yttrium oxide layer

120T‧‧‧頂面120T‧‧‧ top surface

122‧‧‧碳層122‧‧‧ carbon layer

124‧‧‧氮氧化矽層124‧‧‧Nitrogen oxide layer

126‧‧‧光阻圖案126‧‧‧resist pattern

128‧‧‧第一介電材料128‧‧‧First dielectric material

128a‧‧‧第一介電層128a‧‧‧First dielectric layer

128T‧‧‧頂面128T‧‧‧ top surface

130、130a‧‧‧介電層130, 130a‧‧‧ dielectric layer

132‧‧‧第二介電材料132‧‧‧Second dielectric material

132a‧‧‧第二介電層132a‧‧‧Second dielectric layer

134‧‧‧矽化金屬層134‧‧‧Deuterated metal layer

136‧‧‧金屬層136‧‧‧metal layer

140‧‧‧介電層140‧‧‧Dielectric layer

142‧‧‧電容器142‧‧‧ capacitor

142a‧‧‧下電極142a‧‧‧ lower electrode

142b‧‧‧介電層142b‧‧‧ dielectric layer

142c‧‧‧上電極142c‧‧‧Upper electrode

202‧‧‧字元線組202‧‧‧ character line group

202a、202b‧‧‧埋入式字元線202a, 202b‧‧‧ Buried word line

204a、204b‧‧‧閘極204a, 204b‧‧‧ gate

206a、206b‧‧‧閘介電層206a, 206b‧‧‧ gate dielectric layer

208‧‧‧氮化矽層208‧‧‧ layer of tantalum nitride

AA‧‧‧主動區AA‧‧‧Active Area

AC1~AC3‧‧‧主動區行AC1~AC3‧‧‧Active Area

BC‧‧‧位元線接觸窗BC‧‧‧ bit line contact window

CC1、CC2‧‧‧電容器接觸窗CC1, CC2‧‧‧ capacitor contact window

H‧‧‧高度差H‧‧‧ height difference

HM‧‧‧硬罩幕層HM‧‧‧hard mask layer

L1‧‧‧長邊L1‧‧‧ long side

L2‧‧‧短邊L2‧‧‧ Short side

R1‧‧‧第一區R1‧‧‧ first district

R2‧‧‧第二區R2‧‧‧Second District

W1、W3‧‧‧底部寬度W1, W3‧‧‧ bottom width

W2、W4‧‧‧頂部寬度W2, W4‧‧‧ top width

X、Y‧‧‧方向X, Y‧‧ direction

θ‧‧‧夾角Θ‧‧‧ angle

圖1是本發明之一實施例的動態隨機存取記憶體的上視示意圖。 圖2A至圖2C是沿著圖1之A-A’線段的動態隨機存取記憶體之製造流程的剖面示意圖。 圖3A至圖3E、圖4、圖5A至圖5C以及圖6-7是沿著圖1之B-B’線段的動態隨機存取記憶體之製造流程的剖面示意圖。1 is a top plan view of a dynamic random access memory according to an embodiment of the present invention. 2A to 2C are schematic cross-sectional views showing a manufacturing flow of a dynamic random access memory along the line A-A' of Fig. 1. 3A to 3E, 4, 5A to 5C, and 6-7 are schematic cross-sectional views showing a manufacturing flow of the dynamic random access memory along the line B-B' of Fig. 1.

Claims (20)

一種動態隨機存取記憶體,包括: 多個隔離結構,位於基底中,以將所述基底分隔成多個主動區,所述主動區被配置成帶狀且排列成一陣列; 多個字元線組,沿著Y方向平行配置於所述基底中; 多個位元線結構,沿著X方向平行配置於所述基底上,且橫越所述字元線組; 多個間隙壁,沿著所述X方向平行配置於所述位元線結構的側壁上,其中所述間隙壁包括氧化矽; 多個電容器,分別配置於所述主動區的長邊的兩端點上;以及 多個電容器接觸窗,分別位於所述電容器與所述主動區之間。A dynamic random access memory, comprising: a plurality of isolation structures disposed in a substrate to divide the substrate into a plurality of active regions, the active regions being configured in a strip shape and arranged in an array; a plurality of word lines a plurality of bit line structures arranged in parallel along the X direction on the substrate and traversing the word line group; a plurality of spacers along the plurality of spacers The X direction is disposed in parallel on a sidewall of the bit line structure, wherein the spacer includes a ruthenium oxide; a plurality of capacitors respectively disposed at both ends of a long side of the active region; and a plurality of capacitors Contact windows are respectively located between the capacitor and the active region. 如申請專利範圍第1項所述的動態隨機存取記憶體,其中各所述間隙壁包括第一間隙壁與第二間隙壁,所述第一間隙壁位於所述位元線結構與所述第二間隙壁之間。The dynamic random access memory according to claim 1, wherein each of the spacers includes a first spacer and a second spacer, and the first spacer is located in the bit line structure and Between the second spacers. 如申請專利範圍第2項所述的動態隨機存取記憶體,其中所述第一間隙壁包括氮化矽,所述第二間隙壁包括氧化矽。The dynamic random access memory of claim 2, wherein the first spacer comprises tantalum nitride and the second spacer comprises hafnium oxide. 如申請專利範圍第1項所述的動態隨機存取記憶體,更包括多個介電層分別位於所述電容器接觸窗之間,其中所述介電層包括氮化矽。The dynamic random access memory according to claim 1, further comprising a plurality of dielectric layers respectively located between the capacitor contact windows, wherein the dielectric layer comprises tantalum nitride. 如申請專利範圍第1項所述的動態隨機存取記憶體,其中所述字元線組包括兩個埋入式字元線。The dynamic random access memory according to claim 1, wherein the word line group includes two buried word lines. 如申請專利範圍第5項所述的動態隨機存取記憶體,其中所述電容器接觸窗之一者覆蓋所述主動區以及所述兩個埋入式字元線之一者的部分頂面。The dynamic random access memory of claim 5, wherein one of the capacitor contact windows covers a portion of a top surface of the active region and one of the two buried word lines. 如申請專利範圍第1項所述的動態隨機存取記憶體,其中各所述電容器接觸窗為複合結構,其包括導體層、矽化金屬層以及金屬層。The dynamic random access memory according to claim 1, wherein each of the capacitor contact windows is a composite structure including a conductor layer, a deuterated metal layer, and a metal layer. 如申請專利範圍第1項所述的動態隨機存取記憶體,其中各所述電容器接觸窗具有底部寬度與頂部寬度,所述底部寬度大於或等於所述頂部寬度。The dynamic random access memory of claim 1, wherein each of the capacitor contact windows has a bottom width and a top width, the bottom width being greater than or equal to the top width. 如申請專利範圍第1項所述的動態隨機存取記憶體,其中相鄰兩行的所述主動區呈鏡像配置。The dynamic random access memory of claim 1, wherein the active areas of two adjacent rows are in a mirrored configuration. 一種動態隨機存取記憶體的製造方法,包括: 於基底中形成多個隔離結構,以將所述基底分隔成多個主動區,所述主動區被配置成帶狀且排列成一陣列; 於所述基底中形成多個字元線組,所述字元線組沿著Y方向延伸並穿過所述隔離結構與所述主動區,以將所述基底分成多個第一區與多個第二區,其中所述第一區與所述第二區沿著X方向交替排列且所述字元線組位於所述第一區中; 於所述基底上形成多個位元線結構,所述位元線結構沿著所述X方向延伸並橫跨所述字元線組; 於所述位元線結構的側壁上分別形成多個間隙壁; 於所述第二區的所述基底上形成多個導體層; 於所述第一區的所述基底上形成多個第一介電層,其中所述導體層的頂面低於所述第一介電層的頂面; 於所述導體層中分別形成多個第二介電層,各所述第二介電層將所對應的導體層分隔成兩個導體柱,其中所述第一介電層的材料與所述第二介電層的材料相同;以及 於所述導體柱上分別形成多個電容器。A method for manufacturing a dynamic random access memory, comprising: forming a plurality of isolation structures in a substrate to divide the substrate into a plurality of active regions, the active regions being arranged in a strip shape and arranged in an array; Forming a plurality of word line groups in the substrate, the word line groups extending along the Y direction and passing through the isolation structure and the active area to divide the substrate into a plurality of first areas and a plurality of a second area, wherein the first area and the second area are alternately arranged along the X direction and the word line group is located in the first area; forming a plurality of bit line structures on the substrate a bit line structure extending along the X direction and spanning the word line group; a plurality of spacers respectively formed on sidewalls of the bit line structure; on the substrate of the second area Forming a plurality of conductor layers; forming a plurality of first dielectric layers on the substrate of the first region, wherein a top surface of the conductor layer is lower than a top surface of the first dielectric layer; A plurality of second dielectric layers are respectively formed in the conductor layer, and each of the second dielectric layers has a corresponding conductor layer Dividing into two conductor pillars, wherein a material of the first dielectric layer is the same as a material of the second dielectric layer; and a plurality of capacitors are respectively formed on the conductor pillars. 如申請專利範圍第10項所述的動態隨機存取記憶體的製造方法,其中所述第一介電層的材料包括氮化矽,所述第二介電層的材料包括氮化矽。The method of manufacturing a dynamic random access memory according to claim 10, wherein the material of the first dielectric layer comprises tantalum nitride, and the material of the second dielectric layer comprises tantalum nitride. 如申請專利範圍第10項所述的動態隨機存取記憶體的製造方法,其中所述第一介電層的形成方法包括: 於所述位元線結構之間的所述基底上形成導體材料; 移除部分所述導體材料,以於所述導體材料中形成多個開口,所述開口暴露出所述第一區的所述基底的表面並將各所述導體材料分隔成兩個導體層; 將第一介電材料填入所述開口中。The method of manufacturing a dynamic random access memory according to claim 10, wherein the forming method of the first dielectric layer comprises: forming a conductor material on the substrate between the bit line structures Removing a portion of the conductor material to form a plurality of openings in the conductor material, the openings exposing a surface of the substrate of the first region and separating each of the conductor materials into two conductor layers ; filling a first dielectric material into the opening. 如申請專利範圍第10項所述的動態隨機存取記憶體的製造方法,其中所述第二介電層分別對應所述第二區的所述基底中的所述隔離結構,以電性隔絕相鄰兩個導體柱。The method for manufacturing a dynamic random access memory according to claim 10, wherein the second dielectric layer is electrically isolated from the isolation structure in the substrate of the second region. Two adjacent conductor posts. 如申請專利範圍第10項所述的動態隨機存取記憶體的製造方法,其中各所述間隙壁包括第一間隙壁與第二間隙壁,所述第一間隙壁位於所述位元線結構與所述第二間隙壁之間。The method of manufacturing a dynamic random access memory according to claim 10, wherein each of the spacers includes a first spacer and a second spacer, and the first spacer is located in the bit line structure Between the second spacer and the second spacer. 如申請專利範圍第14項所述的動態隨機存取記憶體的製造方法,其中所述第一間隙壁包括氮化矽,所述第二間隙壁包括氧化矽。The method of manufacturing a dynamic random access memory according to claim 14, wherein the first spacer includes tantalum nitride, and the second spacer includes hafnium oxide. 如申請專利範圍第10項所述的動態隨機存取記憶體的製造方法,其中所述字元線組包括兩個埋入式字元線。The method of manufacturing a dynamic random access memory according to claim 10, wherein the word line group includes two buried word lines. 如申請專利範圍第16項所述的動態隨機存取記憶體的製造方法,其中所述導體柱為電容器接觸窗,其覆蓋所述主動區以及所述兩個埋入式字元線之一者的部分頂面。The method of manufacturing a dynamic random access memory according to claim 16, wherein the conductor post is a capacitor contact window covering the active area and one of the two buried word lines. Part of the top. 如申請專利範圍第17項所述的動態隨機存取記憶體的製造方法,其中各所述電容器接觸窗具有底部寬度與頂部寬度,所述底部寬度大於或等於所述頂部寬度。The method of manufacturing a dynamic random access memory according to claim 17, wherein each of the capacitor contact windows has a bottom width and a top width, and the bottom width is greater than or equal to the top width. 如申請專利範圍第17項所述的動態隨機存取記憶體的製造方法,其中各所述電容器接觸窗為複合結構,其包括導體層、矽化金屬層以及金屬層。The method of manufacturing a dynamic random access memory according to claim 17, wherein each of the capacitor contact windows is a composite structure including a conductor layer, a deuterated metal layer, and a metal layer. 如申請專利範圍第10項所述的動態隨機存取記憶體的製造方法,其中相鄰兩行的所述主動區呈鏡像配置。The method for manufacturing a dynamic random access memory according to claim 10, wherein the active areas of two adjacent rows are in a mirror image configuration.
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US11107785B2 (en) 2019-09-25 2021-08-31 Nanya Technology Corporation Semiconductor device with a plurality of landing pads and method for fabricating the same

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