CN113314540A - Preparation method of three-dimensional memory and three-dimensional memory - Google Patents

Preparation method of three-dimensional memory and three-dimensional memory Download PDF

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CN113314540A
CN113314540A CN202110583956.9A CN202110583956A CN113314540A CN 113314540 A CN113314540 A CN 113314540A CN 202110583956 A CN202110583956 A CN 202110583956A CN 113314540 A CN113314540 A CN 113314540A
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layer
epitaxial layer
replaced
stacked structure
substrate
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刘小欣
薛磊
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

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Abstract

The application provides a preparation method of a three-dimensional memory and the three-dimensional memory, wherein the preparation method comprises the following steps: providing the substrate; sequentially forming a layer to be replaced and the stacked structure on the substrate, wherein the stacked structure comprises an insulating layer and a sacrificial layer; etching the stacked structure to form the gate isolation groove, wherein the gate isolation groove exposes the layer to be replaced; replacing the layer to be replaced with the epitaxial layer to form a semiconductor structure; and carrying out first doping on the epitaxial layer through the grid separation groove to form a doped epitaxial layer. The preparation method of the three-dimensional memory solves the problem that the electrical property of the bottom selection grid is influenced by the epitaxial structure which grows transversely, so that the preparation yield of the three-dimensional memory is reduced.

Description

Preparation method of three-dimensional memory and three-dimensional memory
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a three-dimensional memory and a three-dimensional memory.
Background
The three-dimensional memory is a memory which realizes the storage and the transmission of data in a three-dimensional space and greatly improves the storage capacity of the storage device. The existing epitaxial structure of the three-dimensional memory adopts a transverse growth mode, so that related problems caused by subsequent processes are well avoided, but the transverse growth epitaxial structure is limited by the existing process method, the electrical property of a bottom selection grid can be influenced, and the preparation yield of the three-dimensional memory is reduced.
Disclosure of Invention
The application provides a preparation method of a three-dimensional memory and the three-dimensional memory, and solves the problem that the electrical property of a bottom selection grid is influenced by a laterally grown epitaxial structure, so that the preparation yield of the three-dimensional memory is reduced.
The application provides a preparation method of a three-dimensional memory, which comprises the following steps:
providing the substrate;
sequentially forming a layer to be replaced and the stacked structure on the substrate, wherein the stacked structure comprises an insulating layer and a sacrificial layer;
etching the stacked structure to form the gate isolation groove, wherein the gate isolation groove exposes the layer to be replaced;
replacing the layer to be replaced with the epitaxial layer to form a semiconductor structure;
and carrying out first doping on the epitaxial layer through the grid separation groove to form a doped epitaxial layer.
Wherein, in the steps of "forming the layer to be replaced and the stacked structure on the substrate in sequence" and "etching the stacked structure to form the gate spacer grooves, the gate spacer grooves are exposed between the layers to be replaced", the preparation method comprises:
etching the stacked structure to form a channel hole, the channel hole exposing the substrate;
a NAND string is formed in the channel hole.
Wherein the NAND string comprises a conductive structure and a peripheral wall provided at the periphery of the conductive structure, and the replacing the layer to be replaced with the epitaxial layer comprises:
removing the layer to be replaced to form a gap and expose the peripheral wall of the NAND string;
forming the epitaxial layer in the void.
Wherein, before the step of forming the epitaxial layer in the gap, the preparation method comprises the following steps:
and removing the part of the peripheral wall on the layer to be replaced to expose part of the conductive structure so as to enable the conductive structure to be in contact with the epitaxial layer in the subsequent process.
Wherein, after the step of forming the epitaxial layer in the gap, the preparation method comprises the following steps:
replacing the sacrificial layer with a gate layer.
Wherein the "first doping the epitaxial layer through the gate spacer to form a doped epitaxial layer" comprises:
carrying out first doping on the epitaxial layer through the grid separation groove;
and heating the semiconductor structure to enable the epitaxial layer to form the doped epitaxial layer.
Wherein, after the "first doping the epitaxial layer through the gate spacer to form a doped epitaxial layer", the preparation method comprises:
forming an array common source in the gate spacer.
Wherein the "forming an array common source in the gate spacer trench" comprises:
carrying out second doping on the bottom of the grid separation groove;
an electrical conductor is formed in the gate spacer.
The application further provides a three-dimensional memory, the three-dimensional memory includes a substrate, a doped epitaxial layer and a stacked structure, the doped epitaxial layer and the stacked structure are sequentially formed on the substrate, the stacked structure is provided with a grid spacer groove, and the grid spacer groove is exposed out of the doped epitaxial layer.
According to the preparation method of the three-dimensional memory, the epitaxial layer is subjected to the first doping through the grid spacer groove to form the doped epitaxial layer, so that the doping concentration of the epitaxial layer is ensured, the influence of the epitaxial layer on the electrical property of the bottom selection grid is effectively avoided, and the preparation yield of the three-dimensional memory is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic flow chart of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure.
Fig. 2 is a schematic process structure diagram of the preparation method provided in fig. 1.
FIG. 3 is a schematic flow diagram of a specific embodiment of the preparation method provided in FIG. 1.
FIG. 4 is a schematic flow diagram of a specific embodiment of the preparation method provided in FIG. 1.
Fig. 5-9 are schematic process structures of the preparation method provided in fig. 1.
Fig. 10 is a schematic flowchart of another method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure.
Fig. 11-12 are schematic flow diagrams of a detailed process of the preparation method provided in fig. 10.
Fig. 13-14 are schematic process structures of the manufacturing method provided in fig. 12.
Fig. 15 is a schematic structural diagram of a three-dimensional memory according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The epitaxial structure growing on the side edge of the channel hole is a transverse epitaxial structure growing mode, and is different from the epitaxial structure growing in the channel hole directly and longitudinally, the epitaxial structure growing on the side edge of the channel hole can well avoid a series of problems caused by damage of the epitaxial structure and the difference of growing density and height due to process conditions during epitaxial growth of the epitaxial structure, so that the three-dimensional memory can be used as a stacked structure with more layers, and more memory units are provided. However, the doping of the existing epitaxial structure grown transversely is diffused through the bottom silicon substrate, and the doping concentration and gradient of the epitaxial structure cannot meet the requirements, so that the electrical performance of the adjacent bottom selection gate can be affected, for example, the problems of bottom gate leakage and bottom selection gate voltage difference at different positions due to the short channel effect occur, and the electrical performance and the preparation yield of the three-dimensional memory are seriously affected.
In view of this, the present application provides a method for manufacturing a three-dimensional memory. The method comprises the steps of firstly providing a semiconductor structure, wherein the semiconductor structure comprises a substrate, an epitaxial layer arranged on the substrate and a stacked structure arranged on the epitaxial layer, the semiconductor structure is also provided with a grid separation groove penetrating through the stacked structure, and the grid separation groove exposes the epitaxial layer. The epitaxial layer is then first doped through the gate spacer to form a doped epitaxial layer. The method solves the problems of doping concentration and gradient of the epitaxial layer, and effectively improves the electrical property and the preparation yield of the three-dimensional memory.
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure. As shown in fig. 1, the method for manufacturing the three-dimensional memory includes the following steps S110 to S120.
S110: referring to fig. 4, a semiconductor structure 10 is provided, wherein the semiconductor structure 10 includes a substrate 11, an epitaxial layer 14 disposed on the substrate 11, and a stacked structure 13 disposed on the epitaxial layer 14, the semiconductor structure 10 further has a gate separation groove 15 penetrating through the stacked structure 13, and the gate separation groove 15 exposes the epitaxial layer 14.
In one possible example, referring to fig. 3, the step S110 of providing the semiconductor structure 10 may include the following steps S111 to S114.
S111: the substrate 11 is provided.
Specifically, referring to fig. 2, the material of the substrate 11 is, for example, silicon, in the present embodiment, the substrate 11 includes a lower substrate 111 and an upper substrate 112, the upper substrate 112 is a portion of the substrate 11 after ion implantation, in other words, the upper substrate 112 forms a well region by doping, for example, P-type doping. Of course, the substrate 11 may also be other Silicon-containing substrates 11, such as Silicon-on-insulator (SOI), Silicon germanium (SiGe), Silicon carbide (SiC), and the like.
S112: a layer to be replaced 12 and the stacked structure 13 are sequentially formed on the substrate 11.
Specifically, referring to fig. 2, a layer to be replaced 12 is first formed on an upper substrate 112, and then an insulating layer 131/sacrificial layer 132 overlapping stack structure 13 is formed on the layer to be replaced 12. In this embodiment, the layer to be replaced 12 and the sacrificial layer 132 are formed of the same material, for example, silicon nitride, and the insulating layer 131 is formed of, for example, silicon oxide. The layer to be replaced 12, the insulating layer 131 and the sacrificial layer 132 may be formed by chemical vapor deposition, atomic layer deposition or other suitable deposition methods. Of course, in other embodiments, the layer to be replaced 12 and the sacrificial layer 132 may also be made of amorphous silicon, polysilicon, or aluminum oxide, and the insulating layer 131 may also be made of silicon oxynitride.
S113: the stacked structure 13 is etched to form the gate spacer 15, and the gate spacer 15 exposes the layer to be replaced 12.
Specifically, referring to fig. 2, prior to etching the stacked structure 13 to form the gate spacer 15, the stacked structure 13 is etched to form a channel hole 16, the channel hole 16 exposes the substrate 11, and then a NAND string 17 is formed in the channel hole 16. In this embodiment, the NAND string 17 includes a conductive structure 171 and a peripheral wall 172 disposed on the periphery of the conductive structure 171, the peripheral wall 172 is formed by sequentially forming a barrier material layer 1721, a memory material layer 1722 and an oxide material layer 1723 on the wall of the trench hole 16, and then the conductive structure 171 is filled in the trench hole 16. Wherein an exemplary material of the barrier material layer 1721 and the oxide material layer 1723 is silicon oxide, and an exemplary material of the memory material layer 1722 is silicon nitride, which can be deposited by CVD, ALD or other suitable deposition methods, such that the peripheral wall 172 forms a stacked structure of silicon oxide-silicon nitride-silicon oxide (ONO) three layers.
Then, the stacked structure 13 is etched to form the gate separation groove 15, and the gate separation groove 15 penetrates through the stacked structure 13 and exposes the layer to be replaced 12.
S114: replacing the layer to be replaced 12 with the epitaxial layer 14.
In a possible example, referring to fig. 4, the step S114 of replacing the layer to be replaced 12 with the epitaxial layer 14 may include the following steps S1141 to S1142.
S1141: the layer to be changed 12 is removed to form a void a exposing the peripheral wall 172 of the NAND string 17.
Specifically, referring to fig. 5, an etching solution is poured into the gate spacer 15 to remove the layer to be replaced 12, so as to form a gap a between the stacked structure 13 and the upper substrate 112, and the peripheral wall 172 of the NAND string 17 and the upper substrate 112 are exposed by the gap a. Then, removing the portion of the peripheral wall 172 in the layer to be replaced 12, that is, removing the portion of the peripheral wall 172 of the NAND string 17 through the gap a, includes removing a portion of the barrier material layer 1721, the memory material layer 1722 and the oxide material layer 1723, and exposing a portion of the conductive structure 171, so that the conductive structure 171 is in contact with the epitaxial layer 14 in the subsequent process. Portions of the barrier material layer 1721, the memory material layer 1722, and the oxide material layer 1723 may be sequentially removed by a plurality of wet etches.
S1142: the epitaxial layer 14 is formed in the void a.
Specifically, referring to fig. 6, the epitaxial layer 14 is formed by a growth process, and the epitaxial layer 14 is recessed at the gate spacer 15. Epitaxial layer 14 is formed, for example, by Selective Epitaxial Growth (SEG) from upper substrate 112 and the exposed portions of NAND strings 17. Of course, epitaxial layer 14 may also be formed using deposition.
Referring to fig. 7, after the epitaxial layer 14 is formed, the sacrificial layer 132 is replaced by a gate layer 133.
S120: the epitaxial layer 14 is first doped through the gate spacer 15 to form a doped epitaxial layer 18.
In particular, referring to fig. 8-9, before the first doping of the epitaxial layer 14, a protection layer 19 is formed on the walls of the gate spacer 15 to prevent the doping process from doping the stacked structure 13. The epitaxial layer 14 is then first doped, for example P-doped, through the gate spacer 15. Since the epitaxial layer 14 is exposed out of the gate spacer 15, the doping concentration and gradient of the epitaxial layer 14 can be better controlled by performing the first doping on the epitaxial layer 14 through the gate spacer 15, and a better doping effect is achieved. Finally, the semiconductor structure 10 is heated to form the epitaxial layer 14 into the doped epitaxial layer 18.
According to the preparation method of the three-dimensional memory, the epitaxial layer 14 is subjected to first doping through the grid spacer 15 to form the doped epitaxial layer 18, so that the doping concentration of the epitaxial layer 14 is ensured, the problem that the electrical performance is influenced by a short channel effect generated by a bottom selection grid due to insufficient doping concentration and gradient of the epitaxial layer 14 is effectively avoided, and the electrical performance and the preparation yield of the three-dimensional memory are improved.
Referring to fig. 10, fig. 10 is a schematic flow chart illustrating a method for fabricating a three-dimensional memory according to an embodiment of the present disclosure. As shown in fig. 10, the method for manufacturing the three-dimensional memory includes the following steps S210 to S230.
S210: referring to fig. 4, a semiconductor structure 10 is provided, wherein the semiconductor structure 10 includes a substrate 11, an epitaxial layer 14 disposed on the substrate 11, and a stacked structure 13 disposed on the epitaxial layer 14, the semiconductor structure 10 further has a gate separation groove 15 penetrating through the stacked structure 13, and the gate separation groove 15 exposes the epitaxial layer 14.
In one possible example, referring to fig. 11, the step S210 of providing the semiconductor structure 10 may include the following steps S211 to S214.
S211: the substrate 11 is provided.
Specifically, referring to fig. 2, the material of the substrate 11 is, for example, silicon, in the present embodiment, the substrate 11 includes an upper substrate 112 and a lower substrate 111, the upper substrate 112 is a portion of the substrate 11 after ion implantation, in other words, the upper substrate 112 forms a well region by doping, for example, P-type doping. Of course, the substrate 11 may also be other Silicon-containing substrates 11, such as Silicon-on-insulator (SOI), Silicon germanium (SiGe), Silicon carbide (SiC), and the like.
S212: a layer to be replaced 12 and the stacked structure 13 are sequentially formed on the substrate 11.
Specifically, referring to fig. 2, a layer to be replaced 12 is first formed on an upper substrate 112, and then an insulating layer 131/sacrificial layer 132 overlapping stack structure 13 is formed on the layer to be replaced 12. In this embodiment, the layer to be replaced 12 and the sacrifice layer 132 are formed of the same material, for example, silicon nitride, and the insulating layer 131 is formed of, for example, silicon oxide. The layer to be replaced 12, the insulating layer 131 and the sacrificial layer 132 may be formed by chemical vapor deposition, atomic layer deposition or other suitable deposition methods. Of course, in other embodiments, the layer to be replaced 12 and the sacrificial layer 132 may also be made of amorphous silicon, polysilicon, or aluminum oxide, and the insulating layer 131 may also be made of silicon oxynitride.
S213: the stacked structure 13 is etched to form the gate spacer 15, and the gate spacer 15 exposes the layer to be replaced 12.
Specifically, referring to fig. 2, prior to etching the stacked structure 13 to form the gate spacer 15, the stacked structure 13 is etched to form a channel hole 16, the channel hole 16 exposes the substrate 11, and then a NAND string 17 is formed in the channel hole 16. In this embodiment, the NAND string 17 includes a conductive structure 171 and a peripheral wall 172 disposed on the periphery of the conductive structure 171, the peripheral wall 172 is formed by sequentially forming a barrier material layer 1721, a memory material layer 1722 and an oxide material layer 1723 on the wall of the trench hole 16, and then the conductive structure 171 is filled in the trench hole 16. Wherein an exemplary material of the barrier material layer 1721 and the oxide material layer 1723 is silicon oxide, and an exemplary material of the memory material layer 1722 is silicon nitride, which can be deposited by CVD, ALD or other suitable deposition methods, such that the peripheral wall 172 forms a stacked structure of silicon oxide-silicon nitride-silicon oxide (ONO) three layers.
Then, the stacked structure 13 is etched to form the gate separation groove 15, and the gate separation groove 15 penetrates through the stacked structure 13 and exposes the layer to be replaced 12.
S214: replacing the layer to be replaced 12 with the epitaxial layer 14.
In a possible example, referring to fig. 12, the step S214 of replacing the layer to be replaced 12 with the epitaxial layer 14 may include the following steps S2141 to S2142.
S2141: the layer to be changed 12 is removed to form a void a exposing the peripheral wall 172 of the NAND string 17.
Specifically, referring to fig. 5, an etching solution is poured into the gate spacer 15 to remove the layer to be replaced 12, so as to form a gap a between the stacked structure 13 and the upper substrate 112, and the peripheral wall 172 of the NAND string 17 and the upper substrate 112 are exposed by the gap a. Then, removing the portion of the peripheral wall 172 in the layer to be replaced 12, that is, removing the portion of the peripheral wall 172 of the NAND string 17 through the gap a, includes removing a portion of the barrier material layer 1721, the memory material layer 1722 and the oxide material layer 1723, and exposing a portion of the conductive structure 171, so that the conductive structure 171 is in contact with the epitaxial layer 14 in the subsequent process. The barrier material layer 1721, the memory material layer 1722, and the oxide material layer 1723 may be sequentially removed by a plurality of wet etches.
S2142: the epitaxial layer 14 is formed in the void a.
Specifically, referring to fig. 6, the epitaxial layer 14 is formed by a growth process, and the epitaxial layer 14 is recessed at the gate spacer 15. Epitaxial layer 14 is formed, for example, by Selective Epitaxial Growth (SEG) from upper substrate 112 and the exposed portions of NAND strings 17. Of course, epitaxial layer 14 may also be formed using deposition.
Referring to fig. 7, after the epitaxial layer 14 is formed, the sacrificial layer 132 is replaced by a gate layer 133.
S220: the epitaxial layer 14 is first doped through the gate spacer 15 to form a doped epitaxial layer 18.
In particular, in fig. 8-9, before the first doping of the epitaxial layer 14, a protection layer 19 is formed on the walls of the gate spacer 15 to avoid doping the stacked structure 13 by the doping process. The epitaxial layer 14 is then first doped, for example P-doped, through the gate spacer 15. Since the epitaxial layer 14 is exposed out of the gate spacer 15, the doping concentration and gradient of the epitaxial layer 14 can be better controlled by performing the first doping on the epitaxial layer 14 through the gate spacer 15, and a better doping effect is achieved. Finally, the semiconductor structure 10 is heated to form the epitaxial layer 14 into the doped epitaxial layer 18.
S230: an array common source 20 is formed in the gate spacer 15.
Specifically, referring to fig. 13 and 14, the bottom of the gate spacer 15 is first doped, for example, N-type doped. Specifically, the doped epitaxial layer 18 is doped N-type in the recess corresponding to the bottom of the gate spacer 15 to form a doped structure 21. The doped structure 21 is wrapped by the doped epitaxial layer 18, so that the voltage between the doped structure 21 and the doped epitaxial layer 18 is effectively improved, the surface voltage stress is reduced, and the electrical performance and the preparation yield of the product are improved. The protective layer 19 is then removed and a conductor 22 is formed in the gate spacer 15, thereby forming a three-dimensional memory. The conductive body 22 includes a barrier layer 221 and a conductive material 222 disposed in the barrier layer 221, and the barrier layer 221 is first formed on the walls of the gate spacer 15, and then the gate spacer 15 is filled with the conductive material 222, thereby forming a three-dimensional memory.
According to the preparation method of the three-dimensional memory, the epitaxial layer 14 is subjected to first doping through the grid spacer 15 to form the doped epitaxial layer 18, so that the doping concentration of the epitaxial layer 14 is ensured, the problem that the electrical performance is influenced by a short channel effect generated by a bottom selection grid due to insufficient doping concentration and gradient of the epitaxial layer 14 is effectively avoided, and the electrical performance and the preparation yield of the three-dimensional memory are improved.
Referring to fig. 15, fig. 15 is a schematic structural diagram of a three-dimensional memory 100 according to an embodiment of the present disclosure. The three-dimensional memory 100 comprises a substrate 11, a doped epitaxial layer 18 and a stacked structure 13, wherein the doped epitaxial layer 18 and the stacked structure 13 are sequentially formed on the substrate 11, the stacked structure 13 is provided with a channel hole 16 and a gate isolation groove 15, a NAND string 17 is formed in the channel hole 16, the NAND string 17 comprises a conductive structure 171 and a peripheral wall 172 arranged on the periphery of the conductive structure 171, and the portion of the conductive structure 171 located on the doped epitaxial layer 18 is exposed out of the peripheral wall 172 and is in contact with the doped epitaxial layer 18. The gate spacer 15 exposes the doped epitaxial layer 18. In this embodiment, the doped epitaxial layer 18 is formed by P-type doping. According to the three-dimensional memory 100, the doped epitaxial layer 18 is formed on the substrate 11, so that the doping concentration of the epitaxial layer 14 is ensured, the influence of the epitaxial layer 14 on the electrical property of the bottom selection gate is effectively avoided, and the electrical property and the preparation yield of the three-dimensional memory 100 are improved.
The three-dimensional memory 100 further comprises a doped structure 21 formed at the bottom of the gate spacer 15 and an electrical conductor 22 formed in the gate spacer 15, wherein in the embodiment, the doped structure 21 is formed by N-type doping. The surface of the doped structure 21 facing away from the gate spacer 15 is connected to the epitaxial doping layer, in other words, the doped structure 21 is disposed on the doped epitaxial layer 18, so that the voltage between the doped structure 21 and the doped epitaxial layer 18 is increased, the surface voltage stress is reduced, and the electrical performance and the manufacturing yield of the three-dimensional memory 100 are improved.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims (9)

1. A method for preparing a three-dimensional memory, the method comprising:
providing the substrate;
sequentially forming a layer to be replaced and the stacked structure on the substrate, wherein the stacked structure comprises an insulating layer and a sacrificial layer;
etching the stacked structure to form the gate isolation groove, wherein the gate isolation groove exposes the layer to be replaced;
replacing the layer to be replaced with the epitaxial layer; and carrying out first doping on the epitaxial layer through the grid separation groove to form a doped epitaxial layer.
2. The method of manufacturing according to claim 1, wherein the step of "sequentially forming the layer to be replaced and the stacked structure on the substrate" and the step of "etching the stacked structure to form the gate spacer grooves, the gate spacer grooves being exposed between the layers to be replaced" includes:
etching the stacked structure to form a channel hole, the channel hole exposing the substrate;
a NAND string is formed in the channel hole.
3. The method of claim 2, wherein the NAND string comprises a conductive structure and a peripheral wall disposed at a periphery of the conductive structure, and wherein replacing the layer to be replaced with the epitaxial layer comprises:
removing the layer to be replaced to form a gap and expose the peripheral wall of the NAND string;
forming the epitaxial layer in the void.
4. The production method according to claim 3, wherein before the "forming the epitaxial layer in the voids", the production method comprises:
and removing the part of the peripheral wall on the layer to be replaced to expose part of the conductive structure so as to enable the conductive structure to be in contact with the epitaxial layer in the subsequent process.
5. The production method according to claim 4, wherein after the "forming the epitaxial layer in the voids", the production method comprises:
replacing the sacrificial layer with a gate layer.
6. The method of any one of claims 1-5, wherein the first doping the epitaxial layer through the gate spacer to form a doped epitaxial layer comprises:
and carrying out first doping on the epitaxial layer through the grid separation groove, and carrying out heating treatment to enable the epitaxial layer to form the doped epitaxial layer.
7. The method of claim 6, wherein after the first doping the epitaxial layer through the gate spacer to form a doped epitaxial layer, the method comprises:
forming an array common source in the gate spacer.
8. The method of claim 7, wherein the forming an array common source in the gate spacer comprises:
carrying out second doping on the bottom of the grid separation groove;
an electrical conductor is formed in the gate spacer.
9. The three-dimensional memory is characterized by comprising a substrate, a doped epitaxial layer and a stacked structure, wherein the doped epitaxial layer and the stacked structure are sequentially formed on the substrate, the stacked structure is provided with a grid separation groove, the grid separation groove exposes the doped epitaxial layer, and the doped epitaxial layer is formed by doping through the grid separation groove.
CN202110583956.9A 2020-01-03 2020-01-03 Preparation method of three-dimensional memory and three-dimensional memory Pending CN113314540A (en)

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