KR20130086778A - Manufacturing method of vertical non-volatile memory device - Google Patents

Abstract

PURPOSE: A method for manufacturing a vertical type non-volatile memory device is provided to improve an electrical property by using a semiconductor pillar for connecting a substrate and a semiconductor layer. CONSTITUTION: A polysilicon mask pattern (130) is formed on a substrate. A channel hole part for exposing the substrate is formed. A spacer layer for covering the upper surface of the polysilicon mask pattern is formed. A semiconductor pillar (155) is formed on the substrate. A semiconductor layer (170) in contact with the semiconductor pillar is formed.

Description

Manufacturing method of vertical non-volatile memory device

The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a vertical nonvolatile memory device.

It is required to increase the degree of integration of semiconductor devices in order to meet the excellent performance and low price required by consumers. In the case of semiconductor devices, since the degree of integration is an important factor in determining the price of a product, an increased degree of integration is particularly required. In the case of the conventional two-dimensional or planar semiconductor device, since the integration degree is mainly determined by the area occupied by the unit memory cell, it is greatly influenced by the level of the fine pattern formation technique. However, the integration of the two-dimensional semiconductor device is increasing, but is still limited, because of the high-cost equipment required to miniaturize the pattern.

In order to overcome this limitation, three-dimensional semiconductor devices having memory cells arranged three-dimensionally have been proposed. However, for mass production of three-dimensional semiconductor devices, a process technology capable of realizing reliable product characteristics while reducing manufacturing cost per bit than that of two-dimensional semiconductor devices is required.

An object of the present invention is to provide a method for manufacturing a vertical nonvolatile memory device having improved electrical characteristics.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

One embodiment of the present invention relates to a method of manufacturing a vertical nonvolatile memory device. The present invention provides a method for forming a polysilicon mask pattern on a substrate in which sacrificial layers and insulating layers are alternately and repeatedly stacked; Forming a channel opening exposing the substrate by using the poly silicon mask pattern; Forming a spacer film covering an upper surface of the polysilicon mask pattern; Forming a semiconductor pillar from the substrate exposed in the channel opening with selective epitaxial growth; And forming a semiconductor film in contact with the semiconductor pillar in the channel opening.

The semiconductor pillar includes a method of manufacturing a vertical nonvolatile memory device, wherein the semiconductor pillar is formed to fill a lower portion of the channel opening.

After the semiconductor pillars are formed, the method may further include removing the spacer layer by pre-cleaning.

And forming a vertical insulating pattern and a semiconductor spacer on an inner wall of the channel opening before forming the semiconductor layer.

The forming of the vertical insulating pattern and the semiconductor spacer on the inner wall of the channel opening may include: sequentially forming the vertical insulating layer and the semiconductor spacer layer; And removing the vertical insulating film and the semiconductor spacer film formed on the upper surface of the semiconductor pillar to expose the semiconductor pillar.

The vertical insulating film includes a method of manufacturing a vertical nonvolatile memory device, characterized in that it comprises a data storage film of the nonvolatile memory device.

The step of forming a semiconductor film in contact with the semiconductor pillar in the channel opening may include: filling a buried insulating film in the channel opening in which the semiconductor film is formed; Patterning the insulating layers and the sacrificial layers on both sides of the channel opening to form trenches; Recessing the sacrificial layers exposed in the trench to form upper and lower recess regions; And sequentially forming a horizontal insulating layer and a conductive pattern in the upper and lower recess regions, respectively.

The lower recess regions include a method of manufacturing a vertical nonvolatile memory device, wherein the lower recess regions expose a portion of the semiconductor pillar.

The horizontal insulating film includes a method of manufacturing a vertical nonvolatile memory device, characterized in that it comprises a data storage film of the nonvolatile memory device.

In the method of manufacturing a vertical nonvolatile memory device according to an embodiment of the present invention, when the channel opening is formed, the substrate is exposed so that selective epitaxial growth is performed from the substrate. Accordingly, a semiconductor pillar formed by selective epitaxial growth may electrically connect the substrate and the semiconductor film to manufacture a vertical nonvolatile memory device having improved electrical characteristics.

In the manufacturing method of the vertical nonvolatile memory device according to the exemplary embodiment of the present invention, a spacer layer may be formed on the polysilicon mask pattern. Accordingly, when the epitaxial growth is selectively performed on the lower surface of the channel opening to which the substrate is exposed, silicon growth in the polysilicon mask pattern may be suppressed, so that silicon growth may be formed in a desired portion.

1A through 1K are cross-sectional views illustrating a method of manufacturing a vertical nonvolatile memory device according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish them, will become apparent by reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms 'comprises' and / or 'comprising' mean that the stated element, step, operation and / or element does not imply the presence of one or more other elements, steps, operations and / Or additions.

In addition, the embodiments described herein will be described with reference to cross-sectional views and / or plan views, which are ideal illustrations of the present invention. In the drawings, the thicknesses of films and regions are exaggerated for effective explanation of technical content. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include variations in forms generated by the manufacturing process. For example, the etched area shown at right angles may be rounded or may have a shape with a certain curvature. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.

1A to 1K are cross-sectional views illustrating a method of manufacturing a vertical nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 1A, the sacrificial layers 110 and the insulating layers 120, 120L, and 120U are alternately and repeatedly stacked on the substrate 10. The substrate 10 may be one of materials having semiconductor characteristics, insulating materials, and a semiconductor or a conductor covered by the insulating material. For example, the substrate 10 may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, or a compound semiconductor substrate.

The sacrificial layers 110 may be formed of a material having an etch selectivity with respect to the insulating layers 120, 120L, and 120U. That is, in the process of etching the sacrificial layers 110 using a predetermined etching recipe, the sacrificial layers 110 may be etched while minimizing the etching of the insulating layers 120, 120L, and 120U. It can be formed as. As is known, such etch selectivity may be quantitatively expressed through a ratio of etching rates of the sacrificial layers 110 to etching rates of the insulating layers 120, 120L, and 120U.

The sacrificial layers 110 may be at least one of a silicon layer, a silicon oxide layer, a silicon carbide, a silicon oxynitride layer, and a silicon nitride layer, and may be formed of a material different from those of the insulating layers 120, 120L, and 120U. The insulating layers 120, 120L, and 120U may be at least one of a silicon layer, a silicon oxide layer, a silicon carbide, a silicon oxynitride layer, and a silicon nitride layer, and may be formed of a material different from that of the sacrificial layers 110.

The sacrificial layers 110 may be formed to have substantially the same thickness. The thicknesses of the insulating layers 120, 120L, and 120U may not be the same. For example, the lowermost insulating layer 120L may be thinner than the insulating layers 120 and 120U. The uppermost insulating layer 120U may be formed thicker than the insulating layers 120 and 120L. The thickness of these insulating layers may be variously modified from those shown. The number of layers of the sacrificial layers 110 and the insulating layers 120, 120L, and 120U may be variously modified.

Referring to FIG. 1B, a polysilicon mask pattern 130 is formed on the uppermost insulating layer 120U. The channel opening 140 exposing the substrate 10 is formed by anisotropically etching the substrate 10 using the polysilicon mask pattern 130 as an etching mask. The substrate 10 may be recessed to a predetermined depth by over etching. Formation of the channel opening 140 may expose sidewalls of the sacrificial layers 110 and the insulating layers 120, 120L, and 120U. The channel opening 140 may have a different width depending on the height from the substrate 10 by the anisotropic etching process. That is, the channel opening 140 may have sidewalls that are inclined with respect to the substrate 10. The channel opening 140 may have a hole shape. The channel opening 140 may be circular, elliptical or polygonal in plan view.

Referring to FIG. 1C, after forming the channel opening 140, a spacer layer 150 covering the top surface of the polysilicon mask pattern 130 is formed. The spacer layer 150 may be formed using any one of chemical vapor deposition and atomic layer deposition. The spacer layer 150 may be a silicon oxide layer or a silicon nitride layer. The spacer layer 150 may be formed using a deposition process such as physical vapor deposition or chemical vapor deposition. When the spacer layer 150 is formed using the deposition process, the spacer layer 150 may cover an upper sidewall of the channel opening 140. Meanwhile, since the aspect ratio of the channel opening is large, it may be difficult to deposit the lower portion of the channel opening 140. That is, the spacer film 150 may not be deposited on the upper surface of the substrate 10 exposed by the channel opening 140.

After forming the spacer layer 150, a semiconductor pillar 155 is formed to fill the lower surface of the channel opening 140. The semiconductor pillar 155 may be formed from the substrate 10 using selective epitaxial growing using the substrate 10 exposed to the channel opening 140 as a seed. Accordingly, when the substrate is a single crystal silicon substrate, the semiconductor pillar 155 may be a single crystal silicon film. The semiconductor pillar 155 may be formed of a conductive semiconductor or an intrinsic semiconductor, such as the substrate 10. For example, when the substrate 10 is a semiconductor material (eg, a silicon wafer) having a p-type conductivity, the semiconductor pillar 155 may be a p-type or an intrinsic semiconductor. The spacer layer 150 suppresses silicon growth in the polysilicon mask pattern 130 when the semiconductor pillar 155 is formed by the selective epitaxial growth method.

Referring to FIG. 1D, the spacer layer 150 may be removed by a pre-cleaning process. The spacer layer 150 may be completely removed. Alternatively, the spacer 151 may be formed by remaining on an upper surface of the polysilicon mask pattern 130 and a portion of an upper sidewall of the channel opening 140. The pre-cleaning process may be an isotropic etching process or an anisotropic etching process.

In the previous process, the vertical insulating layer 160 and the semiconductor spacer layer 162 are sequentially formed on an inner wall of the channel opening 140 in which the spacer 151 is formed. The vertical insulating layer 160 and the semiconductor spacer layer 162 may be formed to conformally cover inner walls of the channel openings 140 to a thickness not completely filling the channel openings 140. The vertical insulating layer 160 may cover the upper surface of the semiconductor pillar 155 exposed in the channel opening 140.

The vertical insulating layer 160 may be formed of one thin film or a plurality of thin films. For example, the vertical insulating layer 160 may include at least one of thin films (eg, data storage layers) used as memory elements of a charge trapping nonvolatile memory transistor. The vertical insulating layer 160 may be formed of an insulating material having an etch selectivity with respect to the sacrificial layers 110, and may include one or a plurality of thin films.

The semiconductor spacer layer 162 may be a polycrystalline silicon layer formed by one of an atomic layer deposition (ALD) technique or a chemical vapor deposition (CVD) technique. Alternatively, the semiconductor spacer layer 162 may be one of an organic semiconductor layer and carbon nanostructures.

Referring to FIG. 1E, the semiconductor spacer layer 162 and the vertical insulating layer 160 are anisotropically etched to form a semiconductor spacer 163 and a vertical insulating pattern 161 exposing the top surface of the semiconductor pillar 155. do. Accordingly, the vertical insulating pattern 161 and the semiconductor spacer 163 may be formed in a cylindrical shape having both open ends.

Meanwhile, during the anisotropic etching step, a portion of the vertical insulating layer 160 positioned below the semiconductor spacer layer 162 may not be etched. In this case, the vertical insulating pattern 161 may be formed of the semiconductor spacer layer. It may have a bottom portion interposed between the bottom surface of the 162 and the top surface of the semiconductor pillar 155.

In addition, an upper surface of the spacer 151 remaining on the polysilicon mask pattern 130 may be exposed as a result of anisotropic etching of the vertical insulating layer 160 and the semiconductor spacer layer 162. . Accordingly, the vertical insulating pattern 161 and the semiconductor spacer 163 may be localized in the channel opening 140. That is, the vertical insulating pattern 161 and the semiconductor spacer 163 may be two-dimensionally arranged on the xy plane.

Referring to FIG. 1F, after the vertical insulating pattern 161 and the semiconductor spacer 163 are formed, the semiconductor film 170 and the buried insulating film 180 are sequentially formed in the empty space of the channel opening 140.

A portion of the lower region of the semiconductor film 170 may be inserted into the upper surface of the semiconductor pillar 155.

The semiconductor film 170 may be a polycrystalline silicon film formed using any one of an atomic layer deposition (ALD) technique or a chemical vapor deposition (CVD) technique. The semiconductor layer 170 may be conformally formed to have a thickness that does not completely fill the channel opening 140. That is, the semiconductor film 170 may be formed in a pipe-shaped, hollow cylindrical shape, or cup shape in the channel opening 140.

The semiconductor layer 170 may be in contact with an upper surface of the semiconductor pillar 155 exposed by the anisotropic etching. Therefore, the semiconductor pillar 155 may electrically connect the substrate 10 and the semiconductor layer 170 to manufacture a vertical nonvolatile memory device having improved electrical characteristics.

The buried insulating layer 180 may be formed to fill the channel opening 140 in which the semiconductor layer 170 is formed, and may be one of insulating materials and silicon oxide layers formed by using SOG technology. have.

Before forming the buried insulating layer 180, a hydrogen annealing step may be further performed to heat-treat the resulting product on which the semiconductor film 170 is formed in a gas atmosphere containing hydrogen or deuterium. Many of the crystal defects present in the semiconductor spacer 163 and the semiconductor film 170 may be healed by this hydrogen annealing step.

Referring to FIG. 1G, the planarization process may be performed using the uppermost insulating layer 120U as an etch stop layer. The planarization process may be performed by an etch back process or a chemical mechanical polishing (CMP) method. The polysilicon mask pattern 130 on the uppermost insulating layer 120U may be removed by the planarization process.

The upper region of the spacer 151, the vertical insulating pattern 161, the semiconductor spacer 163, and the semiconductor layer 170 formed in the channel opening 140 is recessed, and then within the recessed region. The conductive pad D may be formed by filling the conductive material. In addition, the conductive pad D may be formed by doping impurities of a different conductivity type from the semiconductor film 170 positioned below the conductive pad D. FIG. The spacer 151 may be completely removed by forming the conductive pad D. The conductive pad D may form a lower region and a diode.

Referring to FIG. 1H, trenches 210 may be formed by successively patterning the sacrificial layers 110 and the insulating layers 120, 120L, and 120U. The trenches 210 define sacrificial patterns 110a and insulating patterns 120a, 120La, and 120Ua that are alternately and repeatedly stacked. The pair of trenches 210 are formed at both sides of the channel opening 140, and the sacrificial patterns 110a and the insulating patterns 120a, 120La, and 120Ua are formed on sidewalls of the trenches 210. This can be exposed. In the horizontal shape, the trenches 210 may be formed in a line shape or a rectangle.

The trenches 210 may be formed by forming an etching mask on the uppermost insulating layer 120U, and then anisotropically etching the layers under the etching mask until the upper surface of the substrate 10 is exposed. It may include a step. As a result of over-etch in the anisotropic etching step, the substrate 10 under the trenches 210 may be recessed to a predetermined depth. In addition, the trenches 210 may have different widths depending on the distance from the substrate 10.

Referring to FIG. 1I, the sacrificial patterns 110a exposed to the trenches 210 may be removed to form upper recess regions 220 and lower recesses between the insulating patterns 120a, 120La, and 120Ua. The recess regions 222 are formed. The upper and lower recess regions 220 and 222 may extend horizontally from the trenches 210 between the insulating patterns 120a, 120La, and 120Ua.

The upper recess regions 220 may expose portions of sidewalls of the vertical insulating pattern 161. That is, an outer boundary of the upper recess regions 220 may be formed in the insulating patterns 120a and 120Ua disposed at upper and lower portions thereof and in the trenches 210 positioned at both sides thereof. It is limited by. In addition, an internal boundary of the upper recess regions 220 is defined by the vertical insulating pattern 161 penetrating vertically therethrough. The lower recess regions 222 may expose portions of sidewalls of the semiconductor pillar 155. That is, an outer boundary of the lower recess regions 222 may be formed in the insulating patterns 120a and 120La positioned at upper and lower portions thereof and in the trenches 210 positioned at both sides thereof. It is limited by. In addition, an internal boundary of the lower recess regions 222 is defined by the semiconductor pillar 155 vertically penetrating it.

The method of forming the upper and lower recess regions 220 and 222 may have an etch selectivity with respect to the insulating patterns 120a, 120La, and 120Ua, the vertical insulating pattern 161, and the semiconductor pillar 155. And selectively etching the sacrificial patterns 110a using an etching recipe. The selective etching may be wet etching and / or isotropic dry etching. For example, when the sacrificial patterns 110a are silicon nitride layers and the insulating patterns 120a, 120La and 120Ua are silicon oxide layers, the horizontal etching step may be performed using an etchant including phosphoric acid. .

Referring to FIG. 1J, a conductive layer filling the remaining spaces of the horizontal insulating layer 230 covering the inner walls of the upper and lower recess regions 220 and 222 and the upper and lower recess regions 220 and 222 ( 240).

The method of forming the horizontal insulating film 230 and the conductive pattern 240 may include forming the horizontal insulating film 230 and the conductive film sequentially covering the recess regions 220 and 222, and then forming the trenches 210. And removing the conductive layer from the substrate to leave the conductive pattern 240 in the recess regions 220 and 222.

The horizontal insulating layer 230 may be formed of one thin film or a plurality of thin films similar to the vertical insulating film 160. The horizontal insulating layer 230 may include a blocking insulating layer of the charge trapping nonvolatile memory transistor. In addition, the horizontal insulating film 230 may further include a charge storage film or a tunnel insulating film.

The conductive layer may include at least one of doped silicon, metal materials, metal nitride layers, or metal silicides. For example, the conductive film may include a metal material such as tantalum nitride film or tungsten. The conductive layer may be formed to conformally cover the inner walls of the trenches 210. In this case, the forming of the conductive pattern 240 may isotropically etch the conductive layer in the trenches 210. It may include the step of removing. According to another embodiment, the conductive layer may be formed to fill the trenches 210. In this case, the forming of the conductive pattern 240 may be performed by anisotropically etching the conductive layer in the trenches 210. It may include a step.

Referring to FIG. 1K, after the conductive pattern 240 is formed, the step of forming the impurity regions 15 may be further performed. The impurity regions 15 may be formed through an ion implantation process and may be formed in the substrate 10 exposed through the trenches 210. Meanwhile, the impurity regions 15 may have a different conductivity type from that of the substrate 10.

After forming the impurity regions 15, an upper isolation pattern 250 may be formed to fill the trenches 210, and the upper plug 265 and the upper plug may be connected to each of the conductive pads D, respectively. An upper wiring 260 connecting the 265 is formed.

The electrode separation pattern 250 may be formed of at least one of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. The upper plugs 265 may be formed of one of doped silicon or metallic materials.

The upper wiring 260 may be electrically connected to the second space 162 and the semiconductor layer 170 through the upper plug 265, and may cross the conductive pattern 240 or the trenches 210. It can be formed to shout.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative and not restrictive in every respect.

10: substrate
15: impurity regions
110: Sacrifice
111a: Sacrifice patterns
120, 120L, 120U: insulating films
120L: bottom insulating film
120U: top insulating film
120a, 120La, 120Ua: insulation patterns
130: polysilicon mask pattern
140: channel opening
150: spacer film
151: Spacer
155: semiconductor pillar
160: vertical insulating film
161: vertical insulation pattern
162: semiconductor spacer film
163: semiconductor spacer
170: semiconductor film
180: buried insulating film
210: trenches
220, 222: recessed areas
230: horizontal insulating film
240: challenge pattern
250: electrode separation pattern
265: upper plugs

Claims (9)

Forming a polysilicon mask pattern on the substrate in which the sacrificial films and the insulating films are alternately and repeatedly stacked;
Forming a channel opening exposing the substrate by using the poly silicon mask pattern;
Forming a spacer film covering an upper surface of the polysilicon mask pattern;
Forming a semiconductor pillar from the substrate exposed in the channel opening with selective epitaxial growth; And
And forming a semiconductor film in contact with the semiconductor pillar in the channel opening. The method of claim 1,
And the semiconductor pillar is formed to fill a lower portion of the channel opening. The method of claim 1,
And forming the semiconductor pillar, and then removing the spacer layer by pre-cleaning. The method of claim 1,
And forming a vertical insulating pattern and a semiconductor spacer on an inner wall of the channel opening before forming the semiconductor film. The method of claim 4, wherein
The forming of the vertical insulating pattern and the semiconductor spacer on the inner wall of the channel opening may include:
Sequentially forming a vertical insulating film and a semiconductor spacer film;
And removing the vertical insulating film and the semiconductor spacer film formed on the upper surface of the semiconductor pillar to expose the semiconductor pillar. The method of claim 5, wherein
And the vertical insulating film comprises a data storage film of a nonvolatile memory device. The method of claim 1,
Filling a buried insulating film into the channel opening in which the semiconductor film is formed;
Patterning the insulating layers and the sacrificial layers on both sides of the channel opening to form trenches;
Recessing the sacrificial layers exposed in the trench to form upper and lower recess regions; And
And sequentially forming a horizontal insulating layer and a conductive pattern in the upper and lower recess regions. The method of claim 7, wherein
And the lower recess regions expose portions of the semiconductor pillars. The method of claim 7, wherein
And the horizontal insulating film comprises a data storage film of a nonvolatile memory device.

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