CN111370424A - Three-dimensional flash memory and manufacturing method thereof - Google Patents
Three-dimensional flash memory and manufacturing method thereof Download PDFInfo
- Publication number
- CN111370424A CN111370424A CN202010298632.6A CN202010298632A CN111370424A CN 111370424 A CN111370424 A CN 111370424A CN 202010298632 A CN202010298632 A CN 202010298632A CN 111370424 A CN111370424 A CN 111370424A
- Authority
- CN
- China
- Prior art keywords
- layer
- type
- type doped
- doped layer
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses a three-dimensional flash memory and a manufacturing method thereof, and the technical scheme of the invention is that a side wall channel structure is arranged between a storage stacking structure and a substrate, the side wall channel structure comprises a second N-type doped layer and a P-type doped layer, the second N-type doped layer is positioned between the first N-type doped layer and the P-type doped layer, the P-type doped layer is used for connecting a P-type trap region in the substrate during erasing operation and providing a hole, the second N-type doped layer is used for providing a conductive channel during reading operation and providing electrons during programming operation, the independent transmission of the electrons and the hole can be realized, and in the reading operation process, the electrons are transmitted through the second N-type doped layer at the upper part in the side wall channel structure, so that the requirement on a lower selection tube in the storage stacking structure is greatly reduced.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a three-dimensional flash memory (3DNAND) with a side wall channel structure and a manufacturing method thereof.
Background
For a conventional two-dimensional planar memory, since the integration density mainly depends on the unit area occupied by a single memory cell, the integration degree is very dependent on the quality of the photolithography and the mask process. But is limited by the current process conditions, and even if expensive process equipment is continuously adopted to improve the precision of the photoetching and masking process, the improvement of the integration level is still limited. In order to solve the above-described problems of the two-dimensional planar memory, 3D NAND has been produced. The 3D NAND is a main development direction in the current memory field, in which memory cells are stacked in a direction perpendicular to a substrate, and more memory cells can be formed in a smaller area, and have a larger storage capacity compared to a conventional two-dimensional planar memory.
With the continuous increase of the number of stacked layers in the 3D NAND, the channel current is reduced sharply, meanwhile, the channel conduction mode also faces huge challenges, and the side wall channel communication method becomes a solution for communication between the channel and the substrate.
Disclosure of Invention
In view of this, the present application provides a 3D NAND with a sidewall trench structure and a method for manufacturing the same, and the scheme is as follows:
a method for manufacturing a three-dimensional flash memory, the method comprising:
providing a substrate, wherein the substrate is internally provided with a P-type well region;
forming a functional layer above the P-type well region, wherein the functional layer comprises a first N-type doped layer and a sacrificial layer positioned between the substrate and the first N-type doped layer;
forming a storage stack on the functional layer;
forming a channel hole structure penetrating through the storage stack structure and the functional layer, the channel hole structure extending into the P-type well region; the trench hole structure includes: a channel hole through the storage stack structure; the gate dielectric layer is arranged on the surface of the channel hole; the channel layer is arranged on the surface of the gate dielectric layer; and a channel filling medium filled in the channel layer gap;
forming a side wall channel structure between the first N-type doped layer and the P-type trap region based on the functional layer; the side wall channel structure comprises a second N-type doped layer and a P-type doped layer, and the second N-type doped layer is positioned between the first N-type doped layer and the P-type doped layer; the side wall channel structure is connected with the channel layer.
Preferably, in the above manufacturing method, a doping concentration of the first N-type doped layer is greater than that of the second N-type doped layer;
the doping concentration of the P-type well region is greater than that of the P-type doping layer.
Preferably, in the above manufacturing method, the method for forming the side wall channel structure includes:
removing the sacrificial layer and the gate dielectric layer between the first N-type doped layer and the P-type well region to expose the channel layer;
forming an undoped side wall channel structure between the first N-type doped layer and the P-type well region;
and diffusing doping elements in the first N-type doping layer and the P-type well region to an undoped side wall channel structure to form the second N-type doping layer and the P-type doping layer.
Preferably, in the above manufacturing method, the sacrificial layer includes an undoped polysilicon layer, a first SiOxNy layer is provided between the polysilicon layer and the P-type well region, and a second SiOxNy layer is provided between the polysilicon layer and the first N-type doped layer;
the method for removing the sacrificial layer comprises the following steps:
forming a trench penetrating through the stacked structure, the trench penetrating through the first N-type doped layer and the second SiOxNy layer to expose the polysilicon layer;
and removing the first SiOxNy layer and the second SiOxNy layer after removing the polysilicon layer and the gate dielectric layer between the first N-type doped layer and the P-type trap region.
Preferably, in the above manufacturing method, after the second N-type doped layer and the P-type doped layer are formed, the method further includes:
and forming an N-type doped region at the bottom of the groove, wherein the N-type doped region is connected with the second N-type doped layer or the first N-type doped layer and the second N-type doped layer simultaneously, and the N-type doped region is connected with an external circuit through an array common source line.
Preferably, in the above manufacturing method, the memory stack structure includes a plurality of first dielectric layers and a plurality of second dielectric layers alternately arranged;
after the second N-type doped layer and the P-type doped layer are formed, the method further includes:
removing the second dielectric layers to form gaps between the adjacent first dielectric layers;
and filling metal in the gap to form a gate layer.
Preferably, in the above manufacturing method, the second N-type doped layer and the P-type doped layer satisfy the same condition of thickness, and both thicknesses are greater than 0.
The present invention also provides a three-dimensional flash memory, comprising:
the semiconductor device comprises a substrate, a first substrate and a second substrate, wherein a P-type well region is arranged in the substrate;
the side wall channel structure is positioned above the P-type well region;
the first N-type doping layer is positioned above the side wall channel structure;
the storage stacking structure is positioned above the first N-type doping layer and comprises a plurality of layers of first dielectric layers and gate layers which are alternately arranged;
a channel hole structure extending through the storage stack structure, the channel hole structure extending into the P-type well region; the trench hole structure includes: a channel hole through the storage stack structure; the gate dielectric layer is arranged on the surface of the channel hole; the channel layer is arranged on the surface of the gate dielectric layer; and a channel filling medium filled in the channel layer gap;
the side wall channel structure comprises a second N-type doped layer and a P-type doped layer, wherein the second N-type doped layer is positioned between the first N-type doped layer and the P-type doped layer; the side wall channel structure is connected with the channel layer.
Preferably, in the three-dimensional flash memory, the doping element in the first N-type doping layer is diffused to the sidewall channel structure to form the second N-type doping layer;
and the doping elements in the P-type well region are diffused to the side wall channel structure to form the P-type doping layer.
Preferably, in the three-dimensional flash memory, the doping concentration of the first N-type doping layer is greater than that of the second N-type doping layer;
the doping concentration of the P-type well region is greater than that of the P-type doping layer.
As can be seen from the above description, in the 3D NAND and the manufacturing method thereof provided in the technical solution of the present invention, a side wall channel structure is provided between the storage stacked structure and the substrate, the side wall channel structure includes a second N-type doped layer and a P-type doped layer, the second N-type doped layer is located between the first N-type doped layer and the P-type doped layer, the P-type doped layer is used for connecting a P-type well region in the substrate during an erase operation and providing a hole, the second N-type doped layer is used for providing a conduction channel during a read operation and providing an electron during a program operation, and independent transmission of the electron and the hole can be achieved.
Drawings
In order to more clearly illustrate the embodiments of the present application or technical solutions in related arts, the drawings used in the description of the embodiments or prior arts will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
The structure, proportion, size and the like shown in the drawings are only used for matching with the content disclosed in the specification, so that the person skilled in the art can understand and read the description, and the description is not used for limiting the limit condition of the implementation of the invention, so the method has no technical essence, and any structural modification, proportion relation change or size adjustment still falls within the scope of the technical content disclosed by the invention without affecting the effect and the achievable purpose of the invention.
FIG. 1 is a schematic diagram of a conventional 3D NAND structure;
FIG. 2 is a schematic structural diagram of a 3D NAND with a sidewall structure;
fig. 3-13 are process flow diagrams of a method for manufacturing a 3D NAND according to an embodiment of the invention.
FIG. 14 is a schematic diagram illustrating hole h + transport principles in a 3D NAND according to an embodiment of the present invention;
FIG. 15 is a schematic diagram of the e-transmission principle of electrons in 3D NAND according to the embodiment of the invention.
Detailed Description
The embodiments of the present application will be described in detail and fully with reference to the accompanying drawings, wherein the description is only for the purpose of illustrating the embodiments of the present application and is not intended to limit the scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
As shown in fig. 1, fig. 1 is a schematic structural diagram of a 3D NAND with a conventional structure, which includes: the memory structure comprises a P-type well region 11, a storage stack structure arranged on the P-type well region 11, and an N-type doped region 12 arranged in the P-type well region 11, wherein the N-type doped region 12 is doped N +, and is an N-type heavily doped region. The storage stack structure includes: a lower selection pipe BSG and an upper selection pipe TSG, and a multi-layer gate layer therebetween. The multi-layer gate layer includes: a lower redundant gate layer 13 and an upper redundant gate layer 14, and a data gate layer 15 of a multi-layer stack therebetween, the data gate layer 15 being a gate of the memory cell as a word line WL. A dielectric layer is arranged between two adjacent layers of the storage stacking structure, and a dielectric layer is arranged between the lower selection tube BSG and the P-type well region 11. The P-type well region 11 is further provided with a channel hole structure 16 penetrating through the storage stack structure, the upper end of the channel hole structure 16 is provided with an n + doped region 17, and a bit line BL is arranged above the n + doped region 17.
The trench hole structure 16 includes: a channel hole penetrating the storage stack structure; a gate dielectric layer 161 disposed on the surface of the trench hole; a channel layer 162 disposed on the surface of the gate dielectric layer 161; and a channel filling dielectric 163 filled in the gap of the channel layer 162. The gate dielectric layer 161 includes a plurality of gate dielectric structures, such as a blocking layer, a storage layer, and a tunneling layer, which are sequentially formed. The channel layer 162 may be polysilicon. The trench fill dielectric 163 may be silicon oxide. The N-type doped region 12 is connected with an external circuit through an array common source line ACS.
With the increasing number of stacked layers in the 3D NAND, the channel current in the conventional 3D NAND shown in fig. 1 is sharply reduced, and the channel conduction mode also faces a great challenge. The 3D NAND of the sidewall structure shown in fig. 2 becomes a solution for the channel to substrate communication.
Bulk erase architecture: the 3D NAND substrate comprises a P-type well region which provides holes required during erasing operation, and meanwhile, a channel is inverted by using a lower selection tube during reading operation, so that current conduction can be realized, and reading operation can be realized. However, in the sidewall channel conduction mode, the erasing operation can be realized by using the P-type well region alone, but the lower selection tube cannot effectively open the sidewall channel, and the reading operation is difficult to realize. The requirement on the lower selection tube is high, and the control capability in both the horizontal direction (inversion of P-type well region) and the vertical direction (channel switch) is required
As shown in fig. 2, fig. 2 is a schematic structural diagram of a 3D NAND with a sidewall structure, based on the method shown in fig. 1, in the method shown in fig. 2, the channel hole structure 16 extends into the P-type well region 11, and the channel hole structure 16 is located at a portion inside the P-type well region 11, and the sidewall gate dielectric layer 161 is removed to leak out of the channel layer 162.
Fig. 2 shows that there are two erasing modes based on the sidewall channel connection structure, which are GIDL (gate induced drain Leakage) erasing and bulk erasing, respectively. The cell for generating GIDL during GIDL erasure needs to bear great electrical stress, resulting in poor reliability of the device, and also has relatively large potential drop and low erasure speed, and in addition, there are relatively large fluctuations in the efficiency and amount of holes generated by different GIDL cells. The holes needed in the bulk erase mode are provided by the P-type well region 11, the stability during erase is good, but in the read operation process, the P-type well region 11 needs to be inverted to form a conductive channel, a side wall channel cannot be conducted, the requirement on the BSG of the lower selection tube is high, and the control capability in the horizontal direction (inversion of the P-type well region 11) and the control capability in the vertical direction (channel switch) need to be considered at the same time.
In order to solve the above problems, an embodiment of the present invention provides a method for manufacturing a 3D NAND, where the method includes:
providing a substrate, wherein the substrate is internally provided with a P-type well region;
forming a functional layer above the P-type well region, wherein the functional layer comprises a first N-type doped layer and a sacrificial layer positioned between the substrate and the first N-type doped layer;
forming a storage stack on the functional layer;
forming a channel hole structure penetrating through the storage stack structure and the functional layer, the channel hole structure extending into the P-type well region; the trench hole structure includes: a channel hole through the storage stack structure; the gate dielectric layer is arranged on the surface of the channel hole; the channel layer is arranged on the surface of the gate dielectric layer; and a channel filling medium filled in the channel layer gap;
forming a side wall channel structure between the first N-type doped layer and the P-type trap region based on the functional layer; the side wall channel structure comprises a second N-type doped layer and a P-type doped layer, and the second N-type doped layer is positioned between the first N-type doped layer and the P-type doped layer; the side wall channel structure is connected with the channel layer.
Based on the 3D NAND prepared by the preparation method, a specific side wall channel structure can be formed, and areas with different doping types are prepared in the side wall channel structure, wherein the preparation method comprises the following steps: a lower P-type doped layer and an upper second N-type doped layer. The P-type doped layer is used for connecting the P-type well region during erasing operation and providing holes. The second N-type doped layer is used for providing a conductive channel during reading operation and also providing electron electrons during programming operation.
The technical scheme of the invention can realize independent transmission of electrons and holes, the side wall channel structure is easy to conduct, the requirement on the lower selection tube is low, and the control capability in the horizontal direction and the vertical direction is not required to be considered simultaneously. The doping concentration of the first N-type doping layer with the N-type heavy doping is increased to form a second N-type doping layer with higher doping concentration, so that the second N-type doping layer is easy to be in a conducting state in the required operation process.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and the detailed description.
As shown in fig. 3 to 13, fig. 3 to 13 are process flow charts of a 3D NAND manufacturing method according to an embodiment of the present invention, where the manufacturing method includes:
step S11: as shown in fig. 3, a substrate having a P-well region 21 therein is provided.
The substrate is a semiconductor substrate, such as a silicon substrate. A P-type well region 21 is formed in an upper surface thereof. P-type well region 21 may be formed within the substrate surface by an implantation process.
Step S12: as shown in fig. 4, a functional layer 22 is formed over the P-well region 21.
The functional layer 22 includes a first N-type doped layer 221 and a sacrificial layer 222 between the substrate and the first N-type doped layer 221.
Step S13: as shown in fig. 5, a storage stack structure 23 is formed on the functional layer 22.
Step S14: as shown in fig. 6, a trench hole structure 24 is formed through the storage stack structure 23 and the functional layer 22.
The channel hole structure 24 extends into the P-well region 21; the trench hole structure 24 includes: a channel hole 241 penetrating the storage stack structure 23; a gate dielectric layer 242 disposed on the surface of the channel hole 241; a channel layer 243 disposed on the surface of the gate dielectric layer 242; and a channel filling medium 244 filled in the gap of the channel layer 243. The gate dielectric layer 242 includes a blocking layer (which may be silicon oxide), a storage layer (which may be SiOxNy and/or silicon nitride), and a tunneling layer (which may be silicon oxide and/or SiOxNy) formed in sequence. The channel layer 243 may be polysilicon. The trench fill dielectric 244 may be silicon oxide.
Step S15: as shown in fig. 7 to 11, based on the functional layer 22, a sidewall channel structure 25 is formed between the first N-type doped layer 221 and the P-type well region 21; the sidewall channel structure 25 includes a second N-type doped layer 251 and a P-type doped layer 252, wherein the second N-type doped layer 251 is located between the first N-type doped layer 221 and the P-type doped layer 252; the sidewall channel structure 25 is connected to the channel layer 243.
The doping concentration of the first N-type doping layer 221 may be set to be greater than that of the second N-type doping layer 251; the doping concentration of the P-well region 21 is greater than the doping concentration of the P-doped layer 252.
In the embodiment of the present invention, the method for forming the sidewall trench structure 25 includes:
step S21: as shown in fig. 7 to 9, the sacrificial layer 222 and the gate dielectric layer 242 between the first N-type doped layer 221 and the P-type well region 21 are removed, and the channel layer 243 is exposed.
In the embodiment of the invention, as shown in fig. 7, the sacrificial layer 222 includes an undoped polysilicon layer 31, a first SiOxNy layer 32 is disposed between the polysilicon layer 31 and the P-type well region 21, and a second SiOxNy layer 33 is disposed between the first N-type doped layer 221. The ratio of x and y in SiOxNy can be set based on requirements. The respective layer structures of the functional layer may be formed by a deposition process.
In step S21, the method for removing the sacrificial layer 222 includes:
first, as shown in fig. 7, a trench 26 penetrating through the stacked structure 23 is formed, wherein the trench 26 penetrates through the first N-type doped layer 221 and the second SiOxNy layer 33, and exposes the polysilicon layer 31.
Then, as shown in fig. 8, an insulating dielectric layer 27 is formed on the surface of the trench 26. The insulating dielectric layer 27 may be silicon oxide. The insulating dielectric layer 27 is formed by a deposition process. The insulating dielectric layer 27 at the bottom of the trench 26 is removed by an etching process to expose the polysilicon layer 31.
As shown in fig. 9, after the polysilicon layer 31 is removed, the first SiOxNy layer 32, the SiOxNy layer 33, and the gate dielectric layer 242 between the first N-type doped layer and the P-type well region are removed. In this process, the polysilicon layer 31 may be removed by first etching, and at this time, the first SiOxNy layer 32, the SiOxNy layer 33, and the insulating dielectric layer 27 serve as protective layers, so as to prevent the storage stack structure 23 from being etched, and after the first etching process is completed, the gate dielectric layer 242, the first SiOxNy layer 32, the second SiOxNy layer 33, and the insulating dielectric layer 27 are removed by a second etching process.
Step S22: as shown in fig. 10, an undoped sidewall channel structure 25' is formed between the first N-type doped layer 221 and the P-type well region 21. The undoped sidewall channel structure 25' may be formed by an epitaxial process or LPCVD deposition. The undoped sidewall spacer channel structure 25' is polysilicon and/or single crystal silicon. The height of the sidewall channel structure 25' in the trench 26 can be adjusted according to the ACS doping condition of the array common source line formed in the subsequent step.
Step S23: as shown in fig. 11, the second N-type doped layer 241 and the P-type doped layer 252 are formed by diffusing the doping elements in the first N-type doped layer 221 and the P-type well region 21 into the undoped sidewall channel structure 25', so as to form the doped sidewall channel structure 25.
As shown in fig. 11, the storage stack structure 23 includes a plurality of first dielectric layers 231 and second dielectric layers 232 alternately arranged. The surface of the first N-type doped layer 221 is the bottom first dielectric layer 231 in the storage stack structure 23. The various layer structures in the storage stack structure 23 may be formed by a deposition process. The first dielectric layer 231 may be silicon oxide and the second dielectric layer 232 may be silicon nitride.
As shown in fig. 12, after the second N-type doped layer 251 and the P-type doped layer 252 are formed, the method further includes: removing the second dielectric layers 232 to form gaps between the adjacent first dielectric layers 231; the gap is filled with a metal to form a gate layer 233. The bottom gate layer 233 constitutes a lower select transistor BSG, and the top gate layer 233 constitutes an upper select transistor TSG. The gate layer 233 adjacent to the lower select transistor BSG is a lower redundancy layer 234, the gate layer 233 adjacent to the upper select transistor TSG is an upper redundancy layer 235, and the gate layer 233 between the lower redundancy layer 234 and the upper redundancy layer 235 serves as a word line WL.
The trench via structure 24 has a recess at the top to remove the channel layer 243 and the trench filling medium 244 at the top, and the recess is filled with an N-type heavily doped (N +) filling block 29.
As shown in fig. 13, after the second N-type doped layer 251 and the P-type doped layer 252 are formed, the method further includes: an N-type doped region 28 is formed at the bottom of the trench 26, and the N-type doped region 28 is connected to the second N-type doped layer 251, or is connected to the first N-type doped layer 221 and the second N-type doped layer 251 at the same time, and the N-type doped region 28 is connected to an external circuit through an array common source line ACS. Based on the trench 26, the second N-type doped layer exposed at the bottom of the trench 26 may be doped N-type to form an N + heavily doped region N + as the N-type doped region 28. After the array common source line ACS is formed, the bit line BL is formed on the upper surface of the pad block 29.
In the embodiment of the present invention, the first N-type doped layer 251 and the P-type doped layer 252 satisfy the condition of the same thickness, and the difference between the thicknesses of the first N-type doped layer 251 and the P-type doped layer 252 is smaller than a predetermined threshold, i.e. the thicknesses of the first N-type doped layer and the P-type doped layer are the same or approximately the. The thicknesses of the first N-type doped layer 251 and the P-type doped layer 252 may be 1:1, or other ratios, not limited to 1. The thicknesses of the two layers are respectively determined by the diffusion distance from the first N-type doping layer 221 to the lower part of the undoped sidewall channel structure 25 'and the diffusion distance from the diffusion setting of the P-type well region 21 to the upper part of the undoped sidewall channel structure 25'.
As shown in fig. 14, fig. 14 is a schematic diagram illustrating a principle of transmitting holes h + in a 3D NAND according to the embodiment of the present invention, and as can be seen from fig. 14, the holes h + in the P-type well region 21 enter the sidewall channel structure 25 through the P-type doping layer 252 and further enter the channel layer 243 to implement an erase operation.
FIG. 15 shows an electron e in a 3D NAND according to an embodiment of the present invention, as shown in FIG. 5-Schematic diagram of transmission principle, as can be seen from FIG. 15, electrons e in ACS-And the second N-type doped layer 251 of the sidewall channel structure 25 enters the channel layer 243 to form a channel current, so that the read operation is realized.
The 3D NAND manufactured by the manufacturing method provided by the embodiment of the invention can realize independent transmission of electrons and holes, the side wall channel structure 25 is easy to conduct, the requirement on the lower selection tube BSG is low, and the control capability in the horizontal direction and the vertical direction is not required to be considered at the same time. The doping concentration of the first N-type doping layer with the N-type heavy doping is increased to form a second N-type doping layer with higher doping concentration, so that the second N-type doping layer is easy to be in a conducting state in the required operation process.
Based on the foregoing embodiment, another embodiment of the present invention further provides a 3DNAND, as shown in fig. 13, wherein the three-dimensional flash memory includes: the semiconductor device comprises a substrate, a first substrate and a second substrate, wherein a P-type well region is arranged in the substrate; a sidewall channel structure 25 located above the P-type well region 21; a first N-type doped layer 221 located above the sidewall channel structure 25; the storage stack structure 23 is located above the first N-type doped layer 221, and the storage stack structure 23 includes a plurality of first dielectric layers 231 and gate layers 233 alternately arranged; a channel hole structure 24 penetrating the storage stack structure 23, the channel hole structure 24 extending into the P-type well region 21; the trench hole structure 24 includes: a channel hole 241 penetrating the storage stack structure 23; a gate dielectric layer 242 disposed on the surface of the channel hole 241; a channel layer 243 disposed on the surface of the gate dielectric layer 242; and a channel filling medium 244 filled in the gap of the channel layer 243.
The sidewall channel structure 25 includes a second N-type doped layer 251 and a P-type doped layer 252, wherein the second N-type doped layer 251 is located between the first N-type doped layer 251 and the P-type doped layer 252; the sidewall channel structure 25 is connected to the channel layer 243.
In the 3D NAND, doping elements in the first N-type doping layer 221 are diffused to the sidewall channel structure 25 to form the second N-type doping layer 251; doping elements in the P-type well region 21 are diffused to the sidewall channel structure 25 to form the P-type doping layer 252.
In the 3D NAND, the doping concentration of the first N-type doping layer 221 is greater than that of the second N-type doping layer 251; the doping concentration of the P-well region 21 is greater than the doping concentration of the P-doped layer 252.
The 3D NAND provided by the embodiment of the invention can realize independent transmission of electrons and holes, the side wall channel structure 25 is easy to conduct, the requirement on the BSG of the lower selection tube is low, and the control capability in the horizontal direction and the vertical direction is not required to be considered at the same time. The doping concentration of the first N-type doping layer with the N-type heavy doping is increased to form a second N-type doping layer with higher doping concentration, so that the second N-type doping layer is easy to be in a conducting state in the required operation process.
The embodiments in the present description are described in a progressive manner, or in a parallel manner, or in a combination of a progressive manner and a parallel manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments can be referred to each other. For the 3D NAND disclosed in the embodiment, since it corresponds to the manufacturing method disclosed in the embodiment, the description is relatively simple, and the relevant points can be referred to the description of the manufacturing method.
It should be noted that in the description of the present invention, it is to be understood that the terms "upper", "lower", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only used for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A method for manufacturing a three-dimensional flash memory is characterized by comprising the following steps:
providing a substrate, wherein the substrate is internally provided with a P-type well region;
forming a functional layer above the P-type well region, wherein the functional layer comprises a first N-type doped layer and a sacrificial layer positioned between the substrate and the first N-type doped layer;
forming a storage stack on the functional layer;
forming a channel hole structure penetrating through the storage stack structure and the functional layer, the channel hole structure extending into the P-type well region; the trench hole structure includes: a channel hole through the storage stack structure; the gate dielectric layer is arranged on the surface of the channel hole; the channel layer is arranged on the surface of the gate dielectric layer; and a channel filling medium filled in the channel layer gap;
forming a side wall channel structure between the first N-type doped layer and the P-type trap region based on the functional layer; the side wall channel structure comprises a second N-type doped layer and a P-type doped layer, and the second N-type doped layer is positioned between the first N-type doped layer and the P-type doped layer; the side wall channel structure is connected with the channel layer.
2. The method according to claim 1, wherein the first N-type doped layer has a doping concentration greater than that of the second N-type doped layer;
the doping concentration of the P-type well region is greater than that of the P-type doping layer.
3. The manufacturing method according to claim 1, wherein the forming method of the side wall channel structure comprises the following steps:
removing the sacrificial layer and the gate dielectric layer between the first N-type doped layer and the P-type well region to expose the channel layer;
forming an undoped side wall channel structure between the first N-type doped layer and the P-type well region;
and diffusing doping elements in the first N-type doping layer and the P-type well region to an undoped side wall channel structure to form the second N-type doping layer and the P-type doping layer.
4. The method of claim 3, wherein the sacrificial layer comprises an undoped polysilicon layer having a first SiOxNy layer between the polysilicon layer and the P-type well region and a second SiOxNy layer between the first N-type doped layer;
the method for removing the sacrificial layer comprises the following steps:
forming a trench penetrating through the stacked structure, the trench penetrating through the first N-type doped layer and the second SiOxNy layer to expose the polysilicon layer;
and removing the first SiOxNy layer and the second SiOxNy layer after removing the polysilicon layer and the gate dielectric layer between the first N-type doped layer and the P-type trap region.
5. The method of claim 4, wherein after forming the second N-doped layer and the P-doped layer, further comprising:
and forming an N-type doped region at the bottom of the groove, wherein the N-type doping is connected with the second N-type doped layer or the first N-type doped layer and the second N-type doped layer simultaneously, and the N-type doped region is connected with an external circuit through an array common source line.
6. The method of manufacturing according to claim 1, wherein the storage stack structure comprises a plurality of layers of first dielectric layers and second dielectric layers alternately arranged;
after the second N-type doped layer and the P-type doped layer are formed, the method further includes:
removing the second dielectric layers to form gaps between the adjacent first dielectric layers;
and filling metal in the gap to form a gate layer.
7. The method as claimed in claim 1, wherein the second N-type doped layer and the P-type doped layer have the same thickness, and both thicknesses are greater than 0.
8. A three-dimensional flash memory, comprising:
the semiconductor device comprises a substrate, a first substrate and a second substrate, wherein a P-type well region is arranged in the substrate;
the side wall channel structure is positioned above the P-type well region;
the first N-type doping layer is positioned above the side wall channel structure;
the storage stacking structure is positioned above the first N-type doping layer and comprises a plurality of layers of first dielectric layers and gate layers which are alternately arranged;
a channel hole structure extending through the storage stack structure, the channel hole structure extending into the P-type well region; the trench hole structure includes: a channel hole through the storage stack structure; the gate dielectric layer is arranged on the surface of the channel hole; the channel layer is arranged on the surface of the gate dielectric layer; and a channel filling medium filled in the channel layer gap;
the side wall channel structure comprises a second N-type doped layer and a P-type doped layer, wherein the second N-type doped layer is positioned between the first N-type doped layer and the P-type doped layer; the side wall channel structure is connected with the channel layer.
9. The three-dimensional flash memory according to claim 8, wherein the doping element in the first N-type doping layer is diffused into the sidewall channel structure to form the second N-type doping layer;
and the doping elements in the P-type well region are diffused to the side wall channel structure to form the P-type doping layer.
10. The three-dimensional flash memory according to claim 8, wherein the first N-type doped layer has a doping concentration greater than the second N-type doping;
the doping concentration of the P-type well region is greater than that of the P-type doping layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010298632.6A CN111370424B (en) | 2020-04-16 | 2020-04-16 | Three-dimensional flash memory and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010298632.6A CN111370424B (en) | 2020-04-16 | 2020-04-16 | Three-dimensional flash memory and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111370424A true CN111370424A (en) | 2020-07-03 |
| CN111370424B CN111370424B (en) | 2022-09-27 |
Family
ID=71212585
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010298632.6A Active CN111370424B (en) | 2020-04-16 | 2020-04-16 | Three-dimensional flash memory and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111370424B (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105470260A (en) * | 2015-12-03 | 2016-04-06 | 中国科学院微电子研究所 | Three-dimensional semiconductor device and manufacturing method therefor |
| CN105977257A (en) * | 2015-03-11 | 2016-09-28 | 爱思开海力士有限公司 | Semiconductor device and manufacturing method thereof |
| US9741737B1 (en) * | 2016-04-15 | 2017-08-22 | Micron Technology, Inc. | Integrated structures comprising vertical channel material and having conductively-doped semiconductor material directly against lower sidewalls of the channel material |
| US20180366488A1 (en) * | 2017-06-16 | 2018-12-20 | SK Hynix Inc. | Semiconductor device and manufacturing method thereof |
| US20190067312A1 (en) * | 2017-08-31 | 2019-02-28 | Toshiba Memory Corporation | Semiconductor device and method for manufacturing same |
| CN109560083A (en) * | 2017-09-25 | 2019-04-02 | 爱思开海力士有限公司 | Semiconductor devices |
| CN109727995A (en) * | 2019-02-28 | 2019-05-07 | 长江存储科技有限责任公司 | Form the method and three-dimensional storage of three-dimensional storage |
| CN110289267A (en) * | 2018-03-19 | 2019-09-27 | 三星电子株式会社 | Wherein with the memory device and its manufacturing method of vertically extending channel structure |
| CN110785851A (en) * | 2017-08-04 | 2020-02-11 | 闪迪技术有限公司 | Three-dimensional memory device employing direct source contact and hole current detection and method of fabricating the same |
| US20200051997A1 (en) * | 2018-08-10 | 2020-02-13 | SK Hynix Inc. | Semiconductor device and manufacturing method of a semiconductor device |
-
2020
- 2020-04-16 CN CN202010298632.6A patent/CN111370424B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105977257A (en) * | 2015-03-11 | 2016-09-28 | 爱思开海力士有限公司 | Semiconductor device and manufacturing method thereof |
| CN105470260A (en) * | 2015-12-03 | 2016-04-06 | 中国科学院微电子研究所 | Three-dimensional semiconductor device and manufacturing method therefor |
| US9741737B1 (en) * | 2016-04-15 | 2017-08-22 | Micron Technology, Inc. | Integrated structures comprising vertical channel material and having conductively-doped semiconductor material directly against lower sidewalls of the channel material |
| US20180366488A1 (en) * | 2017-06-16 | 2018-12-20 | SK Hynix Inc. | Semiconductor device and manufacturing method thereof |
| CN110785851A (en) * | 2017-08-04 | 2020-02-11 | 闪迪技术有限公司 | Three-dimensional memory device employing direct source contact and hole current detection and method of fabricating the same |
| US20190067312A1 (en) * | 2017-08-31 | 2019-02-28 | Toshiba Memory Corporation | Semiconductor device and method for manufacturing same |
| CN109560083A (en) * | 2017-09-25 | 2019-04-02 | 爱思开海力士有限公司 | Semiconductor devices |
| CN110289267A (en) * | 2018-03-19 | 2019-09-27 | 三星电子株式会社 | Wherein with the memory device and its manufacturing method of vertically extending channel structure |
| US20200051997A1 (en) * | 2018-08-10 | 2020-02-13 | SK Hynix Inc. | Semiconductor device and manufacturing method of a semiconductor device |
| CN110828468A (en) * | 2018-08-10 | 2020-02-21 | 爱思开海力士有限公司 | Semiconductor device and method for manufacturing semiconductor device |
| CN109727995A (en) * | 2019-02-28 | 2019-05-07 | 长江存储科技有限责任公司 | Form the method and three-dimensional storage of three-dimensional storage |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111370424B (en) | 2022-09-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107993996B (en) | Semiconductor device and method of manufacturing the same | |
| US5477071A (en) | MOS random access memory having array of trench type one-capacitor/one-transistor memory cells | |
| KR100640620B1 (en) | NOR type flash memory device having twin bit cell scheme | |
| KR900000181B1 (en) | Semiconductor memory device | |
| US11508749B2 (en) | Cutoff gate electrodes for switches for a three-dimensional memory device and method of making the same | |
| US9786675B2 (en) | Non-volatile memory devices including charge storage layers | |
| KR20150026054A (en) | Semiconductor device and method for fabricating the same | |
| US8274827B2 (en) | Memory device and operating method thereof | |
| US6686240B2 (en) | Semiconductor memory device having a multiple tunnel junction layer pattern and method of fabricating the same | |
| US7282761B2 (en) | Semiconductor memory devices having offset transistors and methods of fabricating the same | |
| CN113555367A (en) | Memory element and method for manufacturing the same | |
| KR20120051409A (en) | Semiconductor device with vertical channel transistor and method of operating the same | |
| US6998306B2 (en) | Semiconductor memory device having a multiple tunnel junction pattern and method of fabricating the same | |
| US20140284682A1 (en) | Nonvolatile semiconductor storage device | |
| CN111370424B (en) | Three-dimensional flash memory and manufacturing method thereof | |
| KR101362219B1 (en) | Memory cell string stack with common body and memory array using the same | |
| CN112310096A (en) | Semiconductor device with a plurality of semiconductor chips | |
| KR100517219B1 (en) | Dram cell arrangement with dynamic gain memory cells, and method for the production thereof | |
| JPS6136384B2 (en) | ||
| US20210398998A1 (en) | Semiconductor device | |
| KR101002246B1 (en) | Nor flash memory array with vertical channel builtin fin-split layer | |
| US20090184364A1 (en) | Non-volatile semiconductor storage device and method of manufacturing the same | |
| TWI796001B (en) | Semiconductor device and manufacturing method thereof | |
| CN116940120B (en) | NOR flash memory with pairing structure and manufacturing method thereof | |
| TWI780950B (en) | Semiconductor device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |