TWI796001B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device includes a peripheral circuit region, a substrate on the peripheral circuit region, and an array region on the substrate. The peripheral circuit region has complementary metal-oxide-semiconductor components. The substrate includes an N-type doped poly silicon layer on the peripheral circuit region, an oxide layer on the N-type doped poly silicon layer, and a conductive layer on the oxide layer. The array region includes gate structures and insulating layers alternately stacked on the conductive layer. A bottommost gate structure and the conductive layer together serve as a plurality ground select lines of the semiconductor device, and a ratio of a thickness of the conductive layer to a thickness of each of the gate structures is about from 3 to 4. The array region further includes a vertical channel structure penetrating the gate structures and the insulating layers and extending into the N-type doped poly silicon layer.

Description

Semiconductor device and manufacturing method thereof

The present disclosure relates to a semiconductor device and a manufacturing method thereof.

In recent years, the structure of semiconductor devices has been constantly changing, and the storage capacity of semiconductor devices has been increasing. Memory devices are used as storage elements in many products (such as digital cameras, mobile phones, and computers, etc.). As these applications increase, the demand for memory devices is focused on small size and large storage capacity. In order to satisfy this condition, a memory device with high device density and small size and its manufacturing method are required.

Therefore, it is desirable to develop a three-dimensional (3D) memory device with a greater number of stacked planes to achieve greater storage capacity, improve quality, and maintain a small size of the memory device.

According to some embodiments of the present disclosure, a semiconductor device includes a peripheral block, a substrate, and an array block. The peripheral block includes CMOS devices. The substrate is disposed on the peripheral block, and the substrate includes an N-type doped polysilicon layer disposed on the peripheral block, an oxide layer disposed on the N-type doped polysilicon layer, and a conductor layer disposed on the oxide layer . The array block is arranged on the substrate, and the array block includes a gate structure and an insulating layer arranged on the conductor layer and stacked alternately, wherein the bottommost one of the gate structure and the conductor layer are used as the ground selection line of the semiconductor device . The ratio of the thickness of the conductor layer to the thickness of each gate structure is about 3-4. The array block further includes a vertical channel structure, passing through the gate structure and the insulating layer, and extending into the N-type doped polysilicon layer.

According to some embodiments of the present disclosure, a method of fabricating a semiconductor device includes providing a structure, the structure including a peripheral block, a substrate, and an array block. The peripheral block includes CMOS devices. The substrate is disposed on the peripheral block, and the substrate includes a first polysilicon layer disposed on the peripheral block, a first oxide layer disposed on the first polysilicon layer, and a first oxide layer disposed on the first oxide layer. The second polysilicon layer, the second oxide layer disposed on the second polysilicon layer, the third polysilicon layer disposed on the second oxide layer, the third polysilicon layer disposed on the The third oxide layer, and the fourth polysilicon layer disposed on the third oxide layer. The array block is arranged on the base material, and the array block includes a first insulating layer and a second insulating layer arranged on the fourth polysilicon layer and stacked alternately, and passes through the first insulating layer and the second insulating layer and extends into the vertical channel structure of the first polysilicon layer. The method further includes removing the fourth polysilicon layer to form a first cavity between the third oxide layer and the bottommost one of the first insulating layers, and filling the first cavity with a conductive layer.

The following will clearly illustrate the spirit of the disclosure with drawings and detailed descriptions. Anyone with ordinary knowledge in the technical field can make changes and modifications based on the techniques taught in the disclosure after understanding the preferred embodiments of the disclosure. It does not depart from the spirit and scope of this disclosure.

Referring to FIG. 1 to FIG. 14 , they are cross-sectional views at different manufacturing stages of some embodiments of the method for manufacturing a semiconductor device according to the present disclosure. Referring to FIG. 1 , a semiconductor structure 10 is provided. The semiconductor structure 10 includes a substrate 100 , a peripheral block 200 disposed below the substrate 100 , and an array block 300 disposed above the substrate 100 . That is, the peripheral block 200 and the array block 300 are respectively disposed on two opposite sides of the substrate 100 . In some embodiments, the substrate 100 is formed on the upper surface of the peripheral block 200 , and then the array block 300 is formed on the upper surface of the substrate 100 . In some other embodiments, the array block 300 is firstly formed on the upper surface of the substrate 100 , and then the substrate 100 and the array block 300 thereon are combined with the peripheral block 200 together.

The peripheral block 200 includes a plurality of semiconductor devices, such as a plurality of complementary metal-oxide-semiconductor (CMOS) devices 210 and other suitable circuits.

The substrate 100 can be, for example, a silicon substrate. The substrate 100 includes a first polysilicon layer 101 on the peripheral block 200 , a first oxide layer 111 on the first polysilicon layer 101 , a second polysilicon layer on the first oxide layer 111 Silicon layer 102, second oxide layer 112 on the second polysilicon layer 102, third polysilicon layer 103 on the second oxide layer 112, third polysilicon layer 103 on the third an oxide layer 113 , and a fourth polysilicon layer 104 on the third oxide layer 113 .

In some embodiments, the first polysilicon layer 101 is the thickest one among the first polysilicon layer 101 to the fourth polysilicon layer 104 of the substrate 100, and the third polysilicon layer 103 is The thinnest one among the first polysilicon layer 101 to the fourth polysilicon layer 104 of the substrate 100 . In some embodiments, the thickness of the first polysilicon layer 101 is about 1500Å, the thickness of the second polysilicon layer 102 is about 400Å, the thickness of the third polysilicon layer 103 is about 100Å, and the fourth polysilicon layer Layer 104 has a thickness of about 1000 Å. In some embodiments, the thickness of the first oxide layer 111 is about 80 Å, the thickness of the second oxide layer 112 is about 120 Å, and the thickness of the third oxide layer 113 is about 450 Å.

The first polysilicon layer 101 may be doped with N-type dopants, such as phosphorus or arsenic. The fourth polysilicon layer 104 may be doped with P-type dopants, such as boron or germanium. In some embodiments, the fourth polysilicon layer 104 serves as a ground select line (GSL) of the semiconductor device.

The array block 300 includes a plurality of first insulating layers 310 and a plurality of second insulating layers 320 alternately stacked on the substrate 100, wherein both the uppermost layer and the lowermost layer are the first insulating layers 310, and the second The material of an insulating layer 310 is different from that of the second insulating layer 320 . In some embodiments, the first insulating layer 310 may be an oxide layer, such as a silicon oxide layer, and the second insulating layer 320 may be a nitride layer, such as a silicon nitride layer.

The array block 300 further includes a plurality of vertical channel structures 330 , and the vertical channel structures 330 are arranged parallel to the normal direction of the substrate 100 . The vertical channel structure 330 is formed through the stack of the first insulating layer 310 and the second insulating layer 320 and extends into the substrate 100 . In some embodiments, the vertical channel structure 330 ends at the first polysilicon layer 101 .

In some embodiments, each vertical channel structure 330 includes a storage layer 332 , a channel layer 334 and isolation columns 336 . The channel layer 334 is sandwiched between the storage layer 332 and the isolation posts 336 . The storage layer 332 and the channel layer 334 have a U-shaped cross-section. In some embodiments, the storage layer 332 is a multi-layer structure, such as an oxide-nitride-oxide (ONO) layer, for trapping electrons. The material of the channel layer 334 can be polysilicon, and the material of the isolation column 336 is an insulating material. Each vertical channel structure 330 further includes a conductive plug 338 disposed on the isolation pillar 336 and in contact with the channel layer 334 . In some embodiments, the conductive plug 338 , the storage layer 332 , the channel layer 334 are substantially flush with the top surface of the uppermost first insulating layer 310 . The upper surface of the isolation pillar 336 is lower than the upper surface of the channel layer 334 , and the sidewall of the conductive plug 338 is in contact with the channel layer 334 .

Referring to FIG. 2 , one or more etching processes are performed to form trenches 340 in the array block 300 . For example, performing the first etching process can remove part of the first insulating layer 310 , the second insulating layer 320 and the fourth polysilicon layer 104 . That is, after the first etching process is performed, the trench 340 stops at the fourth polysilicon layer 104 . Next, a second etching process is performed to deepen the trench 340 so that the trench 340 stops at the third oxide layer 113 . That is, the third oxide layer 113 serves as an etch stop layer in the second etch process. In some embodiments, the first etching process is different from the second etching process.

Referring to FIG. 3, a third etching process is performed to remove the fourth polysilicon layer 104 (see FIG. 2). After the third etching process is performed, the cavity 342 is formed between the bottommost first insulating layer 310 and the third oxide layer 113 . The cavity 342 communicates with the groove 340 . Part of the vertical channel structure 330 is exposed to the cavity 342 . In some embodiments, the third etching process is different from the first etching process and the second etching process.

Referring to FIG. 4, a conductor layer 362 is formed to fill the cavity 342 (see FIG. 3). The conductive layer 362 includes one or more conductive materials, such as tungsten and other filling metals. The conductor layer 362 is disposed around the portion of the vertical channel structure 330 . After the conductive layer 362 fills the cavity 342 , at least one etching process is further performed through the trench 340 to remove part of the conductive layer 362 so as to deepen the trench 340 . The etching process for deepening the trench 340 stops at the third oxide layer 113 . So far, the sidewalls of the first insulating layer 310 , the second insulating layer 320 and the conductive layer 362 are exposed to the trench 340 .

Referring to Figure 5, another etch process is performed to further deepen the trench slot 340 . The etching process removes part of the third oxide layer 113 and the third polysilicon layer 103 and ends at the second oxide layer 112 . That is, the second oxide layer 112 serves as an etch stop layer for this etching process.

Referring to FIG. 6 , spacers 350 are formed on sidewalls of the trenches 340 . In some embodiments, a spacer material is firstly formed on the top surface and side surfaces of the semiconductor structure 10 as shown in FIG. 5 . In some embodiments, the spacer 350 is a multilayer structure and includes a first nitride layer 352 , an oxide layer 354 , and a second nitride layer 356 , wherein the first nitride layer 352 is directly formed on the surface of the trench 340 Above, the oxide layer 354 is sandwiched between the first nitride layer 352 and the second nitride layer 356 . Surfaces of the first insulating layer 310 , the second insulating layer 320 , the conductive layer 362 , the third oxide layer 113 and the third polysilicon layer 103 are protected by spacers 350 .

After the surfaces of the first insulating layer 310, the second insulating layer 320, the conductor layer 362, the third oxide layer 113 and the third polysilicon layer 103 are protected by the spacer 350, another etching process is performed to again Groove 340 is deepened. This etching process removes the bottom of the spacer 350 and part of the second oxide layer 112 and the second polysilicon layer 102 , and stops at the second polysilicon layer 102 . The trench 340 does not penetrate the second polysilicon layer 102 .

Referring to FIG. 7, the second polysilicon layer 102 (see FIG. 6) is removed by wet etching. The second polysilicon layer 102 can also be regarded as a sacrificial layer. After the second polysilicon layer 102 is removed, a cavity 344 is formed between the first oxide layer 111 and the second oxide layer 112 . The portion of the vertical channel structure 330 between the first oxide layer 111 and the second oxide layer 112 is exposed to the cavity 344 .

Referring to FIG. 8 , a series of etching processes are performed to remove the exposed portion of the storage layer 332 of the vertical channel structure 330 . For example, a first etchant, which etches oxide at a rate greater than nitride, and a second etchant, which etch nitride at a rate greater than oxide, can be used to remove exposed The part of the storage layer 332, wherein the storage layer 332 is an oxide-nitride-oxide layer. While removing the exposed portion of the storage layer 332 (ie, the oxide-nitride-oxide layer), the oxide layer 354 and the second nitride layer 356 (see FIG. 7 ) and the first nitride layer 356 of the spacer 350 The first oxide layer 111 and the second oxide layer 112 (see FIG. 7 ) are also removed during the process. Therefore, the cavity 344 is enlarged after the removal step described above. The first nitride layer 352 of the spacer 350 still remains on the sidewall of the trench 340 .

In some embodiments, not only the exposed portion of the storage layer 332 is removed, but also the end of the portion of the storage layer 332 covered by the first polysilicon layer 101 and the third polysilicon layer 103 is removed. Correspondingly, the exposed portion of the storage layer 332 is recessed after removal. In some embodiments, the storage layer 332 includes an upper section 332U and a lower section 332L, wherein the upper section 332U and the lower section 332L are separated by a cavity 344 .

In some embodiments, the upper surface of the lower section 332L of the storage layer 332 is lower than the topmost surface of the first polysilicon layer 101 . In some embodiments, the lower surface of the upper section 332U of the storage layer 332 is higher than the bottommost surface of the third polysilicon layer 103 and higher than the bottom surface of the third oxide layer 113 . In some embodiments, the third polysilicon layer 103 is adjacent to the storage layer 332 A part is also removed when removing the exposed part of the storage layer 332 .

Referring to FIG. 9 , additional polysilicon material 105 is epitaxially grown in cavity 344 (see FIG. 8 ) and backfills cavity 344 . The polysilicon material 105 can be doped with N-type dopants, such as phosphorus or arsenic. The combination of the remaining third polysilicon layer 103 , the polysilicon material 105 and the first polysilicon layer 101 is collectively called the N-type doped polysilicon layer 106 . The thickness of the N-type doped polysilicon layer 106 is about 2200Å. The N-type doped polysilicon layer 106 and the conductive layer 362 are separated by the third oxide layer 113 . In other words, the third oxide layer 113 acts as an isolation layer between the N-type doped polysilicon layer 106 and the conductive layer 362 .

After the N-type doped polysilicon layer 106 is formed, an etching process is performed to remove part of the N-type doped polysilicon layer 106 to deepen the trench 340 . In some embodiments, the bottom of the trench 340 is located between the upper section 332U and the lower section 332L of the storage layer 332 . The portion of the channel layer 334 between the upper section 332U and the lower section 332L of the storage layer 332 directly contacts the N-type doped polysilicon layer 106 .

Referring to FIG. 10, the first nitride layer 352 (see FIG. 9) of the spacer 350 is removed, so that the stacked first insulating layer 310, second insulating layer 320, conductor layer 362, and N-type doped polysilicon Sidewalls of layer 106 are exposed to trench 340 .

Referring to FIG. 11 , an oxidation process, such as a thermal oxidation process, is performed to convert the surface of the N-type doped polysilicon layer 106 into silicon oxide, and a fourth oxide layer 114 is formed on the sidewall of the N-type doped polysilicon layer 106 . In some embodiments, the fourth oxide layer 114 has a U-shaped cross-section, And the fourth oxide layer 114 is connected to the third oxide layer 113 .

Referring to FIG. 12, an etching process is performed to remove the second insulating layer 320 (see FIG. 11). More specifically, the second insulating layer 320 is a silicon nitride layer, and the etching process is to select an etchant whose etching rate of nitride is higher than that of oxide, so that the first insulating layer 310 of the silicon oxide layer is formed on the second insulating layer. 320 remained after it was removed. Part of the vertical channel structure 330 is exposed between the first insulating layers 310 . Since the sidewalls of the N-type doped polysilicon layer 106 are covered by the fourth oxide layer 114 and the third oxide layer 113 , the N-type doped polysilicon layer 106 can be protected from damage during the etching process.

Referring to FIG. 13 , a plurality of gate structures 360 are formed between the first insulating layers 310 and adjacent to the vertical channel structures 330 . Each gate structure 360 includes a fill metal of conductive material, such as tungsten.

In some embodiments, one or more gate structures 360 on the top of the semiconductor structure 10 serve as string select lines (SSL) for the semiconductor structure 10 , and one or more gate structures 360 on the bottom of the semiconductor structure 10 The gate structure 360 and the conductor layer 362 together serve as a ground select line (GSL) of the semiconductor structure 10 , while the remaining gate structures 360 serve as word lines (WL) of the semiconductor structure 10 . The gate structure 360 and the conductor layer 362 are respectively disposed around the vertical channel structure 330 . Therefore, the cells in the array block 300 may be referred to as gate-all-around (GAA) memory cells.

In some embodiments, the thickness T1 of the conductor layer 362 is greater than each Thickness T2 of each gate structure 360 . In some embodiments, the thickness T1 of the conductive layer 362 is about 1000 Å, and the thickness T2 of each gate structure 360 is about 300 Å. In some embodiments, the ratio between the thickness T1 of the conductive layer 362 and the thickness T2 of each gate structure 360 is about 3-4. In some embodiments, the thickness T1 of the conductive layer 362 is smaller than the thickness T3 of the N-type doped polysilicon layer 106 .

After the gate structure 360 and the conductive layer 362 are formed, an etch-back process is performed to recess the gate structure 360 and the conductive layer 362 so that the sidewalls of the gate structure 360 and the conductive layer 362 are recessed from the sidewalls of the first insulating layer 310 . In some embodiments, the recess depths of the sidewalls of the gate structure 360 and the conductive layer 362 from the sidewalls of the first insulating layer 310 may be different. The sidewalls of the gate structure 360 and the conductive layer 362 can be flat, convex, or concave after the etch-back process.

Referring to FIG. 14, additional oxide material is deposited on the sidewalls of the gate structure 360, the first insulating layer 310, and the fourth oxide layer 114 (see FIG. 13). Next, an etching process is performed to remove part of the oxide material and the bottom portion of the fourth oxide layer 114 to open the fourth oxide layer 114 . In this way, an insulating spacer 370 is formed surrounding the trench 340 (see FIG. 11 ), and the N-type doped polysilicon layer 106 is exposed from the opened fourth oxide layer 114 .

Next, a deposition process is performed to form a common source line (CSL) 372 in the trench 340 that fills the trench 340 and is surrounded by insulating spacers 370 . The bottom surface of the insulating spacer 370 is lower than the upper surface of the N-type doped polysilicon layer 106 . in some real In an embodiment, the common source line 372 may be polysilicon doped with N-type dopants, such as phosphorus or arsenic. In other embodiments, the common source line 372 can be a conductor such as tungsten. The common source line 372 is deposited upward from the N-type doped polysilicon layer 106 , wherein the N-type doped polysilicon layer 106 serves as a common source plane of the semiconductor structure 10 . Next, a metal plug 374 is formed to connect to the common source line 372 .

Referring to FIG. 15 , it is an enlarged view of region A in the semiconductor structure 10 of FIG. 14 . In some embodiments, the third oxide layer 113 has a first portion 113a surrounding the upper section 332U of the storage layer 332 and a second portion 113b connected to the first portion 113a. The thickness T4 of the first portion 113a is smaller than the thickness T5 of the second portion 113b. The bottom surface of the first portion 113 a of the third oxide layer 113 is substantially flush with the bottom surface of the upper section 332U of the storage layer 332 . In some embodiments, the bottom surface of the first portion 113a of the third oxide layer 113 and the bottom surface of the upper section 332U of the storage layer 332 may be flat, concave, or convex. In some embodiments, the conductive layer 362 is closer to the common source line 372 than the gate structure 360 . That is, the distance d1 between the sidewall of the conductive layer 362 and the common source line 372 is smaller than the distance d2 between the sidewall of the gate structure 360 and the common source line 372 .

Please refer to FIG. 14 and FIG. 15 at the same time, the fabricated semiconductor structure 10 can be used as a semiconductor device having a plurality of memory cells. At least one gate structure 360 located at the bottom of the semiconductor structure 10 and the conductive layer 362 together serve as a ground select line (GSL) of the semiconductor structure 10 . N-type doped polysilicon layer 106 as a semiconductor The common source plane of the bulk structure 10 . The distance between the N-type doped polysilicon layer 106 and the ground selection line GSL (that is, the N-type doped polysilicon layer 106 and the conductive layer 362 ) is extremely short. In some embodiments, the distance between the conductive layer 362 and the N-type doped polysilicon layer 106 is the thickness T4 of the first portion 113 a of the third oxide layer 113 , which is only about 300 Å. Therefore, the thermal budget required to diffuse the N-type dopant in the N-type doped polysilicon layer 106 is correspondingly reduced. In addition, using the conductive layer 362 as the bottom conductive layer of the ground selection line GSL, compared with the case without the bottom conductive layer, using the conductive layer 362 as the bottom conductive layer of the ground selection line GSL can improve memory performance. Erase speed of cells and reduce leakage current.

Although this disclosure has been disclosed as above with the embodiment, it is not intended to limit this disclosure. Anyone who is familiar with this technology can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, the protection of this disclosure The scope shall be defined by the appended patent application scope.

10:Semiconductor structure

100: Substrate

101: the first polysilicon layer

102: the second polysilicon layer

103: the third polysilicon layer

104: the fourth polysilicon layer

105: Polysilicon material

106: N-type doped polysilicon layer

111: the first oxide layer

112: second oxide layer

113: The third oxide layer

113a: Part I

113b: Part II

114: the fourth oxide layer

200: Surrounding blocks

210: Complementary metal oxide semiconductor element

300: array block

310: the first insulating layer

320: second insulating layer

330: Vertical channel structure

332: storage layer

332U: upper section

332L: Lower section

334: channel layer

336: isolation column

338: Conductive embolism

340: Groove

342,344: cavities

350: spacer

352: the first nitride layer

354: oxide layer

356: Second nitride layer

360:Gate structure

362: conductor layer

370: insulating spacer

372: Shared source line

374: metal plug

d1, d2: distance

T1, T2, T3, T4, T5: Thickness

A: area

In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more comprehensible, the detailed description of the accompanying drawings is as follows: FIG. 1 to FIG. 14 are cross-sectional views of some embodiments of the method for manufacturing a semiconductor device according to the present disclosure at different manufacturing stages. FIG. 15 is an enlarged view of region A of the semiconductor structure in FIG. 14 .

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

10:Semiconductor structure

100: Substrate

106: N-type doped polysilicon layer

200: Surrounding blocks

300: array block

310: the first insulating layer

360:Gate structure

362: conductor layer

370: insulating spacer

372: Shared source line

374: metal plug

A: area

Claims (10)

A semiconductor device comprising: a peripheral block, including a plurality of complementary metal oxide semiconductor devices; A base material is disposed on the peripheral block, the base material includes: an N-type doped polysilicon layer disposed on the peripheral block; an oxide layer disposed on the N-type doped polysilicon layer; and a conductive layer disposed on the oxide layer; and An array block is arranged on the substrate, and the array block includes: A plurality of gate structures and a plurality of insulating layers stacked alternately are arranged on the conductor layer, wherein the lowest one of the gate structures and the conductor layer serve as a ground selection line of the semiconductor device, wherein the conductor the ratio of the thickness of the layer to the thickness of each of the gate structures is about 3 to 4; and A vertical channel structure passes through the gate structures and the insulating layers, and extends into the N-type doped polysilicon layer. The semiconductor device according to claim 1, wherein a part of a channel layer of the vertical channel structure contacts the N-type doped polysilicon layer. The semiconductor device as claimed in claim 2, wherein a storage layer of the vertical channel structure includes an upper section surrounding the top of the channel layer and a lower section surrounding the bottom of the channel layer, and the vertical channel structure The portion of the channel layer is between the upper section and the lower section. The semiconductor device as claimed in claim 3, wherein the oxide layer includes a first portion adjacent to the upper section of the storage layer and a second portion connected to the first portion, wherein the thickness of the first portion is smaller than that of the second portion part thickness. The semiconductor device described in claim 1 further includes: a common source line passing through the array block and extending into the substrate, wherein the distance between the conductor layer and the common source line is smaller than the distance between the gate structures and the common source line . A method of fabricating a semiconductor device, comprising: Provide a structure that contains: a peripheral block, including a plurality of complementary metal oxide semiconductor devices; A base material is disposed on the peripheral block, the base material includes: a first polysilicon layer disposed on the peripheral block; a first oxide layer disposed on the first polysilicon layer; a second polysilicon layer disposed on the first oxide layer; a second oxide layer disposed on the second polysilicon layer; a third polysilicon layer disposed on the second oxide layer; a third oxide layer disposed on the third polysilicon layer; and a fourth polysilicon layer disposed on the third oxide layer; and An array block is arranged on the substrate, and the array block includes: A plurality of first insulating layers and a plurality of second insulating layers stacked alternately are disposed on the fourth polysilicon layer; and a vertical channel structure passing through the first insulating layers and the second insulating layers and extending into the first polysilicon layer; removing the fourth polysilicon layer to form a first cavity between the third oxide layer and a lowermost one of the first insulating layers; and The first cavity is filled with a conductor layer. The method according to claim 6, wherein removing the fourth polysilicon layer comprises: forming a trench in the structure to expose the fourth polysilicon layer; and Etching the fourth polysilicon layer. The method as described in claim item 7 further includes: deepening the trench to expose the second oxide layer; After deepening the trench, forming a spacer on the sidewall of the trench; deepening the trench again to expose the second polysilicon layer; removing the second polysilicon layer; and The first oxide layer and the second oxide layer are removed. The method of claim 8, wherein removing the first oxide layer and the second oxide layer further comprises: A portion of a storage layer of the vertical channel structure and a portion of the spacer are removed such that a second cavity is formed between the first polysilicon layer and the third polysilicon layer. The method as described in claim item 9 further includes: The second cavity is filled with an N-type doped polysilicon.

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